Re: [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
On 8/16/19 8:38 AM, tony.ngu...@bt.com wrote:
> Preparation for collapsing the two byte swaps adjust_endianness and
> handle_bswap into the former.
>
> Call memory_region_dispatch_{read|write} with endianness encoded into
> the "MemOp op" operand.
>
> This patch does not change any behaviour as
> memory_region_dispatch_{read|write} is yet to handle the endianness.
>
> Once it does handle endianness, callers with byte swaps can collapse
> them into adjust_endianness.
>
> Signed-off-by: Tony Nguyen
> ---
> accel/tcg/cputlb.c | 6 --
> exec.c | 5 +++--
> hw/intc/armv7m_nvic.c| 15 ---
> hw/s390x/s390-pci-inst.c | 6 --
> hw/vfio/pci-quirks.c | 5 +++--
> hw/virtio/virtio-pci.c | 6 --
> memory_ldst.inc.c| 18 --
> 7 files changed, 38 insertions(+), 23 deletions(-)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index 6c83878..0aff6a3 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
> *iotlbentry,
> qemu_mutex_lock_iothread();
> locked = true;
> }
> -r = memory_region_dispatch_read(mr, mr_offset, , size_memop(size),
> +r = memory_region_dispatch_read(mr, mr_offset, ,
> +size_memop(size) | MO_TE,
> iotlbentry->attrs);
> if (r != MEMTX_OK) {
> hwaddr physaddr = mr_offset +
> @@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
> *iotlbentry,
> qemu_mutex_lock_iothread();
> locked = true;
> }
> -r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
> +r = memory_region_dispatch_write(mr, mr_offset, val,
> + size_memop(size) | MO_TE,
> iotlbentry->attrs);
Ok. Conversion to target-endian via handle_bswap() in the callers.
> diff --git a/exec.c b/exec.c
> index 303f9a7..562fb5b 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView
> *fv, hwaddr addr,
> potential bugs */
> val = ldn_p(buf, l);
> result |= memory_region_dispatch_write(mr, addr1, val,
> - size_memop(l), attrs);
> + size_memop(l) | MO_TE,
> + attrs);
> } else {
> /* RAM case */
> ptr = qemu_ram_ptr_length(mr->ram_block, addr1, , false);
> @@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr
> addr,
> release_lock |= prepare_mmio_access(mr);
> l = memory_access_size(mr, l, addr1);
> result |= memory_region_dispatch_read(mr, addr1, ,
> - size_memop(l), attrs);
> + size_memop(l) | MO_TE,
> attrs);
> stn_p(buf, l, val);
Ok. Please add comments:
/*
* TODO: Merge bswap from ldn_p into memory_region_dispatch_write
* by using ldn_he_p and dropping MO_TE to get a host-endian value.
*/
and similar for the store.
This must be delayed until after patch 38, when the MO_BSWAP component of the
MemOp is operated on by memory_region_dispatch_*.
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,
> hwaddr addr,
> if (attrs.secure) {
> /* S accesses to the alias act like NS accesses to the real region */
> attrs.secure = 0;
> -return memory_region_dispatch_write(mr, addr, value,
> size_memop(size),
> -attrs);
> +return memory_region_dispatch_write(mr, addr, value,
> +size_memop(size) | MO_TE, attrs);
> } else {
> /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> if (attrs.user) {
> @@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque,
> hwaddr addr,
> if (attrs.secure) {
> /* S accesses to the alias act like NS accesses to the real region */
> attrs.secure = 0;
> -return memory_region_dispatch_read(mr, addr, data, size_memop(size),
> - attrs);
> +return memory_region_dispatch_read(mr, addr, data,
> + size_memop(size) | MO_TE, attrs);
> } else {
> /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> if (attrs.user) {
> @@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque,
> hwaddr addr,
>
> /* Direct the access to the correct systick */
> mr =
[Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.
This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.
Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.
Signed-off-by: Tony Nguyen
---
accel/tcg/cputlb.c | 6 --
exec.c | 5 +++--
hw/intc/armv7m_nvic.c| 15 ---
hw/s390x/s390-pci-inst.c | 6 --
hw/vfio/pci-quirks.c | 5 +++--
hw/virtio/virtio-pci.c | 6 --
memory_ldst.inc.c| 18 --
7 files changed, 38 insertions(+), 23 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..0aff6a3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
-r = memory_region_dispatch_read(mr, mr_offset, , size_memop(size),
+r = memory_region_dispatch_read(mr, mr_offset, ,
+size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
-r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+r = memory_region_dispatch_write(mr, mr_offset, val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
diff --git a/exec.c b/exec.c
index 303f9a7..562fb5b 100644
--- a/exec.c
+++ b/exec.c
@@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView *fv,
hwaddr addr,
potential bugs */
val = ldn_p(buf, l);
result |= memory_region_dispatch_write(mr, addr1, val,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE,
+ attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, , false);
@@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr
addr,
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
result |= memory_region_dispatch_read(mr, addr1, ,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE,
attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 975d7cc..e150f9a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,
hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
-return memory_region_dispatch_write(mr, addr, value, size_memop(size),
-attrs);
+return memory_region_dispatch_write(mr, addr, value,
+size_memop(size) | MO_TE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque,
hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
-return memory_region_dispatch_read(mr, addr, data, size_memop(size),
- attrs);
+return memory_region_dispatch_read(mr, addr, data,
+ size_memop(size) | MO_TE, attrs);
} else {
/* NS attrs are RAZ/WI for privileged, and BusFault for user */
if (attrs.user) {
@@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque,
hwaddr addr,
/* Direct the access to the correct systick */
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(>systick[attrs.secure]), 0);
-return memory_region_dispatch_write(mr, addr, value, size_memop(size),
-attrs);
+return memory_region_dispatch_write(mr, addr, value,
+size_memop(size) | MO_TE, attrs);
}
static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
@@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr
addr,
/* Direct the
