Re: [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu

[Jia Liu]

Hi Andreas,

Thank you for comment.
I've tried fix them, but I'm afraid I didn't fully understand what you mean.
Please read the new code and give me some comment, please.

On Thu, Jul 5, 2012 at 9:22 PM, Andreas Färber  wrote:
> Am 01.07.2012 04:45, schrieb Jia Liu:
>> Add OpenRISC target stubs and cpu support.
>>
>> Signed-off-by: Jia Liu 
>> ---
>>  arch_init.c  |2 +
>>  arch_init.h  |1 +
>>  configure|   14 +-
>>  cpu-exec.c   |2 +
>>  default-configs/or32-softmmu.mak |4 +
>>  elf.h|2 +
>>  hw/openrisc/Makefile.objs|1 +
>>  poison.h |1 +
>>  target-openrisc/Makefile.objs|3 +
>>  target-openrisc/cpu.c|  236 +++
>>  target-openrisc/cpu.h|  286 
>> ++
>>  target-openrisc/intrpt.c |   30 
>>  target-openrisc/machine.c|   30 
>>  target-openrisc/mmu.c|   39 ++
>>  target-openrisc/mmu_helper.c |   43 ++
>>  target-openrisc/translate.c  |   75 ++
>>  16 files changed, 767 insertions(+), 2 deletions(-)
>>  create mode 100644 default-configs/or32-softmmu.mak
>>  create mode 100644 hw/openrisc/Makefile.objs
>>  create mode 100644 target-openrisc/Makefile.objs
>>  create mode 100644 target-openrisc/cpu.c
>>  create mode 100644 target-openrisc/cpu.h
>>  create mode 100644 target-openrisc/intrpt.c
>>  create mode 100644 target-openrisc/machine.c
>>  create mode 100644 target-openrisc/mmu.c
>>  create mode 100644 target-openrisc/mmu_helper.c
>>  create mode 100644 target-openrisc/translate.c
>
>> diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs
>> new file mode 100644
>> index 000..21b76b2
>> --- /dev/null
>> +++ b/target-openrisc/Makefile.objs
>> @@ -0,0 +1,3 @@
>> +obj-$(CONFIG_SOFTMMU) += machine.o
>> +obj-y += cpu.o intrpt.o mmu.o translate.o
>
> intrpt.o? Any chance of a better to read/remember file name?

Is interrupt.o OK?

>
>> +obj-y += mmu_helper.o
>> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
>> new file mode 100644
>> index 000..64ddc98
>> --- /dev/null
>> +++ b/target-openrisc/cpu.c
>> @@ -0,0 +1,236 @@
>> +/*
>> + *  QEMU OpenRISC CPU
>> + *
>> + *  Copyright (c) 2012 Jia Liu 
>
> Two-space indentation? (also in other files)

I'll change all of them into one-space indentation.

>
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see 
>> .
>> + */
>> +
>> +#include "cpu.h"
>> +#include "qemu-common.h"
>
>> +#ifndef CONFIG_USER_ONLY
>> +#include "hw/loader.h"
>> +#endif
>
> Not yet needed in this patch?

Thanks, I've deleted them.

>
>> +
>> +/* CPUClass::reset() */
>> +static void openrisc_cpu_reset(CPUState *s)
>> +{
>> +OpenRISCCPU *cpu = OPENRISC_CPU(s);
>> +OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
>> +
>> +if (qemu_loglevel_mask(CPU_LOG_RESET)) {
>> +qemu_log("CPU Reset (CPU %d)\n", cpu->env.cpu_index);
>> +log_cpu_state(&cpu->env, 0);
>> +}
>> +
>> +occ->parent_reset(s);
>> +
>> +memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
>
> Note, if you wanted, you could've declared a CPUOpenRISCState *env to
> avoid re-typing "cpu->env." or "&cpu->env".

Thank you for notice me.

>
>> +
>> +tlb_flush(&cpu->env, 1);
>> +/*tb_flush(&cpu->env);FIXME: Do we need it?  */
>> +
>> +cpu->env.pc = 0x100;
>> +cpu->env.sr = SR_FO | SR_SM;
>> +cpu->env.exception_index = -1;
>> +
>> +cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
>> +cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
>> +cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 
>> 2));
>> +cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 
>> 2));
>> +
>> +#ifndef CONFIG_USER_ONLY
>> +cpu->env.picmr = 0x;
>> +cpu->env.picsr = 0x;
>> +
>> +cpu->env.ttmr = 0x;
>> +cpu->env.ttcr = 0x;
>> +#endif
>> +}
>> +
>> +static inline int openrisc_feature(OpenRISCCPU *cpu, int feature)
>
> This could return bool.

Thank you for point this!

>
>> +{
>> +return (cpu->env.feature & (1u << feature)) != 0;
>> +}
>> +
>> +static inline void set_f

Re: [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu

[Andreas Färber]

Am 05.07.2012 15:31, schrieb Paolo Bonzini:
> Il 05/07/2012 15:22, Andreas Färber ha scritto:
 +static void openrisc_any_initfn(Object *obj)
 +{
 +OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 +
 +set_feature(cpu, OPENRISC_FEATURE_OB32S);
 +set_feature(cpu, OPENRISC_FEATURE_OF32S);
 +
 +cpu_reset(CPU(cpu));
 +}
>> Paolo, could class_base_init or something help with this pattern of
>> needing to do something in every derived initfn?
> 
> I guess what you're looking for is some instance_post_init that is
> called at init time after instance_init?

Sort of. The pattern I was seeing is parent initializes something, child
modifies it, some action is performed on it.

Here we can get away by deferring the common action to realize stage,
just like we did for arm. My reasoning was that it's better to reset in
realizefn for reproducible behavior over system_reset. Not sure if we
can always escape to such a late stage, but we can worry about that when
we have a concrete use case. :)

Andreas

>> On the other hand I think we should move cpu_reset() into the realizefn
>> instead, that would avoid this issue here.
> 
> Yep.
> 
> Paolo

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu

[Paolo Bonzini]

Il 05/07/2012 15:22, Andreas Färber ha scritto:
>> > +static void openrisc_any_initfn(Object *obj)
>> > +{
>> > +OpenRISCCPU *cpu = OPENRISC_CPU(obj);
>> > +
>> > +set_feature(cpu, OPENRISC_FEATURE_OB32S);
>> > +set_feature(cpu, OPENRISC_FEATURE_OF32S);
>> > +
>> > +cpu_reset(CPU(cpu));
>> > +}
> Paolo, could class_base_init or something help with this pattern of
> needing to do something in every derived initfn?

I guess what you're looking for is some instance_post_init that is
called at init time after instance_init?

> On the other hand I think we should move cpu_reset() into the realizefn
> instead, that would avoid this issue here.

Yep.

Paolo

Re: [Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu

[Andreas Färber]

Am 01.07.2012 04:45, schrieb Jia Liu:
> Add OpenRISC target stubs and cpu support.
> 
> Signed-off-by: Jia Liu 
> ---
>  arch_init.c  |2 +
>  arch_init.h  |1 +
>  configure|   14 +-
>  cpu-exec.c   |2 +
>  default-configs/or32-softmmu.mak |4 +
>  elf.h|2 +
>  hw/openrisc/Makefile.objs|1 +
>  poison.h |1 +
>  target-openrisc/Makefile.objs|3 +
>  target-openrisc/cpu.c|  236 +++
>  target-openrisc/cpu.h|  286 
> ++
>  target-openrisc/intrpt.c |   30 
>  target-openrisc/machine.c|   30 
>  target-openrisc/mmu.c|   39 ++
>  target-openrisc/mmu_helper.c |   43 ++
>  target-openrisc/translate.c  |   75 ++
>  16 files changed, 767 insertions(+), 2 deletions(-)
>  create mode 100644 default-configs/or32-softmmu.mak
>  create mode 100644 hw/openrisc/Makefile.objs
>  create mode 100644 target-openrisc/Makefile.objs
>  create mode 100644 target-openrisc/cpu.c
>  create mode 100644 target-openrisc/cpu.h
>  create mode 100644 target-openrisc/intrpt.c
>  create mode 100644 target-openrisc/machine.c
>  create mode 100644 target-openrisc/mmu.c
>  create mode 100644 target-openrisc/mmu_helper.c
>  create mode 100644 target-openrisc/translate.c

> diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs
> new file mode 100644
> index 000..21b76b2
> --- /dev/null
> +++ b/target-openrisc/Makefile.objs
> @@ -0,0 +1,3 @@
> +obj-$(CONFIG_SOFTMMU) += machine.o
> +obj-y += cpu.o intrpt.o mmu.o translate.o

intrpt.o? Any chance of a better to read/remember file name?

> +obj-y += mmu_helper.o
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> new file mode 100644
> index 000..64ddc98
> --- /dev/null
> +++ b/target-openrisc/cpu.c
> @@ -0,0 +1,236 @@
> +/*
> + *  QEMU OpenRISC CPU
> + *
> + *  Copyright (c) 2012 Jia Liu 

Two-space indentation? (also in other files)

> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see 
> .
> + */
> +
> +#include "cpu.h"
> +#include "qemu-common.h"

> +#ifndef CONFIG_USER_ONLY
> +#include "hw/loader.h"
> +#endif

Not yet needed in this patch?

> +
> +/* CPUClass::reset() */
> +static void openrisc_cpu_reset(CPUState *s)
> +{
> +OpenRISCCPU *cpu = OPENRISC_CPU(s);
> +OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
> +
> +if (qemu_loglevel_mask(CPU_LOG_RESET)) {
> +qemu_log("CPU Reset (CPU %d)\n", cpu->env.cpu_index);
> +log_cpu_state(&cpu->env, 0);
> +}
> +
> +occ->parent_reset(s);
> +
> +memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));

Note, if you wanted, you could've declared a CPUOpenRISCState *env to
avoid re-typing "cpu->env." or "&cpu->env".

> +
> +tlb_flush(&cpu->env, 1);
> +/*tb_flush(&cpu->env);FIXME: Do we need it?  */
> +
> +cpu->env.pc = 0x100;
> +cpu->env.sr = SR_FO | SR_SM;
> +cpu->env.exception_index = -1;
> +
> +cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
> +cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
> +cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 
> 2));
> +cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 
> 2));
> +
> +#ifndef CONFIG_USER_ONLY
> +cpu->env.picmr = 0x;
> +cpu->env.picsr = 0x;
> +
> +cpu->env.ttmr = 0x;
> +cpu->env.ttcr = 0x;
> +#endif
> +}
> +
> +static inline int openrisc_feature(OpenRISCCPU *cpu, int feature)

This could return bool.

> +{
> +return (cpu->env.feature & (1u << feature)) != 0;
> +}
> +
> +static inline void set_feature(OpenRISCCPU *cpu, int feature)
> +{
> +cpu->env.feature |= 1u << feature;
> +}
> +
> +void openrisc_cpu_realize(Object *obj, Error **errp)
> +{
> +OpenRISCCPU *cpu = OPENRISC_CPU(obj);
> +if (openrisc_feature(cpu, OPENRISC_FEATURE_OR1200)) {
> +set_feature(cpu, OPENRISC_FEATURE_OB32S);
> +set_feature(cpu, OPENRISC_FEATURE_OF32S);
> +}
> +
> +qemu_init_vcpu(&cpu->env);
> +}
> +
> +static void openrisc_cpu_initfn(Object *obj)
> +{
> +OpenRISCCPU *cpu = OPENRISC_CPU(obj);
> +c

[Qemu-devel] [PATCH v8 01/16] target-or32: Add target stubs and QOM cpu

[Jia Liu]

Add OpenRISC target stubs and cpu support.

Signed-off-by: Jia Liu 
---
 arch_init.c  |2 +
 arch_init.h  |1 +
 configure|   14 +-
 cpu-exec.c   |2 +
 default-configs/or32-softmmu.mak |4 +
 elf.h|2 +
 hw/openrisc/Makefile.objs|1 +
 poison.h |1 +
 target-openrisc/Makefile.objs|3 +
 target-openrisc/cpu.c|  236 +++
 target-openrisc/cpu.h|  286 ++
 target-openrisc/intrpt.c |   30 
 target-openrisc/machine.c|   30 
 target-openrisc/mmu.c|   39 ++
 target-openrisc/mmu_helper.c |   43 ++
 target-openrisc/translate.c  |   75 ++
 16 files changed, 767 insertions(+), 2 deletions(-)
 create mode 100644 default-configs/or32-softmmu.mak
 create mode 100644 hw/openrisc/Makefile.objs
 create mode 100644 target-openrisc/Makefile.objs
 create mode 100644 target-openrisc/cpu.c
 create mode 100644 target-openrisc/cpu.h
 create mode 100644 target-openrisc/intrpt.c
 create mode 100644 target-openrisc/machine.c
 create mode 100644 target-openrisc/mmu.c
 create mode 100644 target-openrisc/mmu_helper.c
 create mode 100644 target-openrisc/translate.c

diff --git a/arch_init.c b/arch_init.c
index a9e8b74..4b521e5 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -71,6 +71,8 @@ int graphic_depth = 15;
 #define QEMU_ARCH QEMU_ARCH_MICROBLAZE
 #elif defined(TARGET_MIPS)
 #define QEMU_ARCH QEMU_ARCH_MIPS
+#elif defined(TARGET_OPENRISC)
+#define QEMU_ARCH QEMU_ARCH_OPENRISC
 #elif defined(TARGET_PPC)
 #define QEMU_ARCH QEMU_ARCH_PPC
 #elif defined(TARGET_S390X)
diff --git a/arch_init.h b/arch_init.h
index c7cb94a..3dfea3b 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -16,6 +16,7 @@ enum {
 QEMU_ARCH_SH4 = 1024,
 QEMU_ARCH_SPARC = 2048,
 QEMU_ARCH_XTENSA = 4096,
+QEMU_ARCH_OPENRISC = 8192,
 };
 
 extern const uint32_t arch_type;
diff --git a/configure b/configure
index 9f071b7..7780876 100755
--- a/configure
+++ b/configure
@@ -924,6 +924,7 @@ mips-softmmu \
 mipsel-softmmu \
 mips64-softmmu \
 mips64el-softmmu \
+or32-softmmu \
 ppc-softmmu \
 ppcemb-softmmu \
 ppc64-softmmu \
@@ -3503,7 +3504,7 @@ target_arch2=`echo $target | cut -d '-' -f 1`
 target_bigendian="no"
 
 case "$target_arch2" in
-  
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
@@ -3619,6 +3620,11 @@ case "$target_arch2" in
 target_phys_bits=64
 target_long_alignment=8
   ;;
+  or32)
+TARGET_ARCH=openrisc
+TARGET_BASE_ARCH=openrisc
+target_phys_bits=32
+  ;;
   ppc)
 gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml 
power-spe.xml"
 target_phys_bits=64
@@ -3697,7 +3703,7 @@ symlink "$source_path/Makefile.target" 
"$target_dir/Makefile"
 
 
 case "$target_arch2" in
-  alpha | sparc* | xtensa* | ppc*)
+  alpha | or32 | sparc* | xtensa* | ppc*)
 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
   ;;
 esac
@@ -3871,6 +3877,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
 echo "CONFIG_MIPS_DIS=y"  >> $config_target_mak
 echo "CONFIG_MIPS_DIS=y"  >> $libdis_config_mak
   ;;
+  or32)
+echo "CONFIG_OPENRISC_DIS=y"  >> $config_target_mak
+echo "CONFIG_OPENRISC_DIS=y"  >> $libdis_config_mak
+  ;;
   ppc*)
 echo "CONFIG_PPC_DIS=y"  >> $config_target_mak
 echo "CONFIG_PPC_DIS=y"  >> $libdis_config_mak
diff --git a/cpu-exec.c b/cpu-exec.c
index 08c35f7..ce2d569 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -225,6 +225,7 @@ int cpu_exec(CPUArchState *env)
 #elif defined(TARGET_LM32)
 #elif defined(TARGET_MICROBLAZE)
 #elif defined(TARGET_MIPS)
+#elif defined(TARGET_OPENRISC)
 #elif defined(TARGET_SH4)
 #elif defined(TARGET_CRIS)
 #elif defined(TARGET_S390X)
@@ -634,6 +635,7 @@ int cpu_exec(CPUArchState *env)
   | env->cc_dest | (env->cc_x << 4);
 #elif defined(TARGET_MICROBLAZE)
 #elif defined(TARGET_MIPS)
+#elif defined(TARGET_OPENRISC)
 #elif defined(TARGET_SH4)
 #elif defined(TARGET_ALPHA)
 #elif defined(TARGET_CRIS)
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
new file mode 100644
index 000..cce4746
--- /dev/null
+++ b/default-configs/or32-softmmu.mak
@@ -0,0 +1,4 @@
+# Default configuration for or32-softmmu
+
+CONFIG_SERIAL=y
+CONFIG_OPENCORES_ETH=y
diff --git a/elf.h b/elf.h
index 9c9acfa..a21ea53 100644
--- a/elf.h
+++ b/elf.h
@@ -106,6 +106,8 @@ typedef int64_t  Elf64_Sxword;
 #define EM_H8S  48  /* Hitachi H8S */
 #define EM_LATTICEMICO32 138/* LatticeMico32 */
 
+#define EM_OPENRISC 92/* OpenCores OpenRISC */
+
 #define EM_UNICORE32110 /* UniCore32