Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.
Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.
This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.
Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.
Signed-off-by: Tony Nguyen
---
accel/tcg/cputlb.c | 8 ++--
exec.c | 13 +++--
hw/intc/armv7m_nvic.c| 15 ---
hw/s390x/s390-pci-inst.c | 6 --
hw/vfio/pci-quirks.c | 5 +++--
hw/virtio/virtio-pci.c | 6 --
include/exec/memory.h| 3 +++
memory.c | 18 ++
memory_ldst.inc.c| 24 ++--
9 files changed, 75 insertions(+), 23 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878f73..f64c6b1c75 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
-r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+r = memory_region_dispatch_read(mr, mr_offset, &val,
+size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
-r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+r = memory_region_dispatch_write(mr, mr_offset, val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -1305,6 +1307,7 @@ load_helper(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi,
}
}
+/* TODO: Merge bswap into io_readx -> memory_region_dispatch_read. */
res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
mmu_idx, addr, retaddr, access_type, size);
return handle_bswap(res, size, big_endian);
@@ -1553,6 +1556,7 @@ store_helper(CPUArchState *env, target_ulong addr,
uint64_t val,
}
}
+/* TODO: Merge bswap into io_writex -> memory_region_dispatch_write.
*/
io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
handle_bswap(val, size, big_endian),
addr, retaddr, size);
diff --git a/exec.c b/exec.c
index 73d629b9c8..39aff6810b 100644
--- a/exec.c
+++ b/exec.c
@@ -3364,8 +3364,13 @@ static MemTxResult flatview_write_continue(FlatView *fv,
hwaddr addr,
/* XXX: could force current_cpu to NULL to avoid
potential bugs */
val = ldn_p(buf, l);
+/*
+ * TODO: Merge bswap from ldn_p into memory_region_dispatch_write
+ * by using ldn_he_p and dropping MO_TE to get a host-endian value.
+ */
result |= memory_region_dispatch_write(mr, addr1, val,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE,
+ attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3426,8 +3431,12 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr
addr,
/* I/O case */
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
+/*
+ * TODO: Merge bswap from stn_p into memory_region_dispatch_read
+ * by using stn_he_p and dropping MO_TE to get a host-endian value.
+ */
result |= memory_region_dispatch_read(mr, addr1, &val,
- size_memop(l), attrs);
+ size_memop(l) | MO_TE,
attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 7220940133..8e93e51e81 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2349,8 +2349,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,
hwaddr addr,
if (attrs.secure) {
/* S accesses to the alias act like NS accesses to the real region */
attrs.secure = 0;
-return memory_region_dispatch_write(mr, addr, value, size_memop(size),
-attrs);
+return memory_region_dispatch_write(mr, addr, value,
+size_memop(size) | MO_TE, attrs);
