Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
Hi Sebastian, On Mon, Oct 28, 2013 at 9:56 AM, Sebastian Macke sebast...@macke.de wrote: On 25/10/2013 5:21 PM, Jia Liu wrote: On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote: On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Then, I'll make one pull request when you finish all you jobs, please let me know when you finish your last work, is it OK? Ok, do you want me to send then all patches including the old ones together in one patchset? At the moment this are 19 patches. Your call. Keep in mind that the new patches will change much more. And maybe there will be discussions of some decisions I made. But I promise also a speed increase of a factor of 7-10 :) When you summit a patch, I'll be always there :) Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
On 25/10/2013 5:21 PM, Jia Liu wrote: On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote: On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Then, I'll make one pull request when you finish all you jobs, please let me know when you finish your last work, is it OK? Ok, do you want me to send then all patches including the old ones together in one patchset? At the moment this are 19 patches. Keep in mind that the new patches will change much more. And maybe there will be discussions of some decisions I made. But I promise also a speed increase of a factor of 7-10 :) Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke sebast...@macke.de wrote: On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Then, I'll make one pull request when you finish all you jobs, please let me know when you finish your last work, is it OK? Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
On 22/10/2013 8:47 PM, Jia Liu wrote: Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Ok great, the next bunch of patches is already in development. Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
Hi Sebastian, On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke sebast...@macke.de wrote: This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. For v2 0/9 - 9/9 Acked-by: Jia Liu pro...@gmail.com I'll add some comment into the code to explain why we separate flags from sr and send a pull request if nobody raise a rejection. Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1 Regards, Jia
[Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements
This series is the first part to make the OpenRISC target more reliable and faster. It corrects several severe problems which prevented the OpenRISC emulation for being useful in the past. The patchset was tested with - the tests/tcg/openrisc tests - booting Linux 3.11 - run configure + make + gcc of a simple terminal graphic demo called cmatrix - run benchmark tool nbench in qemu-user mode and in the softmmu mode The speed improvement is less than 10% because the overhead is still to high as the openrisc target does not support translation block chaining. This will be included in one of the future patches. Only the patch which removes the npc and ppc variables removes a little feature from the OpenRISC target but which does not break the specification and will lead to a significant speed improvement. Sebastian Macke (9): target-openrisc: Speed up move instruction target-openrisc: Remove unnecessary code generated by jump instructions target-openrisc: Remove executable flag for every page target-openrisc: Correct wrong epcr register in interrupt handler openrisc-timer: Reduce overhead, Separate clock update functions target-openrisc: Correct memory bounds checking for the tlb buffers target-openrisc: Separate branch flag from Supervision register target-openrisc: Complete remove of npc and ppc variables target-openrisc: Correct carry flag check of l.addc and l.addic test cases hw/openrisc/cputimer.c | 29 -- target-openrisc/cpu.c | 1 + target-openrisc/cpu.h | 16 ++- target-openrisc/gdbstub.c | 20 +--- target-openrisc/interrupt.c| 27 ++--- target-openrisc/interrupt_helper.c | 3 +- target-openrisc/machine.c | 3 +- target-openrisc/mmu.c | 4 +- target-openrisc/sys_helper.c | 74 ++ target-openrisc/translate.c| 201 - tests/tcg/openrisc/test_addc.c | 8 +- tests/tcg/openrisc/test_addic.c| 10 +- 12 files changed, 175 insertions(+), 221 deletions(-) -- 1.8.4.1
