Re: [Qemu-devel] [PULL 00/13] target-arm queue

2018-03-20 Thread Peter Maydell 
On 19 March 2018 at 18:34, Peter Maydell  wrote:
> Arm patch queue -- these are all bug fix patches but we might
> as well put them in to rc0...
>
> thanks
> -- PMM
>
> The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
> (2018-03-19 11:44:26 +)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20180319
>
> for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:
>
>   hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 
> +)
>
> 
> target-arm queue:
>  * fsl-imx6: Fix incorrect Ethernet interrupt defines
>  * dump: Update correct kdump phys_base field for AArch64
>  * char: i.MX: Add support for "TX complete" interrupt
>  * bcm2836/raspi: Fix various bugs resulting in panics trying
>to boot a Debian Linux kernel on raspi3
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/13] target-arm queue

2018-03-19 Thread Peter Maydell 
Arm patch queue -- these are all bug fix patches but we might
as well put them in to rc0...

thanks
-- PMM

The following changes since commit 2c8cfc0b52b5a4d123c26c0b5fdf941be24805be:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
(2018-03-19 11:44:26 +)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180319

for you to fetch changes up to ff72cb6b46b95bb530787add5277c211af3d31c6:

  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs (2018-03-19 18:23:24 
+)


target-arm queue:
 * fsl-imx6: Fix incorrect Ethernet interrupt defines
 * dump: Update correct kdump phys_base field for AArch64
 * char: i.MX: Add support for "TX complete" interrupt
 * bcm2836/raspi: Fix various bugs resulting in panics trying
   to boot a Debian Linux kernel on raspi3


Andrey Smirnov (2):
  char: i.MX: Simplify imx_update()
  char: i.MX: Add support for "TX complete" interrupt

Guenter Roeck (1):
  fsl-imx6: Swap Ethernet interrupt defines

Peter Maydell (9):
  hw/arm/raspi: Don't do board-setup or secure-boot for raspi3
  hw/arm/boot: assert that secure_boot and secure_board_setup are false for 
AArch64
  hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE
  hw/arm/bcm2386: Fix parent type of bcm2386
  hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x
  hw/arm/bcm2836: Create proper bcm2837 device
  hw/arm/bcm2836: Use correct affinity values for BCM2837
  hw/arm/bcm2836: Hardcode correct CPU type
  hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

Wei Huang (1):
  dump: Update correct kdump phys_base field for AArch64

 include/hw/arm/bcm2836.h | 31 +---
 include/hw/arm/fsl-imx6.h|  4 +-
 include/hw/char/imx_serial.h |  3 ++
 dump.c   | 14 +--
 hw/arm/bcm2836.c | 87 +++-
 hw/arm/boot.c| 12 ++
 hw/arm/raspi.c   | 77 +++
 hw/char/imx_serial.c | 44 --
 hw/net/imx_fec.c | 28 +-
 9 files changed, 237 insertions(+), 63 deletions(-)

Re: [Qemu-devel] [PULL 00/13] target-arm queue

2017-10-16 Thread Peter Maydell 
On 12 October 2017 at 17:03, Peter Maydell  wrote:
> target-arm queue:
>  * mostly my latest v8M stuff, plus a couple of minor patches
>
> The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:
>
>   Merge remote-tracking branch 
> 'remotes/ehabkost/tags/python-next-pull-request' into staging (2017-10-12 
> 10:02:09 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20171012
>
> for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:
>
>   nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 
> +0100)
>
> 
> target-arm queue:
>  * v8M: SG, BLXNS, secure-return
>  * v8M: fixes for coverity issues in previous patches
>  * arm: fix armv7m_init() declaration to match definition
>  * watchdog/aspeed: fix variable type to store reload value
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/13] target-arm queue

2017-10-12 Thread Peter Maydell 
target-arm queue:
 * mostly my latest v8M stuff, plus a couple of minor patches

The following changes since commit a0b261db8c030813e30a39eae47359ac2a37f7e2:

  Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' 
into staging (2017-10-12 10:02:09 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20171012

for you to fetch changes up to cf5f7937b05c84d5565134f058c00cd48304a117:

  nvic: Fix miscalculation of offsets into ITNS array (2017-10-12 16:33:16 
+0100)


target-arm queue:
 * v8M: SG, BLXNS, secure-return
 * v8M: fixes for coverity issues in previous patches
 * arm: fix armv7m_init() declaration to match definition
 * watchdog/aspeed: fix variable type to store reload value


Cédric Le Goater (1):
  watchdog/aspeed: fix variable type to store reload value

Igor Mammedov (1):
  arm: fix armv7m_init() declaration to match definition

Peter Maydell (11):
  target/arm: Add M profile secure MMU index values to 
get_a32_user_mem_index()
  target/arm: Implement SG instruction
  target/arm: Implement BLXNS
  target/arm: Implement secure function return
  target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
  target/arm: Pull Thumb insn word loads up to top level
  target-arm: Simplify insn_crosses_page()
  target/arm: Support some Thumb insns being always unconditional
  target/arm: Implement SG instruction corner cases
  nvic: Add missing 'break'
  nvic: Fix miscalculation of offsets into ITNS array

 include/hw/arm/arm.h |   2 +-
 target/arm/helper.h  |   1 +
 target/arm/internals.h   |   8 ++
 hw/intc/armv7m_nvic.c|   5 +-
 hw/watchdog/wdt_aspeed.c |   4 +-
 target/arm/helper.c  | 306 --
 target/arm/translate.c   | 310 ---
 7 files changed, 521 insertions(+), 115 deletions(-)

Re: [Qemu-devel] [PULL 00/13] target-arm queue

2017-02-07 Thread no-reply 
Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PULL 00/13] target-arm queue
Message-id: 1486492645-27803-1-git-send-email-peter.mayd...@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/1486454676-29112-1-git-send-email-bhar...@linux.vnet.ibm.com -> 
patchew/1486454676-29112-1-git-send-email-bhar...@linux.vnet.ibm.com
 * [new tag] 
patchew/1486492645-27803-1-git-send-email-peter.mayd...@linaro.org -> 
patchew/1486492645-27803-1-git-send-email-peter.mayd...@linaro.org
 - [tag update]  patchew/20170203160651.19917-1-dgilb...@redhat.com -> 
patchew/20170203160651.19917-1-dgilb...@redhat.com
 - [tag update]  patchew/20170206112953.16993-1-berra...@redhat.com -> 
patchew/20170206112953.16993-1-berra...@redhat.com
 - [tag update]  patchew/20170207135211.15870-1-marcandre.lur...@redhat.com 
-> patchew/20170207135211.15870-1-marcandre.lur...@redhat.com
Switched to a new branch 'test'
42d6adc stellaris: Use the 'unimplemented' device for parts we don't implement
437dc39 hw/misc: New "unimplemented" sysbus device
cf763a0 stellaris: Document memory map and which SoC devices are unimplemented
f9d8179 target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
9a7aa9e target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
9d362c5 arm: Correctly handle watchpoints for BE32 CPUs
a454865 Fix Thumb-1 BE32 execution and disassembly.
753a1d2 target/arm: Add cfgend parameter for ARM CPU selection.
7ddb3c4 hw/arm/integratorcp: Support specifying features via -cpu
49b034d sd: sdhci: check data length during dma_memory_read
0ae81e4 aspeed: add a watchdog controller
d7e9de5 wdt: Add Aspeed watchdog device model
e677809 integratorcp: adding vmstate for save/restore

=== OUTPUT BEGIN ===
Checking PATCH 1/13: integratorcp: adding vmstate for save/restore...
Checking PATCH 2/13: wdt: Add Aspeed watchdog device model...
Checking PATCH 3/13: aspeed: add a watchdog controller...
Checking PATCH 4/13: sd: sdhci: check data length during dma_memory_read...
Checking PATCH 5/13: hw/arm/integratorcp: Support specifying features via 
-cpu...
Checking PATCH 6/13: target/arm: Add cfgend parameter for ARM CPU selection
Checking PATCH 7/13: Fix Thumb-1 BE32 execution and disassembly
ERROR: code indent should never use tabs
#44: FILE: include/disas/bfd.h:298:
+#define INSN_ARM_BE32^I0x0001$

total: 1 errors, 0 warnings, 77 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 8/13: arm: Correctly handle watchpoints for BE32 CPUs...
ERROR: space prohibited between function name and open parenthesis '('
#49: FILE: include/qom/cpu.h:200:
+vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);

total: 1 errors, 0 warnings, 88 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 9/13: target/arm: Abstract out pbit/wbit tests in ARM ldr/str 
decode...
Checking PATCH 10/13: target/arm: A32, T32: Create Instruction Syndromes for 
Data Aborts...
Checking PATCH 11/13: stellaris: Document memory map and which SoC devices are 
unimplemented...
Checking PATCH 12/13: hw/misc: New "unimplemented" sysbus device...
Checking PATCH 13/13: stellaris: Use the 'unimplemented' device for parts we 
don't implement...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@freelists.org

Re: [Qemu-devel] [PULL 00/13] target-arm queue

2017-02-07 Thread Peter Maydell 
On 7 February 2017 at 18:37, Peter Maydell  wrote:
> A random mix of items here, nothing very major.
>
> thanks
> -- PMM
>
>
> The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
>
>   Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' 
> into staging (2017-02-07 15:29:26 +)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20170207
>
> for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:
>
>   stellaris: Use the 'unimplemented' device for parts we don't implement 
> (2017-02-07 18:30:00 +)
>
> 
> target-arm:
>  * new "unimplemented" device for stubbing out devices in a
>system model so accesses can be logged
>  * stellaris: document the SoC memory map
>  * arm: create instruction syndromes for AArch32 data aborts
>  * arm: Correctly handle watchpoints for BE32 CPUs
>  * Fix Thumb-1 BE32 execution and disassembly
>  * arm: Add cfgend parameter for ARM CPU selection
>  * sd: sdhci: check data length during dma_memory_read
>  * aspeed: add a watchdog controller
>  * integratorcp: adding vmstate for save/restore

Clang complains about unused functions; will squash in:

diff --git a/target/arm/translate.c b/target/arm/translate.c
index a14f74c..4436d8f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -982,7 +982,7 @@ static inline void
gen_aa32_ld##SUFF##_iss(DisasContext *s,  \
TCGv_i32 a32, int index,  \
ISSInfo issinfo)  \
 {\
-gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);   \
+gen_aa32_ld##SUFF(s, val, a32, index);   \
 disas_set_da_iss(s, OPC, issinfo);   \
 }

@@ -997,7 +997,7 @@ static inline void
gen_aa32_st##SUFF##_iss(DisasContext *s,  \
TCGv_i32 a32, int index,  \
ISSInfo issinfo)  \
 {\
-gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);   \
+gen_aa32_st##SUFF(s, val, a32, index);   \
 disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);  \
 }


(which avoids the problem by having the _iss() versions of the
function call the non-iss versions rather than duplicating
their function body; seems like better code anyway.)

thanks
-- PMM

[Qemu-devel] [PULL 00/13] target-arm queue

2017-02-07 Thread Peter Maydell 
A random mix of items here, nothing very major.

thanks
-- PMM


The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:

  Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' 
into staging (2017-02-07 15:29:26 +)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20170207

for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:

  stellaris: Use the 'unimplemented' device for parts we don't implement 
(2017-02-07 18:30:00 +)


target-arm:
 * new "unimplemented" device for stubbing out devices in a
   system model so accesses can be logged
 * stellaris: document the SoC memory map
 * arm: create instruction syndromes for AArch32 data aborts
 * arm: Correctly handle watchpoints for BE32 CPUs
 * Fix Thumb-1 BE32 execution and disassembly
 * arm: Add cfgend parameter for ARM CPU selection
 * sd: sdhci: check data length during dma_memory_read
 * aspeed: add a watchdog controller
 * integratorcp: adding vmstate for save/restore


Cédric Le Goater (2):
  wdt: Add Aspeed watchdog device model
  aspeed: add a watchdog controller

Julian Brown (4):
  hw/arm/integratorcp: Support specifying features via -cpu
  target/arm: Add cfgend parameter for ARM CPU selection.
  Fix Thumb-1 BE32 execution and disassembly.
  arm: Correctly handle watchpoints for BE32 CPUs

Pavel Dovgalyuk (1):
  integratorcp: adding vmstate for save/restore

Peter Maydell (5):
  target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
  target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
  stellaris: Document memory map and which SoC devices are unimplemented
  hw/misc: New "unimplemented" sysbus device
  stellaris: Use the 'unimplemented' device for parts we don't implement

Prasad J Pandit (1):
  sd: sdhci: check data length during dma_memory_read

 hw/misc/Makefile.objs|   2 +
 hw/watchdog/Makefile.objs|   1 +
 include/disas/bfd.h  |   7 ++
 include/hw/arm/aspeed_soc.h  |   2 +
 include/hw/misc/unimp.h  |  39 +++
 include/hw/watchdog/wdt_aspeed.h |  32 ++
 include/qom/cpu.h|   3 +
 target/arm/arm_ldst.h|  10 +-
 target/arm/cpu.h |   7 ++
 target/arm/internals.h   |   5 +
 target/arm/translate.h   |  14 +++
 disas.c  |   1 +
 exec.c   |   1 +
 hw/arm/aspeed_soc.c  |  13 +++
 hw/arm/integratorcp.c|  78 +-
 hw/arm/stellaris.c   |  48 +
 hw/misc/unimp.c  | 107 +++
 hw/sd/sdhci.c|   2 +-
 hw/watchdog/wdt_aspeed.c | 225 +++
 qom/cpu.c|   6 ++
 target/arm/cpu.c |  39 +++
 target/arm/op_helper.c   |  22 
 target/arm/translate-a64.c   |  14 ---
 target/arm/translate.c   | 193 -
 24 files changed, 801 insertions(+), 70 deletions(-)
 create mode 100644 include/hw/misc/unimp.h
 create mode 100644 include/hw/watchdog/wdt_aspeed.h
 create mode 100644 hw/misc/unimp.c
 create mode 100644 hw/watchdog/wdt_aspeed.c

Re: [Qemu-devel] [PULL 00/13] target-arm queue

2015-11-03 Thread Peter Maydell 
On 3 November 2015 at 14:13, Peter Maydell  wrote:
> Here's the target-arm queue for 2.5: a few minor cleanups, one or
> two small new features, and a pile of bug fixes.
>
> Still on my to-review list for 2.5:
>  * the breakpoint/singlestep fixes
>  * highbank boot blob patchset
>  * zynq ADC controller (maybe)
>
> so I expect to do another pullreq before rc0.
>
> thanks
> -- PMM
>
> The following changes since commit 130d0bc6594d0cc6591d00312841891b3c187b07:
>
>   Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20151103-1' into 
> staging (2015-11-03 10:20:04 +)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20151103
>
> for you to fetch changes up to 5d9c1756140d680e66e5b45005a1fb7078b74ee1:
>
>   ARM: ACPI: Fix MPIDR value in ACPI table (2015-11-03 13:49:42 +)
>
> 
> target-arm queue:
>  * code cleanup to use symbolic constants for register bank numbers
>  * fix direct booting of modern Linux kernels on xilinx_zynq by setting
>SCLR values to what the kernel expects firmware to have done
>  * implement SYSRESETREQ for ARMv7M CPU (stellaris boards)
>  * update MAINTAINERS to mention new qemu-arm mailing list
>  * clean up display of PSTATE in AArch64 debug logs
>  * report Secure/Nonsecure status in CPU debug logs
>  * fix a missing _CCA attribute in ACPI tables
>  * add support for GICv3 to ACPI tables
>
> 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/13] target-arm queue

2015-11-03 Thread Peter Maydell 
Here's the target-arm queue for 2.5: a few minor cleanups, one or
two small new features, and a pile of bug fixes.

Still on my to-review list for 2.5:
 * the breakpoint/singlestep fixes
 * highbank boot blob patchset
 * zynq ADC controller (maybe)

so I expect to do another pullreq before rc0.

thanks
-- PMM

The following changes since commit 130d0bc6594d0cc6591d00312841891b3c187b07:

  Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20151103-1' into 
staging (2015-11-03 10:20:04 +)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20151103

for you to fetch changes up to 5d9c1756140d680e66e5b45005a1fb7078b74ee1:

  ARM: ACPI: Fix MPIDR value in ACPI table (2015-11-03 13:49:42 +)


target-arm queue:
 * code cleanup to use symbolic constants for register bank numbers
 * fix direct booting of modern Linux kernels on xilinx_zynq by setting
   SCLR values to what the kernel expects firmware to have done
 * implement SYSRESETREQ for ARMv7M CPU (stellaris boards)
 * update MAINTAINERS to mention new qemu-arm mailing list
 * clean up display of PSTATE in AArch64 debug logs
 * report Secure/Nonsecure status in CPU debug logs
 * fix a missing _CCA attribute in ACPI tables
 * add support for GICv3 to ACPI tables


Graeme Gregory (1):
  hw/arm/virt-acpi-build: _CCA attribute is compulsory

Michael Davidsaver (3):
  armv7-m: Return DeviceState* from armv7m_init()
  armv7-m: Implement SYSRESETREQ
  arm: stellaris: exit on external reset request

Peter Crosthwaite (3):
  arm: boot: Adjust indentation of FIXUP comments
  arm: boot: Add board specific setup code API
  arm: xilinx_zynq: Add linux pre-boot

Peter Maydell (3):
  MAINTAINERS: Add new qemu-arm mailing list to ARM related entries
  target-arm: Bring AArch64 debug CPU display of PSTATE into line with 
AArch32
  target-arm: Report S/NS status in the CPU debug logs

Shannon Zhao (2):
  hw/arm/virt-acpi-build: Add GICC ACPI subtable for GICv3
  ARM: ACPI: Fix MPIDR value in ACPI table

Soren Brinkmann (1):
  target-arm: Add and use symbolic names for register banks

 MAINTAINERS| 23 +++
 hw/arm/armv7m.c|  9 ++---
 hw/arm/boot.c  | 36 +++-
 hw/arm/stellaris.c | 41 ++---
 hw/arm/stm32f205_soc.c | 15 ---
 hw/arm/virt-acpi-build.c   | 33 +++--
 hw/arm/xilinx_zynq.c   | 42 ++
 hw/intc/armv7m_nvic.c  |  9 -
 include/hw/arm/arm.h   | 12 +++-
 target-arm/helper.c| 37 ++---
 target-arm/internals.h | 16 +---
 target-arm/kvm32.c | 34 +-
 target-arm/op_helper.c |  8 
 target-arm/translate-a64.c | 17 ++---
 target-arm/translate.c | 12 +++-
 15 files changed, 251 insertions(+), 93 deletions(-)

Re: [Qemu-devel] [PULL 00/13] target-arm queue

2015-10-17 Thread Peter Maydell 
On 16 October 2015 at 14:57, Peter Maydell  wrote:
> Flushing the target-arm queue for softfreeze. I still have stuff
> in my to-review queue but it mostly looked too RFC-ish/otherwise
> not really 2.5 material, or just needs a bit more time on list for
> review.
>
> thanks
> -- PMM
>
>
>
> The following changes since commit c49d3411faae8ffaab8f7e5db47405a008411c10:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-10-12' 
> into staging (2015-10-13 10:42:06 +0100)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20151016
>
> for you to fetch changes up to 5d98bf8f38c17a348ab6e8af196088cd4953acd0:
>
>   target-arm: Fix CPU breakpoint handling (2015-10-16 14:48:56 +0100)
>
> 
> target-arm queue:
>  * break TBs after ISB instructions
>  * more support code for future implementation of EL2 and 64-bit EL3
>  * tell guest if KVM is enabled in SMBIOS version string
>  * implement OSLAR/OSLSR system registers
>  * provide better help text for Sharp PDA machine names
>  * rename imx25_pdk to imx25-pdk (since it has never been released
>with the underscore-version name)
>  * fix MMIO writes in zynq_slcr
>  * implement MDCR_EL2
>  * virt: allow the guest to configure PCI BARs with zero PCI addresses
>  * fix breakpoint handling code
>
> 

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 00/13] target-arm queue

2015-10-16 Thread Peter Maydell 
Flushing the target-arm queue for softfreeze. I still have stuff
in my to-review queue but it mostly looked too RFC-ish/otherwise
not really 2.5 material, or just needs a bit more time on list for
review.

thanks
-- PMM



The following changes since commit c49d3411faae8ffaab8f7e5db47405a008411c10:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-10-12' into 
staging (2015-10-13 10:42:06 +0100)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20151016

for you to fetch changes up to 5d98bf8f38c17a348ab6e8af196088cd4953acd0:

  target-arm: Fix CPU breakpoint handling (2015-10-16 14:48:56 +0100)


target-arm queue:
 * break TBs after ISB instructions
 * more support code for future implementation of EL2 and 64-bit EL3
 * tell guest if KVM is enabled in SMBIOS version string
 * implement OSLAR/OSLSR system registers
 * provide better help text for Sharp PDA machine names
 * rename imx25_pdk to imx25-pdk (since it has never been released
   with the underscore-version name)
 * fix MMIO writes in zynq_slcr
 * implement MDCR_EL2
 * virt: allow the guest to configure PCI BARs with zero PCI addresses
 * fix breakpoint handling code


Alexander Gordeev (1):
  hw/arm/virt: Allow zero address for PCI IO space

Andrew Jones (1):
  hw/arm/virt: smbios: inform guest of kvm

Davorin Mista (1):
  target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs

Peter Crosthwaite (2):
  arm: imx25-pdk: Fix machine name
  misc: zynq_slcr: Fix MMIO writes

Ryo ONODERA (1):
  target-arm: Provide model numbers for Sharp PDAs

Sergey Fedorov (4):
  target-arm: Add MDCR_EL2
  target-arm: implement arm_debug_target_el()
  target-arm: Fix GDB breakpoint handling
  target-arm: Fix CPU breakpoint handling

Sergey Sorokin (2):
  target-arm: Break the TB after ISB to execute self-modified code correctly
  target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL

Stefan Weil (1):
  target-arm: Add missing 'static' attribute

 hw/arm/collie.c|  2 +-
 hw/arm/imx25_pdk.c |  2 +-
 hw/arm/spitz.c |  8 +++
 hw/arm/tosa.c  |  2 +-
 hw/arm/virt.c  |  8 ++-
 hw/misc/zynq_slcr.c|  8 +++
 target-arm/cpu.h   | 30 +++
 target-arm/helper.c| 60 +-
 target-arm/helper.h|  2 ++
 target-arm/op_helper.c | 35 ++-
 target-arm/translate-a64.c | 25 ++-
 target-arm/translate.c | 36 ++--
 tests/ds1338-test.c|  2 +-
 13 files changed, 173 insertions(+), 47 deletions(-)

Re: [Qemu-devel] [PULL 00/13] target-arm queue (feat.ARM KVM support)

2013-03-05 Thread Aurelien Jarno 
On Tue, Mar 05, 2013 at 01:11:58AM +, Peter Maydell wrote:
 Hi; here's a target-arm pullre. Major business here is the KVM
 support patchset, though there are a couple of SRS bugfixes too.
 Please pull.
 
 thanks
 -- PMM
 
 The following changes since commit 26135ead80fa1fd13e95c162dacfd06f2ba82981:
 
   target-mips: Fix accumulator selection for MIPS16 and microMIPS (2013-03-05 
 01:02:09 +0100)
 
 are available in the git repository at:
 
   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
 
 for you to fetch changes up to ed4659d10fa2ec16ace367e4fffe6f7ced73112c:
 
   MAINTAINERS: add entry for ARM KVM guest cores (2013-03-05 00:45:43 +)
 
 
 Christoffer Dall (1):
   ARM: KVM: Add support for KVM on ARM architecture
 
 Peter Maydell (12):
   target-arm: Factor out handling of SRS instruction
   target-arm: Don't decode RFE or SRS on M profile cores
   oslib-posix: Align to permit transparent hugepages on ARM Linux
   linux-headers: resync from mainline to add ARM KVM headers
   target-arm: Drop CPUARMState* argument from bank_number()
   ARM KVM: save and load VFP registers from kernel
   hw/arm_gic: Add presave/postload hooks
   hw/arm_gic: Convert ARM GIC classes to use init/realize
   target-arm: Use MemoryListener to identify GIC base address for KVM
   hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC
   configure: Enable KVM on ARM
   MAINTAINERS: add entry for ARM KVM guest cores
 
  MAINTAINERS  |5 +
  configure|2 +-
  hw/a15mpcore.c   |8 +-
  hw/arm/Makefile.objs |1 +
  hw/arm_gic.c |   23 +-
  hw/arm_gic_common.c  |   36 ++-
  hw/arm_gic_internal.h|4 +-
  hw/arm_pic.c |   26 ++
  hw/armv7m_nvic.c |   15 +-
  hw/kvm/arm_gic.c |  167 
  linux-headers/asm-arm/kvm.h  |  180 +
  linux-headers/asm-arm/kvm_para.h |1 +
  linux-headers/asm-generic/kvm_para.h |4 +
  linux-headers/linux/kvm.h|   17 ++
  target-arm/Makefile.objs |1 +
  target-arm/cpu.h |1 +
  target-arm/helper.c  |   13 +-
  target-arm/kvm.c |  493 
 ++
  target-arm/kvm_arm.h |   32 +++
  target-arm/translate.c   |  141 +-
  util/oslib-posix.c   |2 +-
  21 files changed, 1064 insertions(+), 108 deletions(-)
  create mode 100644 hw/kvm/arm_gic.c
  create mode 100644 linux-headers/asm-arm/kvm.h
  create mode 100644 linux-headers/asm-arm/kvm_para.h
  create mode 100644 linux-headers/asm-generic/kvm_para.h
  create mode 100644 target-arm/kvm.c
  create mode 100644 target-arm/kvm_arm.h
 

Thanks, pulled.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

[Qemu-devel] [PULL 00/13] target-arm queue (feat.ARM KVM support)

2013-03-04 Thread Peter Maydell 
Hi; here's a target-arm pullre. Major business here is the KVM
support patchset, though there are a couple of SRS bugfixes too.
Please pull.

thanks
-- PMM

The following changes since commit 26135ead80fa1fd13e95c162dacfd06f2ba82981:

  target-mips: Fix accumulator selection for MIPS16 and microMIPS (2013-03-05 
01:02:09 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next

for you to fetch changes up to ed4659d10fa2ec16ace367e4fffe6f7ced73112c:

  MAINTAINERS: add entry for ARM KVM guest cores (2013-03-05 00:45:43 +)


Christoffer Dall (1):
  ARM: KVM: Add support for KVM on ARM architecture

Peter Maydell (12):
  target-arm: Factor out handling of SRS instruction
  target-arm: Don't decode RFE or SRS on M profile cores
  oslib-posix: Align to permit transparent hugepages on ARM Linux
  linux-headers: resync from mainline to add ARM KVM headers
  target-arm: Drop CPUARMState* argument from bank_number()
  ARM KVM: save and load VFP registers from kernel
  hw/arm_gic: Add presave/postload hooks
  hw/arm_gic: Convert ARM GIC classes to use init/realize
  target-arm: Use MemoryListener to identify GIC base address for KVM
  hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC
  configure: Enable KVM on ARM
  MAINTAINERS: add entry for ARM KVM guest cores

 MAINTAINERS  |5 +
 configure|2 +-
 hw/a15mpcore.c   |8 +-
 hw/arm/Makefile.objs |1 +
 hw/arm_gic.c |   23 +-
 hw/arm_gic_common.c  |   36 ++-
 hw/arm_gic_internal.h|4 +-
 hw/arm_pic.c |   26 ++
 hw/armv7m_nvic.c |   15 +-
 hw/kvm/arm_gic.c |  167 
 linux-headers/asm-arm/kvm.h  |  180 +
 linux-headers/asm-arm/kvm_para.h |1 +
 linux-headers/asm-generic/kvm_para.h |4 +
 linux-headers/linux/kvm.h|   17 ++
 target-arm/Makefile.objs |1 +
 target-arm/cpu.h |1 +
 target-arm/helper.c  |   13 +-
 target-arm/kvm.c |  493 ++
 target-arm/kvm_arm.h |   32 +++
 target-arm/translate.c   |  141 +-
 util/oslib-posix.c   |2 +-
 21 files changed, 1064 insertions(+), 108 deletions(-)
 create mode 100644 hw/kvm/arm_gic.c
 create mode 100644 linux-headers/asm-arm/kvm.h
 create mode 100644 linux-headers/asm-arm/kvm_para.h
 create mode 100644 linux-headers/asm-generic/kvm_para.h
 create mode 100644 target-arm/kvm.c
 create mode 100644 target-arm/kvm_arm.h