Re: [Qemu-devel] [PULL 00/62] target-arm queue
Peter Maydell peter.mayd...@linaro.org writes: Only took a week for the target-arm queue to fill up again :-) Please pull... ubuntu@build:~/build/qemu$ make CCaarch64-softmmu/gdbstub-xml.o CCaarch64-softmmu/target-arm/cpu.o /home/ubuntu/git/qemu/target-arm/cpu.c: In function ‘arm_cpu_post_init’: /home/ubuntu/git/qemu/target-arm/cpu.c:260:9: error: implicit declaration of function ‘assert_no_error’ [-Werror=implicit-function-declaration] /home/ubuntu/git/qemu/target-arm/cpu.c:260:9: error: nested extern declaration of ‘assert_no_error’ [-Werror=nested-externs] cc1: all warnings being treated as errors make[1]: *** [target-arm/cpu.o] Error 1 make: *** [subdir-aarch64-softmmu] Error 2 Regards, Anthony Liguori thanks -- PMM The following changes since commit f46e720a82ccdf1a521cf459448f3f96ed895d43: qemu_opts_parse(): always check return value (2013-12-16 15:33:48 -0800) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20131217 for you to fetch changes up to 84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c: MAINTAINERS: add myself to maintain allwinner-a10 (2013-12-17 20:12:51 +) target-arm queue: * AES instruction support for 32 bit ARM * pflash01: much better emulation of 2x16bit and similar configs where multiple flash devices are banked together * fixed CBAR handling on Zynq, Highbank * initial AArch64 KVM control support * first two chunks of patches for A64 instruction emulation * new board: canon-a1100 (Canon DIGIC SoC) * new board: cubieboard (Allwinner A10 SoC) Alexander Graf (14): target-arm: A64: add set_pc cpu method target-arm: A64: add stubs for a64 specific helpers target-arm: A64: add support for B and BL insns target-arm: A64: add support for BR, BLR and RET insns target-arm: A64: add support for conditional branches target-arm: A64: add support for 'test and branch' imm target-arm: A64: add support for compare and branch imm target-arm: A64: add support for logical (shifted register) target-arm: A64: add support for ADR and ADRP target-arm: A64: add support for EXTR target-arm: A64: add support for 2-src data processing and DIV target-arm: A64: add support for 2-src shift reg insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for logical (immediate) insns Antony Pavlov (8): ARM: cpu: add reset_hivecs property ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc hw/arm: add very initial support for Canon DIGIC SoC hw/arm/digic: prepare DIGIC-based boards support hw/arm/digic: add timer support hw/arm/digic: add UART support hw/arm/digic: add NOR ROM support MAINTAINERS: Document 'Canon DIGIC' machine Ard Biesheuvel (1): target-arm: add support for v8 AES instructions Claudio Fontana (8): target-arm: A64: provide skeleton for a64 insn decoding target-arm: A64: expand decoding skeleton for system instructions target-arm: A64: add support for conditional select target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for bitfield insns host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for 1-src CLS insn Mian M. Hamayun (2): target-arm: Add minimal KVM AArch64 support hw/arm/boot: Add boot support for AArch64 processor Peter Crosthwaite (8): target-arm/helper.c: Allow cp15.c15 dummy override target-arm: Define and use ARM_FEATURE_CBAR target-arm/cpu: Convert reset CBAR to a property arm/highbank: Use object_new() rather than cpu_arm_init() arm/highbank: Fix CBAR initialisation arm/xilinx_zynq: Use object_new() rather than cpu_arm_init() arm/xilinx_zynq: Implement CBAR initialisation arm/highbank.c: Fix MPCore periphbase name Peter Maydell (9): target-arm/kvm: Split 32 bit only code into its own file target-arm: Clean up handling of AArch64 PSTATE configure: Enable KVM for aarch64 host/target combination hw/arm/boot: Allow easier swapping in of different loader code default-configs: Add config for aarch64-softmmu target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() target-arm: A64: provide functions for accessing FPCR and FPSR target-arm: Support fp registers in gdb stub vmstate: Add support for an array of ptimer_state * Roy Franz (7): rename pflash_t member width to bank_width Add device-width property to pflash_cfi01 return status for each NOR flash device Set proper
Re: [Qemu-devel] [PULL 00/62] target-arm queue
On 20 December 2013 00:14, Anthony Liguori anth...@codemonkey.ws wrote: Peter Maydell peter.mayd...@linaro.org writes: Only took a week for the target-arm queue to fill up again :-) Please pull... ubuntu@build:~/build/qemu$ make CCaarch64-softmmu/gdbstub-xml.o CCaarch64-softmmu/target-arm/cpu.o /home/ubuntu/git/qemu/target-arm/cpu.c: In function ‘arm_cpu_post_init’: /home/ubuntu/git/qemu/target-arm/cpu.c:260:9: error: implicit declaration of function ‘assert_no_error’ [-Werror=implicit-function-declaration] /home/ubuntu/git/qemu/target-arm/cpu.c:260:9: error: nested extern declaration of ‘assert_no_error’ [-Werror=nested-externs] cc1: all warnings being treated as errors make[1]: *** [target-arm/cpu.o] Error 1 make: *** [subdir-aarch64-softmmu] Error 2 Urgh. Looks like the QMP queue included a patch which removes assert_no_error! If you applied pullrequests in chronological order you'd have found this one built and that one didn't :-) thanks -- PMM
[Qemu-devel] [PULL 00/62] target-arm queue
Only took a week for the target-arm queue to fill up again :-) Please pull... thanks -- PMM The following changes since commit f46e720a82ccdf1a521cf459448f3f96ed895d43: qemu_opts_parse(): always check return value (2013-12-16 15:33:48 -0800) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20131217 for you to fetch changes up to 84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c: MAINTAINERS: add myself to maintain allwinner-a10 (2013-12-17 20:12:51 +) target-arm queue: * AES instruction support for 32 bit ARM * pflash01: much better emulation of 2x16bit and similar configs where multiple flash devices are banked together * fixed CBAR handling on Zynq, Highbank * initial AArch64 KVM control support * first two chunks of patches for A64 instruction emulation * new board: canon-a1100 (Canon DIGIC SoC) * new board: cubieboard (Allwinner A10 SoC) Alexander Graf (14): target-arm: A64: add set_pc cpu method target-arm: A64: add stubs for a64 specific helpers target-arm: A64: add support for B and BL insns target-arm: A64: add support for BR, BLR and RET insns target-arm: A64: add support for conditional branches target-arm: A64: add support for 'test and branch' imm target-arm: A64: add support for compare and branch imm target-arm: A64: add support for logical (shifted register) target-arm: A64: add support for ADR and ADRP target-arm: A64: add support for EXTR target-arm: A64: add support for 2-src data processing and DIV target-arm: A64: add support for 2-src shift reg insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for logical (immediate) insns Antony Pavlov (8): ARM: cpu: add reset_hivecs property ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc hw/arm: add very initial support for Canon DIGIC SoC hw/arm/digic: prepare DIGIC-based boards support hw/arm/digic: add timer support hw/arm/digic: add UART support hw/arm/digic: add NOR ROM support MAINTAINERS: Document 'Canon DIGIC' machine Ard Biesheuvel (1): target-arm: add support for v8 AES instructions Claudio Fontana (8): target-arm: A64: provide skeleton for a64 insn decoding target-arm: A64: expand decoding skeleton for system instructions target-arm: A64: add support for conditional select target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for bitfield insns host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for 1-src CLS insn Mian M. Hamayun (2): target-arm: Add minimal KVM AArch64 support hw/arm/boot: Add boot support for AArch64 processor Peter Crosthwaite (8): target-arm/helper.c: Allow cp15.c15 dummy override target-arm: Define and use ARM_FEATURE_CBAR target-arm/cpu: Convert reset CBAR to a property arm/highbank: Use object_new() rather than cpu_arm_init() arm/highbank: Fix CBAR initialisation arm/xilinx_zynq: Use object_new() rather than cpu_arm_init() arm/xilinx_zynq: Implement CBAR initialisation arm/highbank.c: Fix MPCore periphbase name Peter Maydell (9): target-arm/kvm: Split 32 bit only code into its own file target-arm: Clean up handling of AArch64 PSTATE configure: Enable KVM for aarch64 host/target combination hw/arm/boot: Allow easier swapping in of different loader code default-configs: Add config for aarch64-softmmu target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() target-arm: A64: provide functions for accessing FPCR and FPSR target-arm: Support fp registers in gdb stub vmstate: Add support for an array of ptimer_state * Roy Franz (7): rename pflash_t member width to bank_width Add device-width property to pflash_cfi01 return status for each NOR flash device Set proper device-width for vexpress flash Add max device width parameter for NOR devices Fix CFI query responses for NOR flash Fix NOR flash device ID reading liguang (5): hw/timer: add allwinner a10 timer hw/intc: add allwinner A10 interrupt controller hw/arm: add allwinner a10 SoC support hw/arm: add cubieboard support MAINTAINERS: add myself to maintain allwinner-a10 MAINTAINERS | 13 + configure|4 +- default-configs/aarch64-softmmu.mak |6 + default-configs/arm-softmmu.mak |5 + gdb-xml/aarch64-fpu.xml | 86 ++ hw/arm/Makefile.objs |3 + hw/arm/allwinner-a10.c | 103 ++
