From: Yongbok Kim <yongbok....@imgtec.com>
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim <yongbok....@imgtec.com>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: Leon Alrae <leon.al...@imgtec.com>
---
target-mips/msa_helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index 26ffdc7..a1cb48f 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/msa_helper.c
@@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
--
2.1.0
