Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
On Wed, 2017-05-24 at 02:15 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 05/22/2017 02:14 AM, Andrew Jeffery wrote:
> > On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
> > > In ASPEED SoC chip, all register access have following rule.
> > > Most of controller write access is only support 32bit access.
> > > Read is support 8bits/16bits/32bits.
>
> This makes sens thinking about how a DMA controller can take advantage
> of the ADC.
>
> >
> > Thanks for clearing that up Ryan.
> >
> > Phil: I'll rework the model so the reads are 16-bits.
>
> This shouldn't be necessary, QEMU is supposed to supports different
> access size for different implemented size, so you can declare your
> implementation as 32-bit and valid accesses from 8 to 32:
>
> static const MemoryRegionOps aspeed_adc_ops = {
> .read = aspeed_adc_read,
> .write = aspeed_adc_write,
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
> .valid.unaligned = false,
> +.impl.min_access_size = 4,
> +.impl.max_access_size = 4,
> };
>
> This way an I/O access from the CPU or a DMA could use 8/16-bit while
> you keep a 32-bit implementation. The adjustment is done by
> access_with_adjusted_size() from memory.c.
>
> Afaik there is, however, no distinction between read/write different
> access size in current QEMU MemoryRegionOps model.
Yep, I realised all of the above when I went to implement it. Thanks
for pointing it out though!
Andrew
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Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
Hi Andrew,
On 05/22/2017 02:14 AM, Andrew Jeffery wrote:
On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
In ASPEED SoC chip, all register access have following rule.
Most of controller write access is only support 32bit access.
Read is support 8bits/16bits/32bits.
This makes sens thinking about how a DMA controller can take advantage
of the ADC.
Thanks for clearing that up Ryan.
Phil: I'll rework the model so the reads are 16-bits.
This shouldn't be necessary, QEMU is supposed to supports different
access size for different implemented size, so you can declare your
implementation as 32-bit and valid accesses from 8 to 32:
static const MemoryRegionOps aspeed_adc_ops = {
.read = aspeed_adc_read,
.write = aspeed_adc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.valid.unaligned = false,
+.impl.min_access_size = 4,
+.impl.max_access_size = 4,
};
This way an I/O access from the CPU or a DMA could use 8/16-bit while
you keep a 32-bit implementation. The adjustment is done by
access_with_adjusted_size() from memory.c.
Afaik there is, however, no distinction between read/write different
access size in current QEMU MemoryRegionOps model.
Thanks,
Andrew
Best Regards,
Ryan
信驊科技股份有限公司
ASPEED Technology Inc.
2F,No.15,Industry East Road 4.,Hsinchu Science Park, Hsinchu City 30077, Taiwan
Tel: 886-3-578-9568 #857
Fax: 886-3-578-9586
* Email Confidentiality Notice
DISCLAIMER:
This message (and any attachments) may contain legally privileged and/or other
confidential information. If you have received it in error, please notify the
sender by reply e-mail and immediately delete the e-mail and any attachments
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-Original Message-
From: Andrew Jeffery [mailto:and...@aj.id.au]
Sent: Monday, May 22, 2017 8:24 AM
To: Philippe Mathieu-Daudé ; qemu-...@nongnu.org
Cc: Peter Maydell ; Ryan Chen ; Alistair
Francis ; qemu-devel@nongnu.org; Cédric Le Goater ; Joel
Stanley
Subject: Re: [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
Hi Phil,
On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote:
Hi Andrew,
On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
This model implements enough behaviour to do basic functionality
tests such as device initialisation and read out of dummy sample
values. The sample value generation strategy is similar to the STM
ADC already in the tree.
Signed-off-by: Andrew Jeffery
---
hw/adc/Makefile.objs| 1 +
hw/adc/aspeed_adc.c | 246
include/hw/adc/aspeed_adc.h | 33 ++
3 files changed, 280 insertions(+)
create mode 100644 hw/adc/aspeed_adc.c
create mode 100644 include/hw/adc/aspeed_adc.h
diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs index
3f6dfdedaec7..2bf9362ba3c4 100644
--- a/hw/adc/Makefile.objs
+++ b/hw/adc/Makefile.objs
@@ -1 +1,2 @@
obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c new file mode
100644 index ..d08f1684f7bc
--- /dev/null
+++ b/hw/adc/aspeed_adc.c
@@ -0,0 +1,246 @@
+/*
+ * Aspeed ADC
+ *
+ * Andrew Jeffery
+ *
+ * Copyright 2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/aspeed_adc.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+
+#define ASPEED_ADC_ENGINE_CTRL 0x00 #define
+ASPEED_ADC_ENGINE_CH_EN_MASK 0x #define
+ASPEED_ADC_ENGINE_CH_EN(x)((BIT(x)) << 16) #define
+ASPEED_ADC_ENGINE_INIT BIT(8) #define
+ASPEED_ADC_ENGINE_AUTO_COMPBIT(5) #define
+ASPEED_ADC_ENGINE_COMP BIT(4) #define
+ASPEED_ADC_ENGINE_MODE_MASK0x000e #define
+ASPEED_ADC_ENGINE_MODE_OFF(0b000 << 1) #define
+ASPEED_ADC_ENGINE_MODE_STANDBY(0b001 << 1) #define
+ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1) #define
+ASPEED_ADC_ENGINE_EN BIT(0)
+
+#define ASPEED_ADC_L_MASK ((1 << 10) - 1) #define
+ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK) #define
+ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK) #define
+ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 |
+ASPEED_ADC_L_MASK)
+
+static inline uint32_t update_channels(uint32_t current) {
+const uint32_t next = (current + 7) & 0x3ff;
+
+return (next << 16) | next;
+}
+
+static bool breaks_threshold(AspeedADCState *s, int ch_off) {
+const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]);
+const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]);
+const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]);
+const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]);
+const uint32_t b_lower = ASPEED_ADC_
Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
In ASPEED SoC chip, all register access have following rule.
Most of controller write access is only support 32bit access.
Read is support 8bits/16bits/32bits.
Best Regards,
Ryan
信驊科技股份有限公司
ASPEED Technology Inc.
2F,No.15,Industry East Road 4.,Hsinchu Science Park, Hsinchu City 30077, Taiwan
Tel: 886-3-578-9568 #857
Fax: 886-3-578-9586
* Email Confidentiality Notice
DISCLAIMER:
This message (and any attachments) may contain legally privileged and/or other
confidential information. If you have received it in error, please notify the
sender by reply e-mail and immediately delete the e-mail and any attachments
without copying or disclosing the contents. Thank you.
-Original Message-
From: Andrew Jeffery [mailto:and...@aj.id.au]
Sent: Monday, May 22, 2017 8:24 AM
To: Philippe Mathieu-Daudé ; qemu-...@nongnu.org
Cc: Peter Maydell ; Ryan Chen
; Alistair Francis ;
qemu-devel@nongnu.org; Cédric Le Goater ; Joel Stanley
Subject: Re: [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
Hi Phil,
On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
> > This model implements enough behaviour to do basic functionality
> > tests such as device initialisation and read out of dummy sample
> > values. The sample value generation strategy is similar to the STM
> > ADC already in the tree.
> >
> > > > Signed-off-by: Andrew Jeffery
> > ---
> > hw/adc/Makefile.objs| 1 +
> > hw/adc/aspeed_adc.c | 246
> >
> > include/hw/adc/aspeed_adc.h | 33 ++
> > 3 files changed, 280 insertions(+)
> > create mode 100644 hw/adc/aspeed_adc.c
> > create mode 100644 include/hw/adc/aspeed_adc.h
> >
> > diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs index
> > 3f6dfdedaec7..2bf9362ba3c4 100644
> > --- a/hw/adc/Makefile.objs
> > +++ b/hw/adc/Makefile.objs
> > @@ -1 +1,2 @@
> > obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
> > +obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o
> > diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c new file mode
> > 100644 index ..d08f1684f7bc
> > --- /dev/null
> > +++ b/hw/adc/aspeed_adc.c
> > @@ -0,0 +1,246 @@
> > +/*
> > + * Aspeed ADC
> > + *
> > > > + * Andrew Jeffery
> > + *
> > + * Copyright 2017 IBM Corp.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/adc/aspeed_adc.h"
> > +#include "qapi/error.h"
> > +#include "qemu/log.h"
> > +
> > +#define ASPEED_ADC_ENGINE_CTRL 0x00 #define
> > +ASPEED_ADC_ENGINE_CH_EN_MASK 0x #define
> > +ASPEED_ADC_ENGINE_CH_EN(x)((BIT(x)) << 16) #define
> > +ASPEED_ADC_ENGINE_INIT BIT(8) #define
> > +ASPEED_ADC_ENGINE_AUTO_COMPBIT(5) #define
> > +ASPEED_ADC_ENGINE_COMP BIT(4) #define
> > +ASPEED_ADC_ENGINE_MODE_MASK0x000e #define
> > +ASPEED_ADC_ENGINE_MODE_OFF(0b000 << 1) #define
> > +ASPEED_ADC_ENGINE_MODE_STANDBY(0b001 << 1) #define
> > +ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1) #define
> > +ASPEED_ADC_ENGINE_EN BIT(0)
> > +
> > +#define ASPEED_ADC_L_MASK ((1 << 10) - 1) #define
> > +ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK) #define
> > +ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK) #define
> > +ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 |
> > +ASPEED_ADC_L_MASK)
> > +
> > +static inline uint32_t update_channels(uint32_t current) {
> > +const uint32_t next = (current + 7) & 0x3ff;
> > +
> > +return (next << 16) | next;
> > +}
> > +
> > +static bool breaks_threshold(AspeedADCState *s, int ch_off) {
> > +const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]);
> > +const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]);
> > +const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]);
> > +const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]);
> > +const uint32_t b_lower = ASPEED_ADC_L(s->bounds[2 * ch_off +
> > +1]);
> > +const uint32_t b_upper = ASPEED_ADC_H(s->bounds[2 * ch_off +
> > +1]);
> > +
> > +return ((a < a_lower || a > a_upper)) ||
> > + ((b < b_lower || b > b_upper)); }
> > +
> > +static uint32_t read_channel_sample(AspeedADCState *s, int ch_off)
> > +{
> > +uint32_t ret;
> > +
> > +/* Poor man's sampling */
> > +ret = s->channels[ch_off];
> > +s->channels[ch_off] = update_channels(s->channels[ch_off]);
> > +
> > +if (breaks_threshold(s, ch_off)) {
> > +qemu_irq_raise(s->irq);
> > +}
> > +
> > +return ret;
> > +}
> > +
> > +#define TO_INDEX(addr, base) (((addr) - (base)) >> 2)
> > +
> > +static uint64_t aspeed_adc_read(void *opaque, hwaddr addr,
> > + unsigned in
Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
> In ASPEED SoC chip, all register access have following rule.
> Most of controller write access is only support 32bit access.
> Read is support 8bits/16bits/32bits.
Thanks for clearing that up Ryan.
Phil: I'll rework the model so the reads are 16-bits.
Thanks,
Andrew
>
>
>
> Best Regards,
> Ryan
>
> 信驊科技股份有限公司
> ASPEED Technology Inc.
> 2F,No.15,Industry East Road 4.,Hsinchu Science Park, Hsinchu City 30077,
> Taiwan
> Tel: 886-3-578-9568 #857
> Fax: 886-3-578-9586
> * Email Confidentiality Notice
> DISCLAIMER:
> This message (and any attachments) may contain legally privileged and/or
> other confidential information. If you have received it in error, please
> notify the sender by reply e-mail and immediately delete the e-mail and any
> attachments without copying or disclosing the contents. Thank you.
>
> -Original Message-
> > From: Andrew Jeffery [mailto:and...@aj.id.au]
> Sent: Monday, May 22, 2017 8:24 AM
> > To: Philippe Mathieu-Daudé ; qemu-...@nongnu.org
> > > > Cc: Peter Maydell ; Ryan Chen
> > > > ; Alistair Francis ;
> > > > qemu-devel@nongnu.org; Cédric Le Goater ; Joel Stanley
> > > >
> Subject: Re: [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
>
> Hi Phil,
>
> On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote:
> > Hi Andrew,
> >
> > On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
> > > This model implements enough behaviour to do basic functionality
> > > tests such as device initialisation and read out of dummy sample
> > > values. The sample value generation strategy is similar to the STM
> > > ADC already in the tree.
> > >
> > > > > Signed-off-by: Andrew Jeffery
> > >
> > > ---
> > > hw/adc/Makefile.objs| 1 +
> > > hw/adc/aspeed_adc.c | 246
> > >
> > > include/hw/adc/aspeed_adc.h | 33 ++
> > > 3 files changed, 280 insertions(+)
> > > create mode 100644 hw/adc/aspeed_adc.c
> > > create mode 100644 include/hw/adc/aspeed_adc.h
> > >
> > > diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs index
> > > 3f6dfdedaec7..2bf9362ba3c4 100644
> > > --- a/hw/adc/Makefile.objs
> > > +++ b/hw/adc/Makefile.objs
> > > @@ -1 +1,2 @@
> > > obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
> > > +obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o
> > > diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c new file mode
> > > 100644 index ..d08f1684f7bc
> > > --- /dev/null
> > > +++ b/hw/adc/aspeed_adc.c
> > > @@ -0,0 +1,246 @@
> > > +/*
> > > + * Aspeed ADC
> > > + *
> > > > > + * Andrew Jeffery
> > >
> > > + *
> > > + * Copyright 2017 IBM Corp.
> > > + *
> > > + * This code is licensed under the GPL version 2 or later. See
> > > + * the COPYING file in the top-level directory.
> > > + */
> > > +
> > > +#include "qemu/osdep.h"
> > > +#include "hw/adc/aspeed_adc.h"
> > > +#include "qapi/error.h"
> > > +#include "qemu/log.h"
> > > +
> > > +#define ASPEED_ADC_ENGINE_CTRL 0x00 #define
> > > +ASPEED_ADC_ENGINE_CH_EN_MASK 0x #define
> > > +ASPEED_ADC_ENGINE_CH_EN(x)((BIT(x)) << 16) #define
> > > +ASPEED_ADC_ENGINE_INIT BIT(8) #define
> > > +ASPEED_ADC_ENGINE_AUTO_COMPBIT(5) #define
> > > +ASPEED_ADC_ENGINE_COMP BIT(4) #define
> > > +ASPEED_ADC_ENGINE_MODE_MASK0x000e #define
> > > +ASPEED_ADC_ENGINE_MODE_OFF(0b000 << 1) #define
> > > +ASPEED_ADC_ENGINE_MODE_STANDBY(0b001 << 1) #define
> > > +ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1) #define
> > > +ASPEED_ADC_ENGINE_EN BIT(0)
> > > +
> > > +#define ASPEED_ADC_L_MASK ((1 << 10) - 1) #define
> > > +ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK) #define
> > > +ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK) #define
> > > +ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 |
> > > +ASPEED_ADC_L_MASK)
> > > +
> > > +static inline uint32_t update_channels(uint32_t current) {
> > > +const uint32_t next = (current + 7) & 0x3ff;
> > > +
> > > +return (next << 16) | next;
> > > +}
> > > +
> > > +static bool breaks_threshold(AspeedADCState *s, int ch_off) {
> > > +const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]);
> > > +const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]);
> > > +const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]);
> > > +const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]);
> > > +const uint32_t b_lower = ASPEED_ADC_L(s->bounds[2 * ch_off +
> > > +1]);
> > > +const uint32_t b_upper = ASPEED_ADC_H(s->bounds[2 * ch_off +
> > > +1]);
> > > +
> > > +return ((a < a_lower || a > a_upper)) ||
> > > + ((b < b_lower || b > b_upper)); }
> > > +
> > > +static uint32_t read_channel_sample(AspeedADCState *s, int ch_off)
> > > +{
> > > +uint32_t ret;
> > > +
> > > +/*
Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
Hi Phil,
On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
> > This model implements enough behaviour to do basic functionality tests
> > such as device initialisation and read out of dummy sample values. The
> > sample value generation strategy is similar to the STM ADC already in
> > the tree.
> >
> > > > Signed-off-by: Andrew Jeffery
> > ---
> > hw/adc/Makefile.objs| 1 +
> > hw/adc/aspeed_adc.c | 246
> >
> > include/hw/adc/aspeed_adc.h | 33 ++
> > 3 files changed, 280 insertions(+)
> > create mode 100644 hw/adc/aspeed_adc.c
> > create mode 100644 include/hw/adc/aspeed_adc.h
> >
> > diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs
> > index 3f6dfdedaec7..2bf9362ba3c4 100644
> > --- a/hw/adc/Makefile.objs
> > +++ b/hw/adc/Makefile.objs
> > @@ -1 +1,2 @@
> > obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
> > +obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o
> > diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c
> > new file mode 100644
> > index ..d08f1684f7bc
> > --- /dev/null
> > +++ b/hw/adc/aspeed_adc.c
> > @@ -0,0 +1,246 @@
> > +/*
> > + * Aspeed ADC
> > + *
> > > > + * Andrew Jeffery
> > + *
> > + * Copyright 2017 IBM Corp.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/adc/aspeed_adc.h"
> > +#include "qapi/error.h"
> > +#include "qemu/log.h"
> > +
> > +#define ASPEED_ADC_ENGINE_CTRL 0x00
> > +#define ASPEED_ADC_ENGINE_CH_EN_MASK 0x
> > +#define ASPEED_ADC_ENGINE_CH_EN(x)((BIT(x)) << 16)
> > +#define ASPEED_ADC_ENGINE_INIT BIT(8)
> > +#define ASPEED_ADC_ENGINE_AUTO_COMPBIT(5)
> > +#define ASPEED_ADC_ENGINE_COMP BIT(4)
> > +#define ASPEED_ADC_ENGINE_MODE_MASK0x000e
> > +#define ASPEED_ADC_ENGINE_MODE_OFF(0b000 << 1)
> > +#define ASPEED_ADC_ENGINE_MODE_STANDBY(0b001 << 1)
> > +#define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1)
> > +#define ASPEED_ADC_ENGINE_EN BIT(0)
> > +
> > +#define ASPEED_ADC_L_MASK ((1 << 10) - 1)
> > +#define ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK)
> > +#define ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK)
> > +#define ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 |
> > ASPEED_ADC_L_MASK)
> > +
> > +static inline uint32_t update_channels(uint32_t current)
> > +{
> > +const uint32_t next = (current + 7) & 0x3ff;
> > +
> > +return (next << 16) | next;
> > +}
> > +
> > +static bool breaks_threshold(AspeedADCState *s, int ch_off)
> > +{
> > +const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]);
> > +const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]);
> > +const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]);
> > +const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]);
> > +const uint32_t b_lower = ASPEED_ADC_L(s->bounds[2 * ch_off + 1]);
> > +const uint32_t b_upper = ASPEED_ADC_H(s->bounds[2 * ch_off + 1]);
> > +
> > +return ((a < a_lower || a > a_upper)) ||
> > + ((b < b_lower || b > b_upper));
> > +}
> > +
> > +static uint32_t read_channel_sample(AspeedADCState *s, int ch_off)
> > +{
> > +uint32_t ret;
> > +
> > +/* Poor man's sampling */
> > +ret = s->channels[ch_off];
> > +s->channels[ch_off] = update_channels(s->channels[ch_off]);
> > +
> > +if (breaks_threshold(s, ch_off)) {
> > +qemu_irq_raise(s->irq);
> > +}
> > +
> > +return ret;
> > +}
> > +
> > +#define TO_INDEX(addr, base) (((addr) - (base)) >> 2)
> > +
> > +static uint64_t aspeed_adc_read(void *opaque, hwaddr addr,
> > + unsigned int size)
> > +{
> > +AspeedADCState *s = ASPEED_ADC(opaque);
> > +uint64_t ret;
> > +
> > +switch (addr) {
> > +case 0x00:
> > +ret = s->engine_ctrl;
> > +break;
> > +case 0x04:
> > +ret = s->irq_ctrl;
> > +break;
> > +case 0x08:
> > +ret = s->vga_detect_ctrl;
> > +break;
> > +case 0x0c:
> > +ret = s->adc_clk_ctrl;
> > +break;
> > +case 0x10 ... 0x2e:
> > +ret = read_channel_sample(s, TO_INDEX(addr, 0x10));
> > +break;
> > +case 0x30 ... 0x6e:
> > +ret = s->bounds[TO_INDEX(addr, 0x30)];
> > +break;
> > +case 0x70 ... 0xae:
> > +ret = s->hysteresis[TO_INDEX(addr, 0x70)];
> > +break;
> > +case 0xc0:
> > +ret = s->irq_src;
> > +break;
> > +case 0xc4:
> > +ret = s->comp_trim;
> > +break;
> > +default:
> > +qemu_log_mask(LOG_UNIMP, "%s: addr: 0x%lx, size: %u\n", __func__,
> > addr,
> > +size);
> > +ret = 0;
> > +break;
> > +
Re: [Qemu-devel] [Qemu-arm] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model
Hi Andrew,
On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar to the STM ADC already in
the tree.
Signed-off-by: Andrew Jeffery
---
hw/adc/Makefile.objs| 1 +
hw/adc/aspeed_adc.c | 246
include/hw/adc/aspeed_adc.h | 33 ++
3 files changed, 280 insertions(+)
create mode 100644 hw/adc/aspeed_adc.c
create mode 100644 include/hw/adc/aspeed_adc.h
diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs
index 3f6dfdedaec7..2bf9362ba3c4 100644
--- a/hw/adc/Makefile.objs
+++ b/hw/adc/Makefile.objs
@@ -1 +1,2 @@
obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c
new file mode 100644
index ..d08f1684f7bc
--- /dev/null
+++ b/hw/adc/aspeed_adc.c
@@ -0,0 +1,246 @@
+/*
+ * Aspeed ADC
+ *
+ * Andrew Jeffery
+ *
+ * Copyright 2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/aspeed_adc.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+
+#define ASPEED_ADC_ENGINE_CTRL 0x00
+#define ASPEED_ADC_ENGINE_CH_EN_MASK 0x
+#define ASPEED_ADC_ENGINE_CH_EN(x)((BIT(x)) << 16)
+#define ASPEED_ADC_ENGINE_INIT BIT(8)
+#define ASPEED_ADC_ENGINE_AUTO_COMPBIT(5)
+#define ASPEED_ADC_ENGINE_COMP BIT(4)
+#define ASPEED_ADC_ENGINE_MODE_MASK0x000e
+#define ASPEED_ADC_ENGINE_MODE_OFF(0b000 << 1)
+#define ASPEED_ADC_ENGINE_MODE_STANDBY(0b001 << 1)
+#define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1)
+#define ASPEED_ADC_ENGINE_EN BIT(0)
+
+#define ASPEED_ADC_L_MASK ((1 << 10) - 1)
+#define ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK)
+#define ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK)
+#define ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 | ASPEED_ADC_L_MASK)
+
+static inline uint32_t update_channels(uint32_t current)
+{
+const uint32_t next = (current + 7) & 0x3ff;
+
+return (next << 16) | next;
+}
+
+static bool breaks_threshold(AspeedADCState *s, int ch_off)
+{
+const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]);
+const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]);
+const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]);
+const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]);
+const uint32_t b_lower = ASPEED_ADC_L(s->bounds[2 * ch_off + 1]);
+const uint32_t b_upper = ASPEED_ADC_H(s->bounds[2 * ch_off + 1]);
+
+return ((a < a_lower || a > a_upper)) ||
+ ((b < b_lower || b > b_upper));
+}
+
+static uint32_t read_channel_sample(AspeedADCState *s, int ch_off)
+{
+uint32_t ret;
+
+/* Poor man's sampling */
+ret = s->channels[ch_off];
+s->channels[ch_off] = update_channels(s->channels[ch_off]);
+
+if (breaks_threshold(s, ch_off)) {
+qemu_irq_raise(s->irq);
+}
+
+return ret;
+}
+
+#define TO_INDEX(addr, base) (((addr) - (base)) >> 2)
+
+static uint64_t aspeed_adc_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+AspeedADCState *s = ASPEED_ADC(opaque);
+uint64_t ret;
+
+switch (addr) {
+case 0x00:
+ret = s->engine_ctrl;
+break;
+case 0x04:
+ret = s->irq_ctrl;
+break;
+case 0x08:
+ret = s->vga_detect_ctrl;
+break;
+case 0x0c:
+ret = s->adc_clk_ctrl;
+break;
+case 0x10 ... 0x2e:
+ret = read_channel_sample(s, TO_INDEX(addr, 0x10));
+break;
+case 0x30 ... 0x6e:
+ret = s->bounds[TO_INDEX(addr, 0x30)];
+break;
+case 0x70 ... 0xae:
+ret = s->hysteresis[TO_INDEX(addr, 0x70)];
+break;
+case 0xc0:
+ret = s->irq_src;
+break;
+case 0xc4:
+ret = s->comp_trim;
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "%s: addr: 0x%lx, size: %u\n", __func__, addr,
+size);
+ret = 0;
+break;
+}
+
+return ret;
+}
+
+static void aspeed_adc_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int size)
+{
+AspeedADCState *s = ASPEED_ADC(opaque);
+
+switch (addr) {
+case 0x00:
+{
+uint32_t init;
+
+init = !!(val & ASPEED_ADC_ENGINE_EN);
+init *= ASPEED_ADC_ENGINE_INIT;
+
+val &= ~ASPEED_ADC_ENGINE_INIT;
+val |= init;
+}
+
+val &= ~ASPEED_ADC_ENGINE_AUTO_COMP;
+s->engine_ctrl = val;
+
+break;
+case 0x04:
+s->irq_ctrl = val;
+break;
+case 0x08:
+s->vga_detect_ct
