Re: [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller

2017-05-03 Thread Alistair Francis 
(_On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
 wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep 
> ---
> Hi Peter and Alistair,
>
> I created two SPI controllers as per SoC spec
> in hw/arm/msf2_soc.c. I am assuming there has to be two
> busses spi0 and spi1 one for each controller. In board file
> (hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
> I am not able to understand(from hw/ssi/xilinx_spips.c)
> how to create two busses in hw/ssi/msf2_spi.c.
> Please help me here. Below is the output of info qtree:
>
> (qemu) info qtree
> bus: main-system-bus
>   type System
>   dev: msf2-soc, id ""
> cpu-model = "cortex-m3"
>   dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 40011000/0040
> bus: spi0
>   type SSI
>   dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 40001000/0040
> bus: spi0
>   type SSI
>   dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"

Hey Sundeep,

This looks like you have created two SPI devices with one bus each.
What you want (I think) is one SPI device with two busses.

>
> Thanks,
> Sundeep
>
>  hw/ssi/Makefile.objs  |   1 +
>  hw/ssi/msf2_spi.c | 373 
> ++
>  include/hw/ssi/msf2_spi.h | 102 +
>  3 files changed, 476 insertions(+)
>  create mode 100644 hw/ssi/msf2_spi.c
>  create mode 100644 include/hw/ssi/msf2_spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..86445d7 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>  common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
>  common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
>  common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += msf2_spi.o
>
>  obj-$(CONFIG_OMAP) += omap_spi.o
>  obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
> new file mode 100644
> index 000..e7ffa21
> --- /dev/null
> +++ b/hw/ssi/msf2_spi.c
> @@ -0,0 +1,373 @@
> +/*
> + * SPI controller model of Microsemi SmartFusion2.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep 
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ssi/msf2_spi.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#ifndef MSF2_SPI_ERR_DEBUG
> +#define MSF2_SPI_ERR_DEBUG   0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> +if (MSF2_SPI_ERR_DEBUG >= lvl) { \
> +qemu_log("%s: " fmt, __func__, ## args); \
> +} \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void txfifo_reset(MSF2SpiState *s)
> +{
> +fifo32_reset(>tx_fifo);
> +
> +s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> +s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSF2SpiState *s)
> +{
> +fifo32_reset(>rx_fifo);
> +
> +s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> +s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSF2SpiState *s)
> +{
> +int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> +if (0 <= size && size <= 8) {
> +s->fifo_depth = 32;
> +}
> +if (9 <= size && size <= 16) {
> +s->fifo_depth = 16;
> +}
> +if (17 <= size && size <= 32) {
> +s->fifo_depth = 8;
> +}
> +}
> +
> +static void msf2_spi_do_reset(MSF2SpiState *s)
> +{
> +memset(s->regs, 0, sizeof s->regs);
> +s->regs[R_SPI_CONTROL] = 0x8102;
> +

Re: [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller

2017-05-01 Thread sundeep subbaraya 
Hi,

Gentle Reminder.

Thanks,
Sundeep

On Fri, Apr 28, 2017 at 10:21 PM, Subbaraya Sundeep
 wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep 
> ---
> Hi Peter and Alistair,
>
> I created two SPI controllers as per SoC spec
> in hw/arm/msf2_soc.c. I am assuming there has to be two
> busses spi0 and spi1 one for each controller. In board file
> (hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
> I am not able to understand(from hw/ssi/xilinx_spips.c)
> how to create two busses in hw/ssi/msf2_spi.c.
> Please help me here. Below is the output of info qtree:
>
> (qemu) info qtree
> bus: main-system-bus
>   type System
>   dev: msf2-soc, id ""
> cpu-model = "cortex-m3"
>   dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 40011000/0040
> bus: spi0
>   type SSI
>   dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 40001000/0040
> bus: spi0
>   type SSI
>   dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"
>
> Thanks,
> Sundeep
>
>  hw/ssi/Makefile.objs  |   1 +
>  hw/ssi/msf2_spi.c | 373 
> ++
>  include/hw/ssi/msf2_spi.h | 102 +
>  3 files changed, 476 insertions(+)
>  create mode 100644 hw/ssi/msf2_spi.c
>  create mode 100644 include/hw/ssi/msf2_spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..86445d7 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>  common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
>  common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
>  common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += msf2_spi.o
>
>  obj-$(CONFIG_OMAP) += omap_spi.o
>  obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
> new file mode 100644
> index 000..e7ffa21
> --- /dev/null
> +++ b/hw/ssi/msf2_spi.c
> @@ -0,0 +1,373 @@
> +/*
> + * SPI controller model of Microsemi SmartFusion2.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep 
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ssi/msf2_spi.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#ifndef MSF2_SPI_ERR_DEBUG
> +#define MSF2_SPI_ERR_DEBUG   0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> +if (MSF2_SPI_ERR_DEBUG >= lvl) { \
> +qemu_log("%s: " fmt, __func__, ## args); \
> +} \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void txfifo_reset(MSF2SpiState *s)
> +{
> +fifo32_reset(>tx_fifo);
> +
> +s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> +s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSF2SpiState *s)
> +{
> +fifo32_reset(>rx_fifo);
> +
> +s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> +s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSF2SpiState *s)
> +{
> +int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> +if (0 <= size && size <= 8) {
> +s->fifo_depth = 32;
> +}
> +if (9 <= size && size <= 16) {
> +s->fifo_depth = 16;
> +}
> +if (17 <= size && size <= 32) {
> +s->fifo_depth = 8;
> +}
> +}
> +
> +static void msf2_spi_do_reset(MSF2SpiState *s)
> +{
> +memset(s->regs, 0, sizeof s->regs);
> +s->regs[R_SPI_CONTROL] = 0x8102;
> +s->regs[R_SPI_DFSIZE] = 0x4;
> +s->regs[R_SPI_STATUS] = 0x2440;
> +s->regs[R_SPI_CLKGEN] =

[Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller

2017-04-28 Thread Subbaraya Sundeep 
Modelled Microsemi's Smartfusion2 SPI controller.

Signed-off-by: Subbaraya Sundeep 
---
Hi Peter and Alistair,

I created two SPI controllers as per SoC spec 
in hw/arm/msf2_soc.c. I am assuming there has to be two
busses spi0 and spi1 one for each controller. In board file
(hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
I am not able to understand(from hw/ssi/xilinx_spips.c)
how to create two busses in hw/ssi/msf2_spi.c. 
Please help me here. Below is the output of info qtree:

(qemu) info qtree
bus: main-system-bus
  type System
  dev: msf2-soc, id ""
cpu-model = "cortex-m3"
  dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 40011000/0040
bus: spi0
  type SSI
  dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 40001000/0040
bus: spi0
  type SSI
  dev: s25sl12801, id ""
gpio-in "ssi-gpio-cs" 1
nonvolatile-cfg = 36863 (0x8fff)
spansion-cr1nv = 0 (0x0)
spansion-cr2nv = 1 (0x1)
spansion-cr3nv = 2 (0x2)
spansion-cr4nv = 16 (0x10)
drive = "mtd0"

Thanks,
Sundeep

 hw/ssi/Makefile.objs  |   1 +
 hw/ssi/msf2_spi.c | 373 ++
 include/hw/ssi/msf2_spi.h | 102 +
 3 files changed, 476 insertions(+)
 create mode 100644 hw/ssi/msf2_spi.c
 create mode 100644 include/hw/ssi/msf2_spi.h

diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 487add2..86445d7 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
 common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+common-obj-$(CONFIG_MSF2) += msf2_spi.o
 
 obj-$(CONFIG_OMAP) += omap_spi.o
 obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
new file mode 100644
index 000..e7ffa21
--- /dev/null
+++ b/hw/ssi/msf2_spi.c
@@ -0,0 +1,373 @@
+/*
+ * SPI controller model of Microsemi SmartFusion2.
+ *
+ * Copyright (C) 2017 Subbaraya Sundeep 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ssi/msf2_spi.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+#ifndef MSF2_SPI_ERR_DEBUG
+#define MSF2_SPI_ERR_DEBUG   0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+if (MSF2_SPI_ERR_DEBUG >= lvl) { \
+qemu_log("%s: " fmt, __func__, ## args); \
+} \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void txfifo_reset(MSF2SpiState *s)
+{
+fifo32_reset(>tx_fifo);
+
+s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
+s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
+}
+
+static void rxfifo_reset(MSF2SpiState *s)
+{
+fifo32_reset(>rx_fifo);
+
+s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+}
+
+static void set_fifodepth(MSF2SpiState *s)
+{
+int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
+
+if (0 <= size && size <= 8) {
+s->fifo_depth = 32;
+}
+if (9 <= size && size <= 16) {
+s->fifo_depth = 16;
+}
+if (17 <= size && size <= 32) {
+s->fifo_depth = 8;
+}
+}
+
+static void msf2_spi_do_reset(MSF2SpiState *s)
+{
+memset(s->regs, 0, sizeof s->regs);
+s->regs[R_SPI_CONTROL] = 0x8102;
+s->regs[R_SPI_DFSIZE] = 0x4;
+s->regs[R_SPI_STATUS] = 0x2440;
+s->regs[R_SPI_CLKGEN] = 0x7;
+s->regs[R_SPI_STAT8] = 0x7;
+s->regs[R_SPI_RIS] = 0x0;
+
+s->fifo_depth = 4;
+s->frame_count = 1;
+s->enabled = false;
+
+rxfifo_reset(s);
+txfifo_reset(s);
+}
+
+static void update_mis(MSF2SpiState *s)
+{
+uint32_t reg = s->regs[R_SPI_CONTROL];
+uint32_t tmp;
+
+/*
+ * form the Control register interrupt enable bits
+ * same as RIS, MIS and Interrupt clear