[RFC 8/8] Got GPU init working. Stops at probing display
From: Aaron Dominick
---
hw/display/ati.c | 9 +-
hw/display/r300.c | 571 +-
hw/display/r300.h | 77 ++-
3 files changed, 544 insertions(+), 113 deletions(-)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index db3b254316..1d36233163 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -44,7 +44,7 @@ enum { VGA_MODE, EXT_MODE };
static void ati_vga_switch_mode(ATIVGAState *s)
{
-DPRINTF("%d -> %d\n",
+qemu_log("%d -> %d\n",
s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
/* Extended mode enabled */
@@ -88,7 +88,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
}
assert(bpp != 0);
-DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp,
offs);
+qemu_log("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp,
offs);
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(>vga, 0, VBE_DISPI_DISABLED);
s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
@@ -111,14 +111,14 @@ static void ati_vga_switch_mode(ATIVGAState *s)
vbe_ioport_write_data(>vga, 0, stride);
stride *= bypp;
if (offs % stride) {
-DPRINTF("CRTC offset is not multiple of pitch\n");
+qemu_log("CRTC offset is not multiple of pitch\n");
vbe_ioport_write_index(>vga, 0,
VBE_DISPI_INDEX_X_OFFSET);
vbe_ioport_write_data(>vga, 0, offs % stride / bypp);
}
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
vbe_ioport_write_data(>vga, 0, offs / stride);
-DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n",
+qemu_log("VBE offset (%d,%d), vbe_start_addr=%x\n",
s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],
s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],
s->vga.vbe_start_addr);
@@ -129,6 +129,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
s->mode = VGA_MODE;
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(>vga, 0, VBE_DISPI_DISABLED);
+qemu_log("VGA MODE %d \n",s->mode);
}
}
diff --git a/hw/display/r300.c b/hw/display/r300.c
index 074dbf5b2d..5bd71142a8 100644
--- a/hw/display/r300.c
+++ b/hw/display/r300.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "r300.h"
#include "r300_reg.h"
+#include "r100d.h"
#include "radeon_reg.h"
#include "vga-access.h"
#include "hw/qdev-properties.h"
@@ -38,18 +39,20 @@ static const struct {
uint16_t dev_id;
} r300_model_aliases[] = {
{ "radeon9500", PCI_DEVICE_ID_ATI_RADEON_9500_PRO },
+{ "radeon9700", PCI_DEVICE_ID_ATI_RADEON_9700 }
};
enum { VGA_MODE, EXT_MODE };
static void r300_vga_switch_mode(RADVGAState *s)
{
-DPRINTF("%d -> %d\n",
-s->mode, !!(s->regs.crtc_gen_cntl & RADEON_CRTC_EXT_DISP_EN));
-if (s->regs.crtc_gen_cntl & RADEON_CRTC_EXT_DISP_EN) {
+qemu_log(" R300 %d -> %d\n",
+s->mode, !(s->regs.crtc_gen_cntl & RADEON_CRTC_EN));
+qemu_log("R300 RADEON_CRTC_EXT_DISP_EN = %08x CRTC_GEN_CNTL = %08x
",RADEON_CRTC_EN,s->regs.crtc_gen_cntl);
+if (s->regs.crtc_gen_cntl & ~RADEON_CRTC_EN) {
/* Extended mode enabled */
s->mode = EXT_MODE;
-if (s->regs.crtc_gen_cntl & RADEON_CRTC2_EN) {
+if (s->regs.crtc_gen_cntl & ~RADEON_CRTC_EN) {
/* CRT controller enabled, use CRTC values */
/* FIXME Should these be the same as VGA CRTC regs? */
uint32_t offs = s->regs.crtc_offset & 0x07ff;
@@ -65,32 +68,32 @@ static void r300_vga_switch_mode(RADVGAState *s)
}
h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
v = (s->regs.crtc_v_total_disp >> 16) + 1;
-// switch (s->regs.crtc_gen_cntl & RADEON_CRTC_CUR_MODE_MASK) {
-// // case RADEON_CRTC_PIX_WIDTH_4BPP:
-// // bpp = 4;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_8BPP:
-// // bpp = 8;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_15BPP:
-// // bpp = 15;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_16BPP:
-// // bpp = 16;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_24BPP:
-// // bpp = 24;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_32BPP:
-// // bpp = 32;
-// // break;
-// default:
-// qemu_log_mask(LOG_UNIMP, "Unsupported bpp
[RFC 8/8] Got GPU init working. Stops at probing display
From: Aaron Dominick
---
hw/display/ati.c | 9 +-
hw/display/r300.c | 571 +-
hw/display/r300.h | 77 ++-
3 files changed, 544 insertions(+), 113 deletions(-)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index db3b254316..1d36233163 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -44,7 +44,7 @@ enum { VGA_MODE, EXT_MODE };
static void ati_vga_switch_mode(ATIVGAState *s)
{
-DPRINTF("%d -> %d\n",
+qemu_log("%d -> %d\n",
s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
/* Extended mode enabled */
@@ -88,7 +88,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
}
assert(bpp != 0);
-DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp,
offs);
+qemu_log("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp,
offs);
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(>vga, 0, VBE_DISPI_DISABLED);
s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN ||
@@ -111,14 +111,14 @@ static void ati_vga_switch_mode(ATIVGAState *s)
vbe_ioport_write_data(>vga, 0, stride);
stride *= bypp;
if (offs % stride) {
-DPRINTF("CRTC offset is not multiple of pitch\n");
+qemu_log("CRTC offset is not multiple of pitch\n");
vbe_ioport_write_index(>vga, 0,
VBE_DISPI_INDEX_X_OFFSET);
vbe_ioport_write_data(>vga, 0, offs % stride / bypp);
}
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
vbe_ioport_write_data(>vga, 0, offs / stride);
-DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n",
+qemu_log("VBE offset (%d,%d), vbe_start_addr=%x\n",
s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],
s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],
s->vga.vbe_start_addr);
@@ -129,6 +129,7 @@ static void ati_vga_switch_mode(ATIVGAState *s)
s->mode = VGA_MODE;
vbe_ioport_write_index(>vga, 0, VBE_DISPI_INDEX_ENABLE);
vbe_ioport_write_data(>vga, 0, VBE_DISPI_DISABLED);
+qemu_log("VGA MODE %d \n",s->mode);
}
}
diff --git a/hw/display/r300.c b/hw/display/r300.c
index 074dbf5b2d..5bd71142a8 100644
--- a/hw/display/r300.c
+++ b/hw/display/r300.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "r300.h"
#include "r300_reg.h"
+#include "r100d.h"
#include "radeon_reg.h"
#include "vga-access.h"
#include "hw/qdev-properties.h"
@@ -38,18 +39,20 @@ static const struct {
uint16_t dev_id;
} r300_model_aliases[] = {
{ "radeon9500", PCI_DEVICE_ID_ATI_RADEON_9500_PRO },
+{ "radeon9700", PCI_DEVICE_ID_ATI_RADEON_9700 }
};
enum { VGA_MODE, EXT_MODE };
static void r300_vga_switch_mode(RADVGAState *s)
{
-DPRINTF("%d -> %d\n",
-s->mode, !!(s->regs.crtc_gen_cntl & RADEON_CRTC_EXT_DISP_EN));
-if (s->regs.crtc_gen_cntl & RADEON_CRTC_EXT_DISP_EN) {
+qemu_log(" R300 %d -> %d\n",
+s->mode, !(s->regs.crtc_gen_cntl & RADEON_CRTC_EN));
+qemu_log("R300 RADEON_CRTC_EXT_DISP_EN = %08x CRTC_GEN_CNTL = %08x
",RADEON_CRTC_EN,s->regs.crtc_gen_cntl);
+if (s->regs.crtc_gen_cntl & ~RADEON_CRTC_EN) {
/* Extended mode enabled */
s->mode = EXT_MODE;
-if (s->regs.crtc_gen_cntl & RADEON_CRTC2_EN) {
+if (s->regs.crtc_gen_cntl & ~RADEON_CRTC_EN) {
/* CRT controller enabled, use CRTC values */
/* FIXME Should these be the same as VGA CRTC regs? */
uint32_t offs = s->regs.crtc_offset & 0x07ff;
@@ -65,32 +68,32 @@ static void r300_vga_switch_mode(RADVGAState *s)
}
h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
v = (s->regs.crtc_v_total_disp >> 16) + 1;
-// switch (s->regs.crtc_gen_cntl & RADEON_CRTC_CUR_MODE_MASK) {
-// // case RADEON_CRTC_PIX_WIDTH_4BPP:
-// // bpp = 4;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_8BPP:
-// // bpp = 8;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_15BPP:
-// // bpp = 15;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_16BPP:
-// // bpp = 16;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_24BPP:
-// // bpp = 24;
-// // break;
-// // case RADEON_CRTC_PIX_WIDTH_32BPP:
-// // bpp = 32;
-// // break;
-// default:
-// qemu_log_mask(LOG_UNIMP, "Unsupported bpp
