Introduce the PEXTUW opcode (Parallel Extend Upper from Word).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tx79.decode | 4
target/mips/tx79_translate.c | 26 ++
2 files changed, 30 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index d1c07c7d901..ead5f8281e5 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -35,6 +35,10 @@ PSUBW 011100 . . . 1 001000
@rs_rt_rd
PSUBH 011100 . . . 00101 001000 @rs_rt_rd
PSUBB 011100 . . . 01001 001000 @rs_rt_rd
+# MMI1
+
+PEXTUW 011100 . . . 10010 101000 @rs_rt_rd
+
# MMI2
PCPYLD 011100 . . . 01110 001001 @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 23146f6bfac..0a2fb28600b 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -332,6 +332,32 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
* PEXTLW rd, rs, rtParallel Extend Lower from Word
*/
+/* Parallel Extend Upper from Word */
+static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
+{
+TCGv_i64 ax, bx;
+
+if (a->rd == 0) {
+/* nop */
+return true;
+}
+
+ax = tcg_temp_new_i64();
+bx = tcg_temp_new_i64();
+
+gen_load_gpr_hi(ax, a->rs);
+gen_load_gpr_hi(bx, a->rt);
+
+tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32);
+tcg_gen_shri_i64(bx, bx, 32);
+tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32);
+
+tcg_temp_free(bx);
+tcg_temp_free(ax);
+
+return true;
+}
+
/*
* Others (16 instructions)
*
--
2.26.2