Re: [RFC PATCH v2 3/4] target/ppc: Remove the software TLB model of 7450 CPUs
On 12/1/21 00:01, Fabiano Rosas wrote:
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 2029134431.406753-1-faro...@linux.ibm.com
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/cpu-qom.h | 6 +-
target/ppc/cpu.h | 4 +---
target/ppc/cpu_init.c| 26 --
target/ppc/excp_helper.c | 29 -
target/ppc/helper.h | 2 --
target/ppc/mmu_common.c | 19 ---
target/ppc/mmu_helper.c | 31 ---
target/ppc/translate.c | 26 --
8 files changed, 6 insertions(+), 137 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 5800fa324e..ef9e324474 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -45,7 +45,11 @@ enum powerpc_mmu_t {
POWERPC_MMU_32B= 0x0001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x0002,
-/* PowerPC 74xx MMU with software TLB */
+/*
+ * PowerPC 74xx MMU with software TLB (this has been
+ * disabled, see git history for more information.
+ * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
+ */
POWERPC_MMU_SOFT_74xx = 0x0003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x0004,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e946da5f3a..432d609094 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2138,8 +2138,6 @@ enum {
PPC_SEGMENT= 0x0200ULL,
/* PowerPC 6xx TLB management instructions
*/
PPC_6xx_TLB= 0x0400ULL,
-/* PowerPC 74xx TLB management instructions */
-PPC_74xx_TLB = 0x0800ULL,
/* PowerPC 40x TLB management instructions
*/
PPC_40x_TLB= 0x1000ULL,
/* segment register access instructions for PowerPC 64 "bridge"
*/
@@ -2196,7 +2194,7 @@ enum {
| PPC_CACHE_DCBZ \
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
-| PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
+| PPC_40x_TLB | PPC_SEGMENT_64B \
| PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 962acf295f..ed0e2136d9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -945,31 +945,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x);
}
-static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
-env->nb_tlb = nb_tlbs;
-env->nb_ways = nb_ways;
-env->id_tlbs = 1;
-env->tlb_type = TLB_6XX;
-/* XXX : not implemented */
-spr_register(env, SPR_PTEHI, "PTEHI",
- SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_PTELO, "PTELO",
- SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_TLBMISS, "TLBMISS",
-
[RFC PATCH v2 3/4] target/ppc: Remove the software TLB model of 7450 CPUs
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 2029134431.406753-1-faro...@linux.ibm.com
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu-qom.h | 6 +-
target/ppc/cpu.h | 4 +---
target/ppc/cpu_init.c| 26 --
target/ppc/excp_helper.c | 29 -
target/ppc/helper.h | 2 --
target/ppc/mmu_common.c | 19 ---
target/ppc/mmu_helper.c | 31 ---
target/ppc/translate.c | 26 --
8 files changed, 6 insertions(+), 137 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 5800fa324e..ef9e324474 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -45,7 +45,11 @@ enum powerpc_mmu_t {
POWERPC_MMU_32B= 0x0001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x0002,
-/* PowerPC 74xx MMU with software TLB */
+/*
+ * PowerPC 74xx MMU with software TLB (this has been
+ * disabled, see git history for more information.
+ * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
+ */
POWERPC_MMU_SOFT_74xx = 0x0003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x0004,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e946da5f3a..432d609094 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2138,8 +2138,6 @@ enum {
PPC_SEGMENT= 0x0200ULL,
/* PowerPC 6xx TLB management instructions */
PPC_6xx_TLB= 0x0400ULL,
-/* PowerPC 74xx TLB management instructions */
-PPC_74xx_TLB = 0x0800ULL,
/* PowerPC 40x TLB management instructions */
PPC_40x_TLB= 0x1000ULL,
/* segment register access instructions for PowerPC 64 "bridge"*/
@@ -2196,7 +2194,7 @@ enum {
| PPC_CACHE_DCBZ \
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
-| PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
+| PPC_40x_TLB | PPC_SEGMENT_64B \
| PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 962acf295f..ed0e2136d9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -945,31 +945,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x);
}
-static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
-env->nb_tlb = nb_tlbs;
-env->nb_ways = nb_ways;
-env->id_tlbs = 1;
-env->tlb_type = TLB_6XX;
-/* XXX : not implemented */
-spr_register(env, SPR_PTEHI, "PTEHI",
- SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_PTELO, "PTELO",
- SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
- 0x);
-/* XXX : not implemented */
-spr_register(env, SPR_TLBMISS, "TLBMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- _read_generic, _write_generic,
- 0x);
-#endif
-}
