Re: [RFC v4 51/70] target/riscv: rvv-1.0: mask-register logical instructions

[Richard Henderson]

On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang 
> 
> Signed-off-by: Frank Chang 
> ---
>  target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
>  target/riscv/vector_helper.c| 4 
>  2 files changed, 2 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson 


r~

[RFC v4 51/70] target/riscv: rvv-1.0: mask-register logical instructions

[frank . chang]

From: Frank Chang 

Signed-off-by: Frank Chang 
---
 target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
 target/riscv/vector_helper.c| 4 
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index c3be3dd97ff..41789a2ba6f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2987,7 +2987,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
 #define GEN_MM_TRANS(NAME) \
 static bool trans_##NAME(DisasContext *s, arg_r *a)\
 {  \
-if (vext_check_isa_ill(s)) {   \
+if (require_rvv(s) &&  \
+vext_check_isa_ill(s)) {   \
 uint32_t data = 0; \
 gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
 TCGLabel *over = gen_new_label();  \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 766622d3878..ea1715b5484 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4490,7 +4490,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,  
\
   void *vs2, CPURISCVState *env,  \
   uint32_t desc)  \
 { \
-uint32_t vlmax = env_archcpu(env)->cfg.vlen;  \
 uint32_t vl = env->vl;\
 uint32_t i;   \
 int a, b; \
@@ -4500,9 +4499,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,  
\
 b = vext_elem_mask(vs2, i);   \
 vext_set_elem_mask(vd, i, OP(b, a));  \
 } \
-for (; i < vlmax; i++) {  \
-vext_set_elem_mask(vd, i, 0); \
-} \
 }
 
 #define DO_NAND(N, M)  (!(N & M))
-- 
2.17.1