From: Zack Buhman <z...@buhman.org> CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related instructions, but not to the PC-relative mov* instructions.
I verified the existence of an illegal slot exception on a SH7091 when any of these instructions are attempted inside a delay slot. This also matches the behavior described in the SH-4 ISA manual. Signed-off-by: Zack Buhman <z...@buhman.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Message-Id: <20240407150705.5965-1-z...@buhman.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewd-by: Yoshinori Sato <ys...@users.sourceforge.jp> (cherry picked from commit b754cb2dcde26a7bc8a9d17bb6900a0ac0dd38e2) Signed-off-by: Michael Tokarev <m...@tls.msk.ru> (Mjt: trivial context (whitespace before comments) fixup) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7db3468b01..8d6eae7ddf 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -528,6 +528,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_movi_i32(REG(B11_8), B7_0s); return; case 0x9000: /* mov.w @(disp,PC),Rn */ + CHECK_NOT_DELAY_SLOT { TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); @@ -535,6 +536,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0xd000: /* mov.l @(disp,PC),Rn */ + CHECK_NOT_DELAY_SLOT { TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); @@ -1295,6 +1297,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0xc700: /* mova @(disp,PC),R0 */ + CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + 4 + B7_0 * 4) & ~3); return; -- 2.39.2