Re: [PATCH RESEND 09/18] i386: Fix comment style in topology.h
On Wed, Feb 15, 2023 at 06:54:15PM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 18:54:15 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 09/18] i386: Fix comment style in topology.h
>
> 在 2023/2/13 17:36, Zhao Liu 写道:
> > From: Zhao Liu
> >
> > For function comments in this file, keep the comment style consistent
> > with other places.
> >
> > Signed-off-by: Zhao Liu
> nit：Better to move this cleanup patch to top of the series.
Ok, will do that. Thanks!
> > ---
> > include/hw/i386/topology.h | 33 +
> > 1 file changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> > index b0174c18b7bd..5de905dc00d3 100644
> > --- a/include/hw/i386/topology.h
> > +++ b/include/hw/i386/topology.h
> > @@ -24,7 +24,8 @@
> > #ifndef HW_I386_TOPOLOGY_H
> > #define HW_I386_TOPOLOGY_H
> > -/* This file implements the APIC-ID-based CPU topology enumeration logic,
> > +/*
> > + * This file implements the APIC-ID-based CPU topology enumeration logic,
> >* documented at the following document:
> >* Intel® 64 Architecture Processor Topology Enumeration
> >*
> > http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
> > @@ -41,7 +42,8 @@
> > #include "qemu/bitops.h"
> > -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC
> > support
> > +/*
> > + * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC
> > support
> >*/
> > typedef uint32_t apic_id_t;
> > @@ -60,8 +62,7 @@ typedef struct X86CPUTopoInfo {
> > unsigned threads_per_core;
> > } X86CPUTopoInfo;
> > -/* Return the bit width needed for 'count' IDs
> > - */
> > +/* Return the bit width needed for 'count' IDs */
> > static unsigned apicid_bitwidth_for_count(unsigned count)
> > {
> > g_assert(count >= 1);
> > @@ -69,15 +70,13 @@ static unsigned apicid_bitwidth_for_count(unsigned
> > count)
> > return count ? 32 - clz32(count) : 0;
> > }
> > -/* Bit width of the SMT_ID (thread ID) field on the APIC ID
> > - */
> > +/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
> > static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
> > {
> > return apicid_bitwidth_for_count(topo_info->threads_per_core);
> > }
> > -/* Bit width of the Core_ID field
> > - */
> > +/* Bit width of the Core_ID field */
> > static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
> > {
> > /*
> > @@ -94,8 +93,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
> > *topo_info)
> > return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
> > }
> > -/* Bit offset of the Core_ID field
> > - */
> > +/* Bit offset of the Core_ID field */
> > static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
> > {
> > return apicid_smt_width(topo_info);
> > @@ -107,14 +105,14 @@ static inline unsigned
> > apicid_die_offset(X86CPUTopoInfo *topo_info)
> > return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
> > }
> > -/* Bit offset of the Pkg_ID (socket ID) field
> > - */
> > +/* Bit offset of the Pkg_ID (socket ID) field */
> > static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
> > {
> > return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
> > }
> > -/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
> > +/*
> > + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
> >*
> >* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
> >*/
> > @@ -127,7 +125,8 @@ static inline apic_id_t
> > x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
> > topo_ids->smt_id;
> > }
> > -/* Calculate thread/core/package IDs for a specific topology,
> > +/*
> > + * Calculate thread/core/package IDs for a specific topology,
> >* based on (contiguous) CPU index
> >*/
> > static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
> > @@ -154,7 +153,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo
> > *topo_info,
> > topo_ids->smt_id = cpu_index % nr_threads;
> > }
> > -/* Calculate thread/core/package IDs for a specific topology,
> > +/*
> > + * Calculate thread/core/package IDs for a specific topology,
> >* based on APIC ID
> >*/
> > static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
> > @@ -178,7 +178,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
> > apicid,
> > topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
> > }
> > -/* Make APIC ID for the CPU 'cpu_index'
> > +/*
> > + * Make APIC ID for the CPU 'cpu_index'
> >*
> >* 'cpu_index' is a sequential, contiguous ID for the CPU.
> >*/
>
Re: [PATCH RESEND 09/18] i386: Fix comment style in topology.h
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other places.
Signed-off-by: Zhao Liu
nit：Better to move this cleanup patch to top of the series.
---
include/hw/i386/topology.h | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b0174c18b7bd..5de905dc00d3 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -24,7 +24,8 @@
#ifndef HW_I386_TOPOLOGY_H
#define HW_I386_TOPOLOGY_H
-/* This file implements the APIC-ID-based CPU topology enumeration logic,
+/*
+ * This file implements the APIC-ID-based CPU topology enumeration logic,
* documented at the following document:
* Intel® 64 Architecture Processor Topology Enumeration
*
http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
@@ -41,7 +42,8 @@
#include "qemu/bitops.h"
-/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
+/*
+ * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
*/
typedef uint32_t apic_id_t;
@@ -60,8 +62,7 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;
-/* Return the bit width needed for 'count' IDs
- */
+/* Return the bit width needed for 'count' IDs */
static unsigned apicid_bitwidth_for_count(unsigned count)
{
g_assert(count >= 1);
@@ -69,15 +70,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
return count ? 32 - clz32(count) : 0;
}
-/* Bit width of the SMT_ID (thread ID) field on the APIC ID
- */
+/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
-/* Bit width of the Core_ID field
- */
+/* Bit width of the Core_ID field */
static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
/*
@@ -94,8 +93,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
*topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
-/* Bit offset of the Core_ID field
- */
+/* Bit offset of the Core_ID field */
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
return apicid_smt_width(topo_info);
@@ -107,14 +105,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo
*topo_info)
return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
-/* Bit offset of the Pkg_ID (socket ID) field
- */
+/* Bit offset of the Pkg_ID (socket ID) field */
static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
-/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
@@ -127,7 +125,8 @@ static inline apic_id_t
x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
topo_ids->smt_id;
}
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
* based on (contiguous) CPU index
*/
static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
@@ -154,7 +153,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo
*topo_info,
topo_ids->smt_id = cpu_index % nr_threads;
}
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
* based on APIC ID
*/
static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
@@ -178,7 +178,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
}
-/* Make APIC ID for the CPU 'cpu_index'
+/*
+ * Make APIC ID for the CPU 'cpu_index'
*
* 'cpu_index' is a sequential, contiguous ID for the CPU.
*/
Re: [PATCH RESEND 09/18] i386: Fix comment style in topology.h
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
For function comments in this file, keep the comment style consistent
with other places.
Signed-off-by: Zhao Liu
---
include/hw/i386/topology.h | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b0174c18b7bd..5de905dc00d3 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -24,7 +24,8 @@
#ifndef HW_I386_TOPOLOGY_H
#define HW_I386_TOPOLOGY_H
-/* This file implements the APIC-ID-based CPU topology enumeration logic,
+/*
+ * This file implements the APIC-ID-based CPU topology enumeration logic,
* documented at the following document:
* Intel® 64 Architecture Processor Topology Enumeration
*
http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
@@ -41,7 +42,8 @@
#include "qemu/bitops.h"
-/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
+/*
+ * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
*/
typedef uint32_t apic_id_t;
@@ -60,8 +62,7 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;
-/* Return the bit width needed for 'count' IDs
- */
+/* Return the bit width needed for 'count' IDs */
static unsigned apicid_bitwidth_for_count(unsigned count)
{
g_assert(count >= 1);
@@ -69,15 +70,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
return count ? 32 - clz32(count) : 0;
}
-/* Bit width of the SMT_ID (thread ID) field on the APIC ID
- */
+/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
-/* Bit width of the Core_ID field
- */
+/* Bit width of the Core_ID field */
static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
/*
@@ -94,8 +93,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
*topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
-/* Bit offset of the Core_ID field
- */
+/* Bit offset of the Core_ID field */
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
return apicid_smt_width(topo_info);
@@ -107,14 +105,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo
*topo_info)
return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
-/* Bit offset of the Pkg_ID (socket ID) field
- */
+/* Bit offset of the Pkg_ID (socket ID) field */
static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
-/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
@@ -127,7 +125,8 @@ static inline apic_id_t
x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
topo_ids->smt_id;
}
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
* based on (contiguous) CPU index
*/
static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
@@ -154,7 +153,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo
*topo_info,
topo_ids->smt_id = cpu_index % nr_threads;
}
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
* based on APIC ID
*/
static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
@@ -178,7 +178,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
}
-/* Make APIC ID for the CPU 'cpu_index'
+/*
+ * Make APIC ID for the CPU 'cpu_index'
*
* 'cpu_index' is a sequential, contiguous ID for the CPU.
*/
Reviewed-by: Yanan Wang
Thanks,
Yanan
Re: [PATCH RESEND 09/18] i386: Fix comment style in topology.h
On 13/2/23 10:36, Zhao Liu wrote: From: Zhao Liu For function comments in this file, keep the comment style consistent with other places. Signed-off-by: Zhao Liu --- include/hw/i386/topology.h | 33 + 1 file changed, 17 insertions(+), 16 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
