Re: [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

[Alexey Baturo]

Hi Richard,

Thanks for noticing that.
Do you think it would be an ok solution to pass dst as a pointer
into gen_pm_adjust_address, so in case pm is enabled, it'd allocate the
temp and update the dst afterwards?
Thanks

пт, 10 сент. 2021 г. в 00:00, Richard Henderson <
richard.hender...@linaro.org>:

> On 9/9/21 9:00 PM, Alexey Baturo wrote:
> > +++ b/target/riscv/insn_trans/trans_rva.c.inc
> > @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a,
> MemOp mop)
> >   if (a->rl) {
> >   tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> >   }
> > +gen_pm_adjust_address(ctx, src1, src1);
>
> This will not work anymore, since src1 may not be a temporary.  See the
> use of temp_new()
> e.g. in gen_load().  We're currently only conditionally allocating a
> temporary; with this
> extension, we'll always need one.  So it is probably worth cleaning that
> up at this time.
>
>
> r~
>

Re: [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

[Richard Henderson]

On 9/9/21 9:00 PM, Alexey Baturo wrote:

+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp 
mop)
  if (a->rl) {
  tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
  }
+gen_pm_adjust_address(ctx, src1, src1);


This will not work anymore, since src1 may not be a temporary.  See the use of temp_new() 
e.g. in gen_load().  We're currently only conditionally allocating a temporary; with this 
extension, we'll always need one.  So it is probably worth cleaning that up at this time.



r~