Re: [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c

[Richard Henderson]

On 6/4/21 8:52 AM, Alex Bennée wrote:

From: Claudio Fontana 

cpu-sysemu.c:

we need this sysemu code for KVM too, so we move the code to
cpu-sysemu.c so we can reach a builable state.

There will be further split later on in dedicated
exception modules for 32 and 64bit, after we make more
necessary changes to be able to split TARGET_AARCH64-only code.

tcg/sysemu/tcg-cpu.c:

the TCG-specific code we put in tcg/sysemu/, in preparation
for the addition of the tcg-cpu accel-cpu ARM subclass.

Signed-off-by: Claudio Fontana 
Signed-off-by: Alex Bennée 
---
  target/arm/tcg/tcg-cpu.h  |  31 ++
  target/arm/cpu-sysemu.c   | 670 +++
  target/arm/tcg/helper.c   | 734 --
  target/arm/tcg/sysemu/tcg-cpu.c   |  73 +++
  target/arm/tcg/sysemu/meson.build |   1 +
  5 files changed, 775 insertions(+), 734 deletions(-)
  create mode 100644 target/arm/tcg/tcg-cpu.h
  create mode 100644 target/arm/tcg/sysemu/tcg-cpu.c

diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h
new file mode 100644
index 00..0ee8ba073b
--- /dev/null
+++ b/target/arm/tcg/tcg-cpu.h
@@ -0,0 +1,31 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * 
+ */
+#ifndef ARM_TCG_CPU_H
+#define ARM_TCG_CPU_H
+
+#include "cpu.h"


I presume there's something later that requires this include?


+
+#ifndef CONFIG_USER_ONLY
+/* Do semihosting call and set the appropriate return value. */
+void handle_semihosting(CPUState *cs);


... because at present this typedef is already present, via "qemu/typedefs.h" 
via "qemu/osdep.h", which is always included first.


r`





+
+#endif /* !CONFIG_USER_ONLY */
+
+#endif /* ARM_TCG_CPU_H */
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 0d80a0161c..0e872b2e55 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -19,10 +19,14 @@
   */
  
  #include "qemu/osdep.h"

+#include "qemu/log.h"
+#include "qemu/main-loop.h"
  #include "cpu.h"
  #include "internals.h"
  #include "sysemu/hw_accel.h"
  #include "kvm_arm.h"
+#include "sysemu/tcg.h"
+#include "tcg/tcg-cpu.h"
  
  void arm_cpu_set_irq(void *opaque, int irq, int level)

  {
@@ -508,3 +512,669 @@ int fp_exception_el(CPUARMState *env, int cur_el)
  }
  return 0;
  }
+
+static void take_aarch32_exception(CPUARMState *env, int new_mode,
+   uint32_t mask, uint32_t offset,
+   uint32_t newpc)
+{
+int new_el;
+
+/* Change the CPU state so as to actually take the exception. */
+switch_mode(env, new_mode);
+
+/*
+ * For exceptions taken to AArch32 we must clear the SS bit in both
+ * PSTATE and in the old-state value we save to SPSR_, so zero it 
now.
+ */
+env->pstate &= ~PSTATE_SS;
+env->spsr = cpsr_read(env);
+/* Clear IT bits.  */
+env->condexec_bits = 0;
+/* Switch to the new mode, and to the correct instruction set.  */
+env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
+
+/* This must be after mode switching. */
+new_el = arm_current_el(env);
+
+/* Set new mode endianness */
+env->uncached_cpsr &= ~CPSR_E;
+if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
+env->uncached_cpsr |= CPSR_E;
+}
+/* J and IL must always be cleared for exception entry */
+env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
+env->daif |= mask;
+
+if (new_mode == ARM_CPU_MODE_HYP) {
+env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
+env->elr_el[2] = env->regs[15];
+} else {
+/* CPSR.PAN is normally preserved preserved unless...  */
+if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
+switch (new_el) {
+case 3:
+if (!arm_is_secure_below_el3(env)) {
+/* ... the target is EL3, from non-secure state.  */
+env->uncached_cpsr &= ~CPSR_PAN;
+break;
+}
+/* ... the target is EL3, from secure state ... */
+/* fall through */
+case 1:
+/* ... the target is EL1 and SCTLR.SPAN is 0.  */
+if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
+env->uncached_cpsr |= CPSR_PAN;
+

Re: [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c

[Richard Henderson]

On 6/4/21 8:52 AM, Alex Bennée wrote:

From: Claudio Fontana

cpu-sysemu.c:

we need this sysemu code for KVM too, so we move the code to
cpu-sysemu.c so we can reach a builable state.

There will be further split later on in dedicated
exception modules for 32 and 64bit, after we make more
necessary changes to be able to split TARGET_AARCH64-only code.

tcg/sysemu/tcg-cpu.c:

the TCG-specific code we put in tcg/sysemu/, in preparation
for the addition of the tcg-cpu accel-cpu ARM subclass.

Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
---
  target/arm/tcg/tcg-cpu.h  |  31 ++
  target/arm/cpu-sysemu.c   | 670 +++
  target/arm/tcg/helper.c   | 734 --
  target/arm/tcg/sysemu/tcg-cpu.c   |  73 +++
  target/arm/tcg/sysemu/meson.build |   1 +
  5 files changed, 775 insertions(+), 734 deletions(-)
  create mode 100644 target/arm/tcg/tcg-cpu.h
  create mode 100644 target/arm/tcg/sysemu/tcg-cpu.c


Reviewed-by: Richard Henderson 

r~