Re: [PATCH v6 02/25] target/riscv: Add a general status enum for extensions
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> The pointer masking is the only extension that directly use status.
> The vector or float extension uses the status in an indirect way.
>
> Replace the pointer masking extension special status fields with
> the general status.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: LIU Zhiwei
> Message-Id: <20230324143031.1093-3-zhiwei_...@linux.alibaba.com>
> [rth: Add a typedef for the enum]
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 8
> target/riscv/cpu_bits.h | 12
> target/riscv/cpu.c | 2 +-
> target/riscv/csr.c | 14 +++---
> 4 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 12fe8d8546..30d9828d59 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -99,6 +99,14 @@ enum {
> TRANSLATE_G_STAGE_FAIL
> };
>
> +/* Extension context status */
> +typedef enum {
> +EXT_STATUS_DISABLED = 0,
> +EXT_STATUS_INITIAL,
> +EXT_STATUS_CLEAN,
> +EXT_STATUS_DIRTY,
> +} RISCVExtStatus;
> +
> #define MMU_USER_IDX 3
>
> #define MAX_RISCV_PMPS (16)
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index fca7ef0cef..b84f62f8d6 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -9,6 +9,9 @@
> (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
> (uint64_t)(mask)))
>
> +/* Extension context status mask */
> +#define EXT_STATUS_MASK 0x3ULL
> +
> /* Floating point round mode */
> #define FSR_RD_SHIFT5
> #define FSR_RD (0x7 << FSR_RD_SHIFT)
> @@ -734,13 +737,6 @@ typedef enum RISCVException {
> #define PM_ENABLE 0x0001ULL
> #define PM_CURRENT 0x0002ULL
> #define PM_INSN 0x0004ULL
> -#define PM_XS_MASK 0x0003ULL
> -
> -/* PointerMasking XS bits values */
> -#define PM_EXT_DISABLE 0xULL
> -#define PM_EXT_INITIAL 0x0001ULL
> -#define PM_EXT_CLEAN0x0002ULL
> -#define PM_EXT_DIRTY0x0003ULL
>
> /* Execution enviornment configuration bits */
> #define MENVCFG_FIOM BIT(0)
> @@ -780,7 +776,7 @@ typedef enum RISCVException {
> #define S_OFFSET 5ULL
> #define M_OFFSET 8ULL
>
> -#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
> +#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
> #define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> #define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> #define U_PM_INSN(PM_INSN<< U_OFFSET)
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..1135106b3e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -764,7 +764,7 @@ static void riscv_cpu_reset_hold(Object *obj)
> i++;
> }
> /* mmte is supposed to have pm.current hardwired to 1 */
> -env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
> +env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
> #endif
> env->xl = riscv_cpu_mxl(env);
> riscv_cpu_update_mask(env);
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..abea7b749e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3513,7 +3513,7 @@ static RISCVException write_mmte(CPURISCVState *env,
> int csrno,
>
> /* hardwiring pm.instruction bit to 0, since it's not supported yet */
> wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
> -env->mmte = wpri_val | PM_EXT_DIRTY;
> +env->mmte = wpri_val | EXT_STATUS_DIRTY;
> riscv_cpu_update_mask(env);
>
> /* Set XS and SD bits, since PM CSRs are dirty */
> @@ -3593,7 +3593,7 @@ static RISCVException write_mpmmask(CPURISCVState *env,
> int csrno,
> if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> env->cur_pmmask = val;
> }
> -env->mmte |= PM_EXT_DIRTY;
> +env->mmte |= EXT_STATUS_DIRTY;
>
> /* Set XS and SD bits, since PM CSRs are dirty */
> mstatus = env->mstatus | MSTATUS_XS;
> @@ -3621,7 +3621,7 @@ static RISCVException write_spmmask(CPURISCVState *env,
> int csrno,
> if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> env->cur_pmmask = val;
> }
> -env->mmte |= PM_EXT_DIRTY;
> +env->mmte |= EXT_STATUS_DIRTY;
>
> /* Set XS and SD bits, since PM CSRs are dirty */
> mstatus = env->mstatus | MSTATUS_XS;
> @@ -3649,7 +3649,7 @@ static RISCVException write_upmmask(CPURISCVState *env,
> int csrno,
> if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> env->cur_pmmask = val;
> }
> -env->mmte |= PM_EXT_DIRTY;
> +env->mmte |= EXT_STATUS_DIRTY;
>
> /* Set XS and SD bits, since PM CSRs are dirty */
> mstatus = env->mstatus | MSTATUS_XS;
> @@ -3673,7 +3673,7 @@ static RISCVException write_mpmbase(CPURISCVState *env,
> int csrno,
> if ((env->priv == PRV_M) && (env->mmte &
Re: [PATCH v6 02/25] target/riscv: Add a general status enum for extensions
On 2023/3/25 18:54, Richard Henderson wrote:
From: LIU Zhiwei
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson
Signed-off-by: LIU Zhiwei
Message-Id: <20230324143031.1093-3-zhiwei_...@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson
---
Reviewed-by: Weiwei Li
Weiwei Li
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 12
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 14 +++---
4 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 12fe8d8546..30d9828d59 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -99,6 +99,14 @@ enum {
TRANSLATE_G_STAGE_FAIL
};
+/* Extension context status */
+typedef enum {
+EXT_STATUS_DISABLED = 0,
+EXT_STATUS_INITIAL,
+EXT_STATUS_CLEAN,
+EXT_STATUS_DIRTY,
+} RISCVExtStatus;
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fca7ef0cef..b84f62f8d6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -9,6 +9,9 @@
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
(uint64_t)(mask)))
+/* Extension context status mask */
+#define EXT_STATUS_MASK 0x3ULL
+
/* Floating point round mode */
#define FSR_RD_SHIFT5
#define FSR_RD (0x7 << FSR_RD_SHIFT)
@@ -734,13 +737,6 @@ typedef enum RISCVException {
#define PM_ENABLE 0x0001ULL
#define PM_CURRENT 0x0002ULL
#define PM_INSN 0x0004ULL
-#define PM_XS_MASK 0x0003ULL
-
-/* PointerMasking XS bits values */
-#define PM_EXT_DISABLE 0xULL
-#define PM_EXT_INITIAL 0x0001ULL
-#define PM_EXT_CLEAN0x0002ULL
-#define PM_EXT_DIRTY0x0003ULL
/* Execution enviornment configuration bits */
#define MENVCFG_FIOM BIT(0)
@@ -780,7 +776,7 @@ typedef enum RISCVException {
#define S_OFFSET 5ULL
#define M_OFFSET 8ULL
-#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
#define U_PM_INSN(PM_INSN<< U_OFFSET)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..1135106b3e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -764,7 +764,7 @@ static void riscv_cpu_reset_hold(Object *obj)
i++;
}
/* mmte is supposed to have pm.current hardwired to 1 */
-env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
+env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
#endif
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..abea7b749e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3513,7 +3513,7 @@ static RISCVException write_mmte(CPURISCVState *env, int
csrno,
/* hardwiring pm.instruction bit to 0, since it's not supported yet */
wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
-env->mmte = wpri_val | PM_EXT_DIRTY;
+env->mmte = wpri_val | EXT_STATUS_DIRTY;
riscv_cpu_update_mask(env);
/* Set XS and SD bits, since PM CSRs are dirty */
@@ -3593,7 +3593,7 @@ static RISCVException write_mpmmask(CPURISCVState *env,
int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
-env->mmte |= PM_EXT_DIRTY;
+env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3621,7 +3621,7 @@ static RISCVException write_spmmask(CPURISCVState *env,
int csrno,
if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
}
-env->mmte |= PM_EXT_DIRTY;
+env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3649,7 +3649,7 @@ static RISCVException write_upmmask(CPURISCVState *env,
int csrno,
if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
}
-env->mmte |= PM_EXT_DIRTY;
+env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus = env->mstatus | MSTATUS_XS;
@@ -3673,7 +3673,7 @@ static RISCVException write_mpmbase(CPURISCVState *env,
int csrno,
if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
-env->mmte |= PM_EXT_DIRTY;
+env->mmte |= EXT_STATUS_DIRTY;
/* Set XS and SD bits, since PM CSRs are dirty */
mstatus =
