On 29 June 2018 at 14:29, Luc Michel <luc.mic...@greensocs.com> wrote: > Implement the maintenance interrupt generation that is part of the GICv2 > virtualization extensions. > > Signed-off-by: Luc Michel <luc.mic...@greensocs.com> > +static void gic_compute_misr(GICState *s, int cpu) > +{ > + int val;
This could be a bool. > + int vcpu = cpu + GIC_NCPU; > + > + int num_eoi, num_valid, num_pending; > + > + gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); > + > + /* EOI */ > + val = (num_eoi != 0); > + s->h_misr[cpu] = FIELD_DP32(0, GICH_MISR, EOI, val); Where you're starting with 0 and just ORing in bits, it's probably clearer to use value = 0; if (something) { value |= R_GICH_MISR_EOI_MASK; } if (something) { value |= R_GICH_MISR_U_MASK; } etc... s->h_misr[cpu] = value; All the logic here is fine though so Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM