On Tue, 20 Nov 2018 at 21:26, Aaron Lindsay
wrote:
>
> This commit doesn't add any supported events, but provides the framework
> for adding them. We store the pm_event structs in a simple array, and
> provide the mapping from the event numbers to array indexes in the
> supported_event_map array. Because the value of PMCEID[01] depends upon
> which events are supported at runtime, generate it dynamically.
>
> Signed-off-by: Aaron Lindsay
> ---
> target/arm/cpu.c| 19 +--
> target/arm/cpu.h| 10
> target/arm/cpu64.c | 4
> target/arm/helper.c | 57 +
> 4 files changed, 79 insertions(+), 11 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index f7bad04f60..208a08e867 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1019,10 +1019,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
>
> if (!cpu->has_pmu) {
> unset_feature(env, ARM_FEATURE_PMU);
> +}
> +if (arm_feature(env, ARM_FEATURE_PMU)) {
> +cpu->pmceid0 = get_pmceid(>env, 0);
> +cpu->pmceid1 = get_pmceid(>env, 1);
> +
> +if (!kvm_enabled()) {
> +arm_register_pre_el_change_hook(cpu, _pre_el_change, 0);
> +arm_register_el_change_hook(cpu, _post_el_change, 0);
> +}
> +} else {
> cpu->id_aa64dfr0 &= ~0xf00;
> -} else if (!kvm_enabled()) {
> -arm_register_pre_el_change_hook(cpu, _pre_el_change, 0);
> -arm_register_el_change_hook(cpu, _post_el_change, 0);
> +cpu->pmceid0 = 0;
> +cpu->pmceid1 = 0;
> }
>
> if (!arm_feature(env, ARM_FEATURE_EL2)) {
> @@ -1665,8 +1674,6 @@ static void cortex_a7_initfn(Object *obj)
> cpu->id_pfr0 = 0x1131;
> cpu->id_pfr1 = 0x00011011;
> cpu->id_dfr0 = 0x02010555;
> -cpu->pmceid0 = 0x;
> -cpu->pmceid1 = 0x;
> cpu->id_afr0 = 0x;
> cpu->id_mmfr0 = 0x10101105;
> cpu->id_mmfr1 = 0x4000;
> @@ -1712,8 +1719,6 @@ static void cortex_a15_initfn(Object *obj)
> cpu->id_pfr0 = 0x1131;
> cpu->id_pfr1 = 0x00011011;
> cpu->id_dfr0 = 0x02010555;
> -cpu->pmceid0 = 0x000;
> -cpu->pmceid1 = 0x;
> cpu->id_afr0 = 0x;
> cpu->id_mmfr0 = 0x10201105;
> cpu->id_mmfr1 = 0x2000;
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 50de58e4a2..32c3397948 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -993,6 +993,16 @@ void pmu_op_finish(CPUARMState *env);
> void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
> void pmu_post_el_change(ARMCPU *cpu, void *ignored);
>
> +/*
> + * get_pmceid
> + * @env: CPUARMState
> + *
> + * Return the PMCEID[01]_EL0 register values corresponding to the counters
> + * which are supported given the current configuration (`which` is 0 or 1 to
> + * indicate which PMCEID should be returned)
> + */
Nit: you should have a line here below the one for "@env"
for the "@which" parameter, and the reference to it in
the text should just be "@which", not "`which`" (or just
put that description in the line saying what @which is
rather than having it in a parenthetical).
> +uint64_t get_pmceid(CPUARMState *env, unsigned which);
> +
> /* SCTLR bit meanings. Several bits have been reused in newer
> * versions of the architecture; in that case we define constants
> * for both old and new bit meanings. Code which tests against those
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 873f059bf2..a1aad772fa 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -138,8 +138,6 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->isar.id_isar6 = 0;
> cpu->isar.id_aa64pfr0 = 0x;
> cpu->id_aa64dfr0 = 0x10305106;
> -cpu->pmceid0 = 0x;
> -cpu->pmceid1 = 0x;
> cpu->isar.id_aa64isar0 = 0x00011120;
> cpu->id_aa64mmfr0 = 0x1124;
> cpu->dbgdidr = 0x3516d000;
> @@ -246,8 +244,6 @@ static void aarch64_a72_initfn(Object *obj)
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_aa64pfr0 = 0x;
> cpu->id_aa64dfr0 = 0x10305106;
> -cpu->pmceid0 = 0x;
> -cpu->pmceid1 = 0x;
> cpu->isar.id_aa64isar0 = 0x00011120;
> cpu->id_aa64mmfr0 = 0x1124;
> cpu->dbgdidr = 0x3516d000;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 75f054fe79..68e9743606 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1009,6 +1009,63 @@ static inline uint64_t pmu_counter_mask(CPUARMState
> *env)
>return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
> }
>
> +typedef struct pm_event {
> +uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
> +/* If the event is supported on this CPU (used to generate PMCEID[01]) */
> +bool (*supported)(CPUARMState *);
> +/*
> + * Retrieve the current count of the underlying event. The programmed
> + * counters hold a
