Re: [Qemu-devel] [RFC 2/3] intc/arm_gic: Support PPI injection for more than 256 vpus
Hi,
On 8/29/19 9:58 AM, Auger Eric wrote:
> Hi Zenghui,
>
> On 8/29/19 4:53 AM, Zenghui Yu wrote:
>> Hi Eric,
>>
>> On 2019/8/28 0:05, Eric Auger wrote:
>>> Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
>>> allow injection of PPIs along with vcpu ids larger than 255. Let's
>>> encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
>>> ABI when needed.
>>>
>>> Without that patch qemu exits with "kvm_set_irq: Invalid argument"
>>> message.
>>>
>>> Signed-off-by: Eric Auger
>>> Reported-by: Zenghui Yu
>>> ---
>>> hw/intc/arm_gic_kvm.c | 10 +++---
>>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
>>> index b56fda144f..889293e97f 100644
>>> --- a/hw/intc/arm_gic_kvm.c
>>> +++ b/hw/intc/arm_gic_kvm.c
>>> @@ -56,6 +56,7 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq,
>>> int level)
>>> * CPU number and interrupt number.
>>> */
>>> int kvm_irq, irqtype, cpu;
>>> + int cpu_idx1 = 0, cpu_idx2 = 0;
>>> if (irq < (num_irq - GIC_INTERNAL)) {
>>> /* External interrupt. The kernel numbers these like the GIC
>>> @@ -63,17 +64,20 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int
>>> irq, int level)
>>> * internal ones.
>>> */
>>> irqtype = KVM_ARM_IRQ_TYPE_SPI;
>>> - cpu = 0;
>>> irq += GIC_INTERNAL;
>>> } else {
>>> /* Internal interrupt: decode into (cpu, interrupt id) */
>>> irqtype = KVM_ARM_IRQ_TYPE_PPI;
>>> irq -= (num_irq - GIC_INTERNAL);
>>> cpu = irq / GIC_INTERNAL;
>>> + cpu_idx2 = cpu / 256;
>>> + cpu_idx1 = cpu % 256;
>>> irq %= GIC_INTERNAL;
>>> }
>>> - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
>>> - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
>>> + kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) |
>>> + (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) |
>>> + ((cpu_idx2 & KVM_ARM_IRQ_VCPU2_MASK) <<
>>> KVM_ARM_IRQ_VCPU2_SHIFT) |
>>> + irq;
>>> kvm_set_irq(kvm_state, kvm_irq, !!level);
>>> }
>>>
>>
>> For confirmation, should we also adjust the vcpu_index in
>> arm_cpu_kvm_set_irq(), just like above?
>
> I am not familiar with this path. in arm_cpu_initfn(), there is a
> comment saying "VIRQ and VFIQ are unused with KVM but we add them to
> maintain the same interface as non-KVM CPUs." So I don't know when that
> code gets executed.
>
> But maybe it would be more cautious to implement your suggestion here as
> well.
>
> Maybe Peter can provide more info here?
If this is supposed to get used along with kernel_irqchip=off, it seems
this latter is not supported with GICv3 anyway. So max number of vcpus
with GICv2 is 8.
Thanks
Eric
>
> Thanks
>
> Eric
>
>
>>
>>
>> Thanks,
>> zenghui
>>
>>
>
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On Thu, Aug 29, 2019 at 05:26:49PM +0800, He Zhe wrote: > > > On 8/29/19 5:15 PM, Daniel P. Berrangé wrote: > > On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote: > >> From: He Zhe > >> > >> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config > >> handling for libgcrypt. > > Where are you seeing pkg-config files for libgcrypt ? > > > > The upstream project has (frustratingly) been hostile to any proposal to > > add pkg-config support saying people should stick with their custom > > libgcrypt-config tool > > > >https://dev.gnupg.org/T2037 > > > > Even if this is something added by some distro downstream, what is the > > benefit in using it, compared with libgcrypt-confg which should already > > work & is portable. > > IMHO, it could be easy for people to use pkg-config as a center to control > configurations for many different packages. > > This is just an addition for qemu to be able to work in both cases. It does > not > remove libgcrypt-confg and can fall back to libgcrypt-confg when pkg-config > does > not work. The addition has a maint cost associated with it, since we have have two different ways to achieve the same thing. When only one of the approaches is provided by upstream, the other is not going to be widely tested. In maintaining packages in Fedora which rely on pkg-config files that are not upstream, we've seen frequent breakage when. So my preference is stick with what we have that is supported by upstream gcrypt. Regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [Qemu-devel] [patch-for-4.2 PATCH v11 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests
On Wed, 14 Aug 2019 11:40:50 +0530 Aravinda Prasad wrote: > This patch set adds support for FWNMI in PowerKVM guests. > > System errors such as SLB multihit and memory errors > that cannot be corrected by hardware is passed on to > the kernel for handling by raising machine check > exception (an NMI). Upon such machine check exceptions, > if the address in error belongs to guest then KVM > invokes guests' 0x200 interrupt vector if the guest > is not FWNMI capable. For FWNMI capable guest > KVM passes the control to QEMU by exiting the guest. > > This patch series adds functionality to QEMU to pass > on such machine check exceptions to the FWNMI capable > guest kernel by building an error log and invoking > the guest registered machine check handling routine. > > The KVM changes are now part of the upstream kernel > (commit e20bbd3d). This series contain QEMU changes. > > Change Log v11: > - Moved FWNMI SPAPR cap defaults to 4.2 class option > - Fixed issues with handling fwnmi KVM capability > Hi Aravinda, I'm afraid this series needs rebasing. It doesn't apply cleanly on current ppc-for-4.2 (SHA1 b1e8156743). Cheers, -- Greg > Change Log v10: > - Reshuffled the patch sequence + minor fixes > > Change Log v9: > - Fixed kvm cap and spapr cap issues > > Change Log v8: > - Added functionality to check FWNMI capability during > VM migration > --- > > Aravinda Prasad (6): > Wrapper function to wait on condition for the main loop mutex > ppc: spapr: Introduce FWNMI capability > target/ppc: Handle NMI guest exit > target/ppc: Build rtas error log upon an MCE > ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls > migration: Include migration support for machine check handling > > > cpus.c |5 + > hw/ppc/spapr.c | 78 + > hw/ppc/spapr_caps.c | 29 + > hw/ppc/spapr_events.c| 268 > ++ > hw/ppc/spapr_rtas.c | 78 + > include/hw/ppc/spapr.h | 25 > include/qemu/main-loop.h |8 + > target/ppc/cpu.h |1 > target/ppc/kvm.c | 38 +++ > target/ppc/kvm_ppc.h | 13 ++ > target/ppc/trace-events |1 > 11 files changed, 542 insertions(+), 2 deletions(-) > > -- > Signature
Re: [Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
On Thu, Aug 29, 2019 at 05:02:27PM +0800, Chao Gao wrote: > Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's > perspective, assigned devices cannot be reset. But some devices rely on PCI > reset to recover from hardware hangs. When being assigned to a VM, those > devices cannot be reset and won't work any longer if a hardware hang occurs. > We have to reboot VM to trigger PCI reset on host to recover the device. > > This patch exposes FLR capability to VMs if the assigned device can be reset > on > host. When VM initiates an FLR to a device, qemu cleans up the device state, > (including disabling of intx and/or MSI and unmapping BARs from guest, > deleting > emulated registers), then initiate PCI reset through 'reset' knob under the > device's sysfs, finally initialize the device again. I think you likely need to deassign the device from the VM, perform the reset, and then assign the device again, so that there's no Xen internal state carried over prior to the reset? Thanks, Roger.
[Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4
From: Aleksandar Markovic
Clean up handling of CP0 register 4.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-6-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 36
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d5b7103..496872e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -305,7 +305,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID4
#define CP0_REG00__MMID5
/* CP0 Register 05 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 059f53e..9df59f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6975,16 +6975,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
-case 1:
-/* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -7710,15 +7711,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
-case 1:
-//gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_mtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -8455,15 +8457,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
-case 1:
-//gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -9168,15 +9171,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
-case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_dmtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
--
2.7.4
[Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12
From: Aleksandar Markovic
Clean up handling of CP0 register 12.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-14-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 32
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3797bdc..061effb 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -350,6 +350,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__SRSMAP 3
+#define CP0_REG12__VIEW_IPL4
+#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET7
/* CP0 Register 13 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b5d5994..fb9c719 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7177,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -7893,7 +7893,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -7901,21 +7901,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -8652,21 +8652,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -9356,7 +9356,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -9364,21 +9364,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp =
[Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18
From: Aleksandar Markovic
Clean up handling of CP0 register 18.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 20 +---
target/mips/translate.c | 64 -
2 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6405ad..d6ea111 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* --- --- --- ---
*
- * 0 ConfigLLAddrWatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 ConfigLLAddrWatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO11
#define CP0_REG18__WATCHLO22
#define CP0_REG18__WATCHLO33
+#define CP0_REG18__WATCHLO44
+#define CP0_REG18__WATCHLO55
+#define CP0_REG18__WATCHLO66
+#define CP0_REG18__WATCHLO77
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI00
#define CP0_REG19__WATCHHI11
diff --git a/target/mips/translate.c b/target/mips/translate.c
index edeaaad..6a11e8d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-
[Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26
From: Aleksandar Markovic
Clean up handling of CP0 register 26.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-26-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 168a6d7..40b7cc6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -423,7 +423,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG25__PERFCTL36
#define CP0_REG25__PERFCNT37
/* CP0 Register 26 */
-#define CP0_REG00__ERRCTL 0
+#define CP0_REG26__ERRCTL 0
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 84aabf6..a8ea952 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7456,7 +7456,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -8213,7 +8213,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -8944,7 +8944,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -9683,7 +9683,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
--
2.7.4
[Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23
From: Aleksandar Markovic
Clean up handling of CP0 register 23.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-23-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 6 +++
target/mips/translate.c | 126 +++-
2 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b4866a5..168a6d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -405,6 +405,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 22 */
/* CP0 Register 23 */
#define CP0_REG23__DEBUG 0
+#define CP0_REG23__TRACECONTROL1
+#define CP0_REG23__TRACECONTROL2 2
+#define CP0_REG23__USERTRACEDATA1 3
+#define CP0_REG23__TRACEIBPC 4
+#define CP0_REG23__TRACEDBPC 5
+#define CP0_REG23__DEBUG2 6
/* CP0 Register 24 */
#define CP0_REG24__DEPC0
/* CP0 Register 25 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 55b0005..610631f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7371,25 +7371,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
-case 0:
+case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
-case 1:
-//gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL:
+/* PDtrace support */
+/* gen_helper_mfc0_tracecontrol(arg); */
register_name = "TraceControl";
goto cp0_unimplemented;
-case 2:
-//gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL2:
+/* PDtrace support */
+/* gen_helper_mfc0_tracecontrol2(arg); */
register_name = "TraceControl2";
goto cp0_unimplemented;
-case 3:
-//gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
-register_name = "UserTraceData";
+case CP0_REG23__USERTRACEDATA1:
+/* PDtrace support */
+/* gen_helper_mfc0_usertracedata1(arg);*/
+register_name = "UserTraceData1";
goto cp0_unimplemented;
-case 4:
-//gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
-register_name = "TraceBPC";
+case CP0_REG23__TRACEIBPC:
+/* PDtrace support */
+/* gen_helper_mfc0_traceibpc(arg); */
+register_name = "TraceIBPC";
+goto cp0_unimplemented;
+case CP0_REG23__TRACEDBPC:
+/* PDtrace support */
+/* gen_helper_mfc0_tracedbpc(arg); */
+register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8105,38 +8114,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
-case 0:
+case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
-case 1:
-//gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL:
+/* PDtrace support */
+/* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 2:
-//gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support
*/
+case CP0_REG23__TRACECONTROL2:
+/* PDtrace support */
+/* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 3:
+case CP0_REG23__USERTRACEDATA1:
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
-//gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support
*/
+/* PDtrace support */
+/* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 4:
-//
[Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11
From: Aleksandar Markovic
Clean up handling of CP0 register 11.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-13-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 50863cf..b5d5994 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7166,7 +7166,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -7882,7 +7882,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -8641,7 +8641,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -9343,7 +9343,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
--
2.7.4
Re: [Qemu-devel] [PATCH v9 03/13] block/backup: introduce BlockCopyState
Thanks for reviewing!
28.08.2019 18:59, Max Reitz wrote:
> On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote:
>> Split copying code part from backup to "block-copy", including separate
>> state structure and function renaming. This is needed to share it with
>> backup-top filter driver in further commits.
>>
>> Notes:
>>
>> 1. As BlockCopyState keeps own BlockBackend objects, remaining
>
> I suppose these should be BdrvChild objects at some point, but doing it
> now would just mean effectively duplicating code from block-backend.c.
> (“now” = before we have a backup-top filter to attach the children to.)
How much is it bad to not do it, but leave them to be block-backends in
block-copy
state? They'll connected anyway through the job, as they all are in job.nodes.
We have block-backends in jobs currently, is it bad?
>
>> job->common.blk users only use it to get bs by blk_bs() call, so clear
>> job->commen.blk permissions set in block_job_create.
>>
>> 2. Rename s/initializing_bitmap/skip_unallocated/ to sound a bit better
>> as interface to BlockCopyState
>>
>> 3. Split is not very clean: there left some duplicated fields, backup
>
> Are there any but cluster_size and len (and source, in a sense)?
Seems no more
>
>> code uses some BlockCopyState fields directly, let's postpone it for
>> further improvements and keep this comment simpler for review.
>>
>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>> ---
>> block/backup.c | 324 +++--
>> block/trace-events | 12 +-
>> 2 files changed, 200 insertions(+), 136 deletions(-)
>>
>> diff --git a/block/backup.c b/block/backup.c
>> index 13a1d80157..f52ac622e0 100644
>> --- a/block/backup.c
>> +++ b/block/backup.c
>> @@ -35,12 +35,35 @@ typedef struct CowRequest {
>> CoQueue wait_queue; /* coroutines blocked on this request */
>> } CowRequest;
>>
>> +/*
>> + * ProgressCallbackFunc
>> + *
>> + * Called when some progress is done in context of BlockCopyState:
>> + * 1. When some bytes copied, called with @bytes > 0.
>> + * 2. When some bytes resetted from copy_bitmap, called with @bytes = 0
>> (user
>
> *reset
>
>> + * may recalculate remaining bytes from copy_bitmap dirty count.
>> + */
>> +typedef void (*ProgressCallbackFunc)(int64_t bytes, void *opaque);
>
> Maybe there should be two callbacks instead, one for “We’ve actively
> made progress” (bytes > 0) and one for “The expected length has changed”
> (bytes == 0)?
I thought, that there are already too many parameters in block_copy_state_new().
But I agree with you, as actually it led to two callbacks in a one with just
if-else to distinguish them. Will do.
>
>> +typedef struct BlockCopyState {
>> +BlockBackend *source;
>> +BlockBackend *target;
>> +BdrvDirtyBitmap *copy_bitmap;
>> +int64_t cluster_size;
>> +bool use_copy_range;
>> +int64_t copy_range_size;
>> +uint64_t len;
>> +
>> +BdrvRequestFlags write_flags;
>> +bool skip_unallocated;
>
> The rename seems reasonable, although I think this should get a comment,
> because it doesn’t mean just to skip unallocated clusters; it also means
> to clear unallocated clusters from the bitmap.
>
>> +
>> +ProgressCallbackFunc progress_callback;
>> +void *progress_opaque;
>> +} BlockCopyState;
>> +
>> typedef struct BackupBlockJob {
>> BlockJob common;
>> -BlockBackend *target;
>>
>> BdrvDirtyBitmap *sync_bitmap;
>> -BdrvDirtyBitmap *copy_bitmap;
>>
>> MirrorSyncMode sync_mode;
>> BitmapSyncMode bitmap_mode;
>
> [...]
>
>> @@ -99,9 +118,83 @@ static void cow_request_end(CowRequest *req)
>> qemu_co_queue_restart_all(>wait_queue);
>> }
>>
>> +static void block_copy_state_free(BlockCopyState *s)
>> +{
>> +if (!s) {
>> +return;
>> +}
>> +
>> +bdrv_release_dirty_bitmap(blk_bs(s->source), s->copy_bitmap);
>> +blk_unref(s->source);
>> +s->source = NULL;
>> +blk_unref(s->target);
>> +s->target = NULL;
>
> I’m not quite sure why you NULL these pointers when you free the whole
> object next anyway.
it is for backup_drain, I'm afraid of some yield during blk_unref (and seems
it's unsafe
anyway, as I zero reference after calling blk_unref). Anyway,
backup_drain will be dropped in "[PATCH v3] job: drop job_drain", I'll drop
"= NULL" here now and workaround backup_drain in backup_clean with corresponding
comment.
>
>> +g_free(s);
>> +}
>> +
>> +static BlockCopyState *block_copy_state_new(
>> +BlockDriverState *source, BlockDriverState *target,
>> +int64_t cluster_size, BdrvRequestFlags write_flags,
>> +ProgressCallbackFunc progress_callback, void *progress_opaque,
>> +Error **errp)
>> +{
>> +BlockCopyState *s;
>> +int ret;
>> +uint64_t no_resize = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE |
>> + BLK_PERM_WRITE_UNCHANGED | BLK_PERM_GRAPH_MOD;
>> +BdrvDirtyBitmap *copy_bitmap =
>> +
Re: [Qemu-devel] [PATCH v9 04/13] block/backup: adjust block-copy functions style
28.08.2019 19:06, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> Fix comment style and reflow arguments in same manner like >> block_copy_state_new. > > I like the current function header style better. > OK, not critical at all for me, let's keep current. I'll instead fix all comments style here. -- Best regards, Vladimir
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
On Thu, Aug 29, 2019 at 10:46:42AM +0200, Auger Eric wrote: > If I understand correctly PT mode is a bypass mode. With the ARM SMMUv3 > the IOMMU MR translate() function gets called but implements a direct > mapping. I understand that on your side, you destroy the IOMMU MR, right? > > At the moment since SMMUv3/VFIO integration is not ready I plan to > forbid any usage of VFIO along with SMMUv3, whatever the enable state. > > When HW nested paging gets ready, the stage1 bypass state will be > propagated to the HW config structure. > > Hope I answer your question. Yes, nested page tables will be fine. :) Thanks, -- Peter Xu
[Qemu-devel] [PATCH v5 1/2] memory: Add IOMMU_ATTR_NEED_HW_NESTED_PAGING IOMMU memory region attribute
We introduce a new IOMMU Memory Region attribute,
IOMMU_ATTR_NEED_HW_NESTED_PAGING that tells whether the
virtual IOMMU relies on physical IOMMU HW nested paging
capability when protecting host assigned devices.
Current Intel virtual IOMMU device supports "Caching
Mode" and does not require 2 stages at physical level to be
integrated with VFIO. However SMMUv3 does not implement such
"caching mode" and requires HW nested paging.
As such SMMUv3 is the first IOMMU device to advertise this
attribute.
This new attribute will allow the VFIO code to specialize
its handling.
Signed-off-by: Eric Auger
---
v4 -> v5:
- patches 1, 4, 5 were upstreamed separately
- s/IOMMU_ATTR_HW_NESTED_PAGING/IOMMU_ATTR_NEED_HW_NESTED_PAGING
v3 -> v4:
- s/IOMMU_ATTR_VFIO_NESTED/IOMMU_ATTR_HW_NESTED_PAGING
- add comments related to the existing attributes
- fix space after the cast
---
hw/arm/smmuv3.c | 12
include/exec/memory.h | 8 +++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 2eaf07fb5f..a932bf7136 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1490,6 +1490,17 @@ static void smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu,
}
}
+static int smmuv3_get_attr(IOMMUMemoryRegion *iommu,
+ enum IOMMUMemoryRegionAttr attr,
+ void *data)
+{
+if (attr == IOMMU_ATTR_NEED_HW_NESTED_PAGING) {
+*(bool *)data = true;
+return 0;
+}
+return -EINVAL;
+}
+
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
{
@@ -1497,6 +1508,7 @@ static void
smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
imrc->translate = smmuv3_translate;
imrc->notify_flag_changed = smmuv3_notify_flag_changed;
+imrc->get_attr = smmuv3_get_attr;
}
static const TypeInfo smmuv3_type_info = {
diff --git a/include/exec/memory.h b/include/exec/memory.h
index fddc2ff48a..61493633fa 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -212,7 +212,13 @@ typedef struct MemoryRegionClass {
enum IOMMUMemoryRegionAttr {
-IOMMU_ATTR_SPAPR_TCE_FD
+/* Retrieve an integer corresponding to the TCE file descriptor */
+IOMMU_ATTR_SPAPR_TCE_FD,
+/*
+ * Retrieve a boolean that indicates whether the virtual IOMMU relies
+ * on physical IOMMU HW nested paging to protect host assigned devices
+ */
+IOMMU_ATTR_NEED_HW_NESTED_PAGING,
};
/**
--
2.20.1
[Qemu-devel] [PATCH v5 0/2] VFIO/SMMUv3: Fail on VFIO/HW nested paging detection
As of today when a guest is assigned with a host PCI device and an SMMUv3, VFIO calls memory_region_iommu_replay() default implementation. This translates the whole address range and completely stalls the execution. As VFIO/SMMUv3 integration is not supported yet (it requires SMMUv3 HW nested paging), let's recognize this situation and fail. Best Regards Eric This series can be found at: https://github.com/eauger/qemu/tree/v4.1.0_smmu_vfio_fail_v5 History: v4 -> v5: - v4 patches: 1, 4, 5 were upstreamed separately - IOMMU_ATTR_HW_NESTED_PAGING renamed into IOMMU_ATTR_NEED_HW_NESTED_PAGING v3 -> v4: - see individual patches v2 -> v3: - squash IOMMU_ATTR_VFIO_NESTED introduction and SMMUv3 usage - assert when recognizing VFIO/NESTED case - collect R-bs v1 -> v2: - Added "memory: Remove unused memory_region_iommu_replay_all()" & "hw/arm/smmuv3: Log a guest error when decoding an invalid STE" - do not attempt to implement replay Cb but rather remove the call in case it is not needed - explain why we do not remove other log messages on config decoding Eric Auger (2): memory: Add IOMMU_ATTR_NEED_HW_NESTED_PAGING IOMMU memory region attribute hw/vfio/common: Fail on VFIO/HW nested paging detection hw/arm/smmuv3.c | 12 hw/vfio/common.c | 10 ++ include/exec/memory.h | 8 +++- 3 files changed, 29 insertions(+), 1 deletion(-) -- 2.20.1
Re: [Qemu-devel] [PATCH v3 0/4] Introduce the microvm machine type
Hi Sergio, The idea is interesting and I tried to launch a guest by your guide but seems failed to me. I tried both legacy and normal modes, but the vncviewer connected and told me that: The vm has no graphic display device. All the screen in vnc is just black. kernel config: CONFIG_KVM_MMIO=y CONFIG_VIRTIO_MMIO=y I don't know if any specified kernel version/patch/config is needed or anything I missed. Could you kindly give some tips? Thanks very much. Jing A QEMU instance with the microvm machine type can be invoked this way: - Normal mode: qemu-system-x86_64 -M microvm -m 512m -smp 2 \ -kernel vmlinux -append "console=hvc0 root=/dev/vda" \ -nodefaults -no-user-config \ -chardev pty,id=virtiocon0,server \ -device virtio-serial-device \ -device virtconsole,chardev=virtiocon0 \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 - Legacy mode: qemu-system-x86_64 -M microvm,legacy -m 512m -smp 2 \ -kernel vmlinux -append "console=ttyS0 root=/dev/vda" \ -nodefaults -no-user-config \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 \ -serial stdio
[Qemu-devel] [PATCH v5 2/2] hw/vfio/common: Fail on VFIO/HW nested paging detection
As of today, VFIO only works along with vIOMMU supporting
caching mode. The SMMUv3 does not support this mode and
requires HW nested paging to work properly with VFIO.
So any attempt to run a VFIO device protected by such IOMMU
would prevent the assigned device from working and at the
moment the guest does not even boot as the default
memory_region_iommu_replay() implementation attempts to
translate the whole address space and completely stalls
the guest.
So let's fail on that case.
Signed-off-by: Eric Auger
---
v3 -> v4:
- use IOMMU_ATTR_HW_NESTED_PAGING
- do not abort anymore but jump to fail
---
hw/vfio/common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 3e03c495d8..e8c009d019 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -606,9 +606,19 @@ static void vfio_listener_region_add(MemoryListener
*listener,
if (memory_region_is_iommu(section->mr)) {
VFIOGuestIOMMU *giommu;
IOMMUMemoryRegion *iommu_mr = IOMMU_MEMORY_REGION(section->mr);
+bool nested;
int iommu_idx;
trace_vfio_listener_region_add_iommu(iova, end);
+
+if (!memory_region_iommu_get_attr(iommu_mr,
+ IOMMU_ATTR_NEED_HW_NESTED_PAGING,
+ (void *)) && nested) {
+error_report("VFIO/vIOMMU integration based on HW nested paging "
+ "is not yet supported");
+ret = -EINVAL;
+goto fail;
+}
/*
* FIXME: For VFIO iommu types which have KVM acceleration to
* avoid bouncing all map/unmaps through qemu this way, this
--
2.20.1
[Qemu-devel] [PATCH 1/2] scripts/git.orderfile: Order Python files before unordered ones
Order Python source files before the rest of unordered files. This helps in particular while reviewing iotests. Signed-off-by: Philippe Mathieu-Daudé --- scripts/git.orderfile | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index ac699700b1..0ad5b9b8a8 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -26,4 +26,5 @@ Makefile* # code *.c +*.py -- 2.20.1
[Qemu-devel] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
This series update the git.orderfile to order Python and shell scripts before unordered files. This is particularly useful for changes in tests/qemu-iotests. Regards, Phil. Philippe Mathieu-Daudé (2): scripts/git.orderfile: Order Python files before unordered ones scripts/git.orderfile: Order shell scripts before unordered files scripts/git.orderfile | 5 + 1 file changed, 5 insertions(+) -- 2.20.1
[Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5
From: Aleksandar Markovic
Clean up handling of CP0 register 5.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-7-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 6 +
target/mips/translate.c | 64 -
2 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 496872e..ed1a974 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -313,6 +313,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9df59f1..19f86f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6998,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
-case 0:
+case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
-case 1:
+case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
-case 2:
+case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
-case 3:
+case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
-case 4:
+case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
-case 5:
+case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
-case 6:
+case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
-case 7:
+case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7732,42 +7732,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
-case 0:
+case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
-case 1:
+case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
-case 2:
+case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
-case 3:
+case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
-case 4:
+case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
-case 5:
+case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
-case 6:
+case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
-case 7:
+case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -8478,41 +8478,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
[Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13
From: Aleksandar Markovic
Clean up handling of CP0 register 13.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-15-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 061effb..4fce05a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -357,6 +357,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__GTOFFSET7
/* CP0 Register 13 */
#define CP0_REG13__CAUSE 0
+#define CP0_REG13__VIEW_RIPL 4
+#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
/* CP0 Register 15 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fb9c719..4da08e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7202,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -7928,7 +7928,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -8677,7 +8677,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -9391,7 +9391,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
--
2.7.4
[Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27
From: Aleksandar Markovic
Clean up handling of CP0 register 27.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-27-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a8ea952..c969c25 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7466,10 +7466,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -8224,10 +8221,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -8955,10 +8949,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -9694,10 +9685,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
--
2.7.4
[Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20
From: Aleksandar Markovic
Clean up handling of CP0 register 20.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-22-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d617f4..55b0005 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
@@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
register_name = "XContext";
--
2.7.4
[Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode
From: Aleksandar Markovic
Order of arguments in helper_ret_stl_mmu() invocations was wrong,
apparently caused by a misplaced multiline copy-and-paste.
Fixes: 6decc57 ("target/mips: Fix MSA instructions ST. on big endian
host")
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Rikalo
Message-Id: <1567009239-11273-1-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/op_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f88a3ab..5b8bb20 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
-helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
-helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
-helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
-helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
+helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
#else
-helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
-helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
-helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
-helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
#endif
#else
#if !defined(HOST_WORDS_BIGENDIAN)
--
2.7.4
[Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17
From: Aleksandar Markovic
Clean up handling of CP0 register 17.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-19-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4808640..edeaaad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6669,12 +6669,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6751,7 +6751,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6760,7 +6760,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
*/
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7285,16 +7285,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8020,16 +8020,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8757,16 +8757,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9474,16 +9474,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
Re: [Qemu-devel] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
On 8/29/19 5:05 AM, Philippe Mathieu-Daudé wrote: > This series update the git.orderfile to order Python and shell > scripts before unordered files. > This is particularly useful for changes in tests/qemu-iotests. > > Regards, > > Phil. > > Philippe Mathieu-Daudé (2): > scripts/git.orderfile: Order Python files before unordered ones > scripts/git.orderfile: Order shell scripts before unordered files > Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
[Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
From: He Zhe
libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
handling for libgcrypt.
Signed-off-by: He Zhe
---
configure | 48
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index e44e454..0f362a7 100755
--- a/configure
+++ b/configure
@@ -2875,6 +2875,30 @@ has_libgcrypt() {
return 0
}
+has_libgcrypt_pkgconfig() {
+if ! has $pkg_config ; then
+return 1
+fi
+
+if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
+return 1
+fi
+
+if test -n "$cross_prefix" ; then
+host=$($pkg_config --variable=host libgcrypt)
+if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
+print_error "host($host) does not match
cross_prefix($cross_prefix)"
+return 1
+fi
+fi
+
+if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
+print_error "libgcrypt version is $($pkg_config --modversion
libgcrypt)"
+return 1
+fi
+
+return 0
+}
if test "$nettle" != "no"; then
pass="no"
@@ -2902,7 +2926,14 @@ fi
if test "$gcrypt" != "no"; then
pass="no"
-if has_libgcrypt; then
+if has_libgcrypt_pkgconfig; then
+gcrypt_cflags=$($pkg_config --cflags libgcrypt)
+if test "$static" = "yes" ; then
+gcrypt_libs=$($pkg_config --libs --static libgcrypt)
+else
+gcrypt_libs=$($pkg_config --libs libgcrypt)
+fi
+elif has_libgcrypt; then
gcrypt_cflags=$(libgcrypt-config --cflags)
gcrypt_libs=$(libgcrypt-config --libs)
# Debian has removed -lgpg-error from libgcrypt-config
@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
then
gcrypt_libs="$gcrypt_libs -lgpg-error"
fi
+fi
-# Link test to make sure the given libraries work (e.g for static).
-write_c_skeleton
-if compile_prog "" "$gcrypt_libs" ; then
-LIBS="$gcrypt_libs $LIBS"
-QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
-pass="yes"
-fi
+# Link test to make sure the given libraries work (e.g for static).
+write_c_skeleton
+if compile_prog "" "$gcrypt_libs" ; then
+ LIBS="$gcrypt_libs $LIBS"
+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+ pass="yes"
fi
+
if test "$pass" = "yes"; then
gcrypt="yes"
cat > $TMPC << EOF
--
2.7.4
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
On Thu, Aug 29, 2019 at 10:05:27AM +0200, Auger Eric wrote: > Hi Peter, Hi, Eric, > On 8/29/19 3:18 AM, Peter Xu wrote: > > On Wed, Aug 28, 2019 at 02:59:45PM +0200, Auger Eric wrote: > >> Hi Peter, > > > > Hi, Eric, > > > > [...] > > > >> In > >> [PATCH v4 2/5] memory: Add IOMMU_ATTR_HW_NESTED_PAGING IOMMU memory > >> region attribute (https://patchwork.kernel.org/patch/11109701/) > > > > [1] > > > >> > >> [PATCH v4 3/5] hw/vfio/common: Fail on VFIO/HW nested paging detection > >> (https://patchwork.kernel.org/patch/11109697/) > >> > >> I proposed to introduce a new IOMMU MR attribute to retrieve whether the > >> vIOMMU uses HW nested paging to integrate with VFIO. I wonder whether > >> this kind of solution would fit your need too. > >> > >> Assuming we would rename the attribute (whose name is challenged by > >> Peter anyway) into something like IOMMU_ATTR_PHYS_MAP_MODE > >> taking the possible values: NONE, CM, HW_NESTED_PAGING. SMMUv3 would > >> return HW_NESTED_PAGING, Intel IOMMU would return CM if CM is enabled or > >> NONE in the negative. Then we could implement the check directly in VFIO > >> common.c. That way I don't think you would need the new notifiers and > >> this would satisfy both requirements? > > > > IMHO it'll suffer from the similar issue we have now with > > flag_changed, because at the very beginning of x86 system boots DMAR > > is not yet enabled, the intel-iommu device is using the same mode as > > its passthrough mode so there's no IOMMU memory region at all in the > > DMA address spaces of the devices. > > Ah OK I did not get this initially. We don't have this issue with SMMUv3 > as the IOMMU MR exists from the very beginning and does not depend on > its enablement by the guest. Also it stays there. So the detection can > be made immediatly. True. With that, I'm a bit curious on whether ARM should implement something like PT mode of Intel's. For example, have you tried to run a ARM guest with both a vSMMU and a vfio-pci inside, however keep DMAR disabled? IIUC in that case there will be no mapping at all for the assigned device, then would that work? Or is there any magic for ARM? Regards, -- Peter Xu
Re: [Qemu-devel] [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space configurable
On Thu, 15 Aug 2019 08:42:48 +
Shameerali Kolothum Thodi wrote:
> > -Original Message-
> > From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of Shameer
> > Kolothum
> > Sent: 13 August 2019 22:05
> > To: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > eric.au...@redhat.com; imamm...@redhat.com
> > Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> > ard.biesheu...@linaro.org; Linuxarm ;
> > shannon.zha...@gmail.com; sebastien.bo...@intel.com; ler...@redhat.com
> > Subject: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > configurable
> >
> > This is in preparation for adding support for ARM64 platforms
> > where it doesn't use port mapped IO for ACPI IO space. We are
> > making changes so that MMIO region can be accommodated
> > and board can pass the base address into the aml build function.
>
> Looks like, this now breaks the "make check" on x86_64 and needs
> updating bios-tables-test-allowed-diff.h with DSDT entries. But I am
> not sure what changed now compared to v8(and older ones) that makes
> it to complain now!.
you could see diff of what's changed but running test manually with
V=1 env var if you have 'iasl' installed
V=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 tests/bios-tables-test
> Patchew URL:
> https://patchew.org/QEMU/20190813210539.31164-1-shameerali.kolothum.th...@huawei.com/
>
> ERROR:/tmp/qemu-test/src/tests/bios-tables-test.c:447:test_acpi_asl:
> assertion failed: (all_tables_match)
>
> Thanks,
> Shameer
>
> > Also move few MEMORY_* definitions to header so that other memory
> > hotplug event signalling mechanisms (eg. Generic Event Device on
> > HW-reduced acpi platforms) can use the same from their respective
> > event handler code.
> >
> > Signed-off-by: Shameer Kolothum
> > ---
> > v8 --> v9
> > -base address is an input into build_memory_hotplug_aml()
> > -Removed R-by tags from Igor and Eric for now.
> > ---
> > hw/acpi/memory_hotplug.c | 29 ++---
> > hw/i386/acpi-build.c | 4 +++-
> > hw/i386/pc.c | 3 +++
> > include/hw/acpi/memory_hotplug.h | 9 +++--
> > include/hw/i386/pc.h | 3 +++
> > 5 files changed, 30 insertions(+), 18 deletions(-)
> >
> > diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c
> > index 297812d5f7..1734d4b44f 100644
> > --- a/hw/acpi/memory_hotplug.c
> > +++ b/hw/acpi/memory_hotplug.c
> > @@ -29,12 +29,7 @@
> > #define MEMORY_SLOT_PROXIMITY_METHOD "MPXM"
> > #define MEMORY_SLOT_EJECT_METHOD "MEJ0"
> > #define MEMORY_SLOT_NOTIFY_METHOD"MTFY"
> > -#define MEMORY_SLOT_SCAN_METHOD "MSCN"
> > #define MEMORY_HOTPLUG_DEVICE"MHPD"
> > -#define MEMORY_HOTPLUG_IO_LEN 24
> > -#define MEMORY_DEVICES_CONTAINER "\\_SB.MHPC"
> > -
> > -static uint16_t memhp_io_base;
> >
> > static ACPIOSTInfo *acpi_memory_device_status(int slot, MemStatus *mdev)
> > {
> > @@ -209,7 +204,7 @@ static const MemoryRegionOps
> > acpi_memory_hotplug_ops = {
> > };
> >
> > void acpi_memory_hotplug_init(MemoryRegion *as, Object *owner,
> > - MemHotplugState *state, uint16_t
> > io_base)
> > + MemHotplugState *state, hwaddr
> > io_base)
> > {
> > MachineState *machine = MACHINE(qdev_get_machine());
> >
> > @@ -218,12 +213,10 @@ void acpi_memory_hotplug_init(MemoryRegion *as,
> > Object *owner,
> > return;
> > }
> >
> > -assert(!memhp_io_base);
> > -memhp_io_base = io_base;
> > state->devs = g_malloc0(sizeof(*state->devs) * state->dev_count);
> > memory_region_init_io(>io, owner, _memory_hotplug_ops,
> > state,
> >"acpi-mem-hotplug",
> > MEMORY_HOTPLUG_IO_LEN);
> > -memory_region_add_subregion(as, memhp_io_base, >io);
> > +memory_region_add_subregion(as, io_base, >io);
> > }
> >
> > /**
> > @@ -342,7 +335,8 @@ const VMStateDescription vmstate_memory_hotplug
> > = {
> >
> > void build_memory_hotplug_aml(Aml *table, uint32_t nr_mem,
> >const char *res_root,
> > - const char *event_handler_method)
> > + const char *event_handler_method,
> > + AmlRegionSpace rs, hwaddr
> > memhp_io_base)
> > {
> > int i;
> > Aml *ifctx;
> > @@ -365,14 +359,19 @@ void build_memory_hotplug_aml(Aml *table,
> > uint32_t nr_mem,
> > aml_name_decl("_UID", aml_string("Memory hotplug
> > resources")));
> >
> > crs = aml_resource_template();
> > -aml_append(crs,
> > -aml_io(AML_DECODE16, memhp_io_base, memhp_io_base, 0,
> > - MEMORY_HOTPLUG_IO_LEN)
> > -);
> > +if (rs == AML_SYSTEM_IO) {
> > +aml_append(crs,
> > +aml_io(AML_DECODE16, memhp_io_base,
> > memhp_io_base, 0,
> > + MEMORY_HOTPLUG_IO_LEN)
> > +);
Re: [Qemu-devel] [PATCH v9 11/13] block: add lock/unlock range functions
28.08.2019 20:02, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> From: Vladimir Sementsov-Ogievskiy > > Hm. :-) > > Do you want to fix that? Yes.. Hmm seems like I was working from home at some moment > >> Introduce lock/unlock range functionality, based on serialized >> requests. This is needed to refactor backup, dropping local >> tracked-request-like synchronization. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> include/block/block_int.h | 4 >> block/io.c| 44 ++- >> 2 files changed, 47 insertions(+), 1 deletion(-) > > Apart from that, I can’t see any changes from v8, so: > > Reviewed-by: Max Reitz > -- Best regards, Vladimir
[Qemu-devel] [PATCH 2/2] scripts/git.orderfile: Order shell scripts before unordered files
Order shell scripts before the rest of unordered files. This helps in particular while reviewing iotests. Signed-off-by: Philippe Mathieu-Daudé --- scripts/git.orderfile | 4 1 file changed, 4 insertions(+) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index 0ad5b9b8a8..4d25153ea4 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -28,3 +28,7 @@ Makefile* *.c *.py +# shell scripts +*.rc +*.sh + -- 2.20.1
Re: [Qemu-devel] [patch-for-4.2 PATCH v11 3/6] target/ppc: Handle NMI guest exit
On Wed, 14 Aug 2019 11:41:16 +0530
Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
> Patch [1] enhances KVM to exit guest with exit reason
> set to KVM_EXIT_NMI in such cases. This patch handles
> KVM_EXIT_NMI exit.
>
> [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html
> (e20bbd3d and related commits)
>
> Signed-off-by: Aravinda Prasad
> Reviewed-by: David Gibson
> ---
> hw/ppc/spapr.c |8
> hw/ppc/spapr_events.c | 23 +++
> include/hw/ppc/spapr.h | 10 ++
> target/ppc/kvm.c| 14 ++
> target/ppc/kvm_ppc.h|2 ++
> target/ppc/trace-events |1 +
> 6 files changed, 58 insertions(+)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 07714cb..99def34 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1813,6 +1813,12 @@ static void spapr_machine_reset(MachineState *machine)
> first_ppc_cpu->env.gpr[5] = 0;
>
> spapr->cas_reboot = false;
> +
> +spapr->mc_status = -1;
> +spapr->guest_machine_check_addr = -1;
> +
> +/* Signal all vCPUs waiting on this condition */
> +qemu_cond_broadcast(>mc_delivery_cond);
> }
>
> static void spapr_create_nvram(SpaprMachineState *spapr)
> @@ -3089,6 +3095,8 @@ static void spapr_machine_init(MachineState *machine)
>
> kvmppc_spapr_enable_inkernel_multitce();
> }
> +
> +qemu_cond_init(>mc_delivery_cond);
> }
>
> static int spapr_kvm_type(MachineState *machine, const char *vm_type)
> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
> index ae0f093..a0c66d7 100644
> --- a/hw/ppc/spapr_events.c
> +++ b/hw/ppc/spapr_events.c
> @@ -620,6 +620,29 @@ void
> spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
> RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, _id);
> }
>
> +void spapr_mce_req_event(PowerPCCPU *cpu)
> +{
> +SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
> +
> +while (spapr->mc_status != -1) {
> +/*
> + * Check whether the same CPU got machine check error
> + * while still handling the mc error (i.e., before
> + * that CPU called "ibm,nmi-interlock")
> + */
> +if (spapr->mc_status == cpu->vcpu_id) {
> +qemu_system_guest_panicked(NULL);
> +return;
> +}
> +qemu_cond_wait_iothread(>mc_delivery_cond);
hw/ppc/spapr_events.c: In function ‘spapr_mce_req_event’:
hw/ppc/spapr_events.c:638:9: error: implicit declaration of function
‘qemu_cond_wait_iothread’; did you mean ‘qemu_cond_wait_impl’?
[-Werror=implicit-function-declaration]
qemu_cond_wait_iothread(>mc_delivery_cond);
^~~
qemu_cond_wait_impl
hw/ppc/spapr_events.c:638:9: error: nested extern declaration of
‘qemu_cond_wait_iothread’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
It looks like hw/ppc/spapr_events.c is missing:
#include "qemu/main-loop.h"
> +/* Meanwhile if the system is reset, then just return */
> +if (spapr->guest_machine_check_addr == -1) {
> +return;
> +}
> +}
> +spapr->mc_status = cpu->vcpu_id;
> +}
> +
> static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr,
> uint32_t token, uint32_t nargs,
> target_ulong args,
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 01c106f..619677a 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -191,6 +191,15 @@ struct SpaprMachineState {
> * occurs during the unplug process. */
> QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
>
> +/* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */
> +target_ulong guest_machine_check_addr;
> +/*
> + * mc_status is set to -1 if mc is not in progress, else is set to the
> CPU
> + * handling the mc.
> + */
> +int mc_status;
> +QemuCond mc_delivery_cond;
> +
> /*< public >*/
> char *kvm_type;
> char *host_model;
> @@ -804,6 +813,7 @@ void spapr_clear_pending_events(SpaprMachineState *spapr);
> int spapr_max_server_number(SpaprMachineState *spapr);
> void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
>uint64_t pte0, uint64_t pte1);
> +void spapr_mce_req_event(PowerPCCPU *cpu);
>
> /* DRC callbacks. */
> void spapr_core_release(DeviceState *dev);
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index c922bcb..375dc09 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -1702,6 +1702,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run
> *run)
> ret = 0;
> break;
>
> +case KVM_EXIT_NMI:
> +
[Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14
From: Aleksandar Markovic
Clean up handling of CP0 register 14.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-16-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4fce05a..2a9c6d5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -361,6 +361,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
+#define CP0_REG14__NESTEDEPC 2
/* CP0 Register 15 */
#define CP0_REG15__PRID0
#define CP0_REG15__EBASE 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4da08e1..efedced 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7212,7 +7212,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
@@ -7946,7 +7946,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -8687,7 +8687,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -9409,7 +9409,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
--
2.7.4
[Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2
From: Aleksandar Markovic
Clean up handling of CP0 register 2.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-4-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 7 ++
target/mips/translate.c | 64 -
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 36e983a..466f72a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -292,6 +292,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO00
+#define CP0_REG02__TCSTATUS1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO10
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97e0aec..66c6207 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
-case 0:
+case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "EntryLo0";
break;
-case 1:
+case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
-case 2:
+case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
-case 3:
+case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
-case 4:
+case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
-case 5:
+case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
-case 6:
+case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
-case 7:
+case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7650,41 +7650,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
-case 0:
+case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
-case 1:
+case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
-case 2:
+case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
-case 3:
+case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
-case 4:
+case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
-case 5:
+case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
-case 6:
+case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
-case 7:
+case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name =
[Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0
From: Aleksandar Markovic
Clean up handling of CP0 register 0.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-2-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 40
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a18..42d0e44 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF02
+#define CP0_REG00__MVPCONF13
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ebde6f..c3fcfb4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
-
[Qemu-devel] [PATCH] virtiofsd: add man page
Signed-off-by: Stefan Hajnoczi
---
Makefile | 7 +++
contrib/virtiofsd/virtiofsd.texi | 85
2 files changed, 92 insertions(+)
create mode 100644 contrib/virtiofsd/virtiofsd.texi
diff --git a/Makefile b/Makefile
index a3dfdd6fa8..cc18025753 100644
--- a/Makefile
+++ b/Makefile
@@ -334,6 +334,9 @@ DOCS+=docs/qemu-cpu-models.7
ifdef CONFIG_VIRTFS
DOCS+=fsdev/virtfs-proxy-helper.1
endif
+ifdef CONFIG_LINUX
+DOCS+=contrib/virtiofsd/virtiofsd.1
+endif
ifdef CONFIG_TRACE_SYSTEMTAP
DOCS+=scripts/qemu-trace-stap.1
endif
@@ -834,6 +837,9 @@ ifdef CONFIG_VIRTFS
$(INSTALL_DIR) "$(DESTDIR)$(mandir)/man1"
$(INSTALL_DATA) fsdev/virtfs-proxy-helper.1 "$(DESTDIR)$(mandir)/man1"
endif
+ifdef CONFIG_LINUX
+ $(INSTALL_DATA) contrib/virtiofsd.1 "$(DESTDIR)$(mandir)/man1"
+endif
install-datadir:
$(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)"
@@ -1018,6 +1024,7 @@ qemu.1: qemu-doc.texi qemu-options.texi qemu-monitor.texi
qemu-monitor-info.texi
qemu.1: qemu-option-trace.texi
qemu-img.1: qemu-img.texi qemu-option-trace.texi qemu-img-cmds.texi
fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi
+contrib/virtiofsd/virtiofsd.1: contrib/virtiofsd/virtiofsd.texi
qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
qemu-ga.8: qemu-ga.texi
docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi
diff --git a/contrib/virtiofsd/virtiofsd.texi b/contrib/virtiofsd/virtiofsd.texi
new file mode 100644
index 00..eec7fbf4e6
--- /dev/null
+++ b/contrib/virtiofsd/virtiofsd.texi
@@ -0,0 +1,85 @@
+@example
+@c man begin SYNOPSIS
+@command{virtiofsd} [OPTION]
@option{--socket-path=}@var{path}|@option{--fd=}@var{fdnum} @option{-o
source=}@var{path}
+@c man end
+@end example
+
+@c man begin DESCRIPTION
+
+Share a host directory tree with a guest through a virtio-fs device. This
+program is a vhost-user backend that implements the virtio-fs device. Each
+virtio-fs device instance requires its own virtiofsd process.
+
+This program is designed to work with QEMU's @code{--device vhost-user-fs-pci}
+but should work with any virtual machine monitor (VMM) that supports
+vhost-user. See the EXAMPLES section below.
+
+This program must be run as the root user. Upon startup the program will
+switch into a new file system namespace with the shared directory tree as its
+root. This prevents "file system escapes" due to symlinks and other file
+system objects that might lead to files outside the shared directory. The
+program also sandboxes itself using seccomp(2) to prevent ptrace(2) and other
+vectors that could allow an attacker to compromise the system after gaining
+control of the virtiofsd process.
+
+@c man end
+
+@c man begin OPTIONS
+@table @option
+@item -h, --help
+Print help.
+@item -V, --version
+Print version.
+@item -d, -o debug
+Enable debug output.
+@item --syslog
+Print log messages to syslog instead of stderr.
+@item -o log_level=@var{level}
+Print only log messages matching @var{level} or more severe. @var{level} is
+one of @code{err}, @code{warn}, @code{info}, or @code{debug}. The default is
+@var{info}.
+@item -o source=@var{path}
+Share host directory tree located at @var{path}. This option is required.
+@item --socket-path=@var{path}, -o vhost_user_socket=@var{path}
+Listen on vhost-user UNIX domain socket at @var{path}.
+@item --fd=@var{fdnum}
+Accept connections from vhost-user UNIX domain socket file descriptor
@var{fdnum}. The file descriptor must already be listening for connections.
+@item --thread-pool-size=@var{num}
+Restrict the number of worker threads per request queue to @var{num}. The
default is 64.
+@item --cache=@code{none}|@code{auto}|@code{always}
+Select the desired trade-off between coherency and performance. @code{none}
+forbids the FUSE client from caching to achieve best coherency at the cost of
+performance. @code{auto} acts similar to NFS with a 1 second metadata cache
+timeout. @code{always} sets a long cache lifetime at the expense of coherency.
+@item --writeback
+Enable writeback cache, allowing the FUSE client to buffer and merge write
requests.
+@end table
+@c man end
+
+@c man begin EXAMPLES
+Export @code{/var/lib/fs/vm001/} on vhost-user UNIX domain socket
@code{/var/run/vm001-vhost-fs.sock}:
+
+@example
+host# virtiofsd --socket-path=/var/run/vm001-vhost-fs.sock -o
source=/var/lib/fs/vm001
+host# qemu-system-x86_64 \
+-chardev socket,id=char0,path=/var/run/vm001-vhost-fs.sock \
+-device vhost-user-fs-pci,chardev=char0,tag=myfs \
+-object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on \
+-numa node,memdev=mem \
+...
+guest# mount -t virtio_fs \
+-o
default_permissions,allow_other,user_id=0,group_id=0,rootmode=04,dax \
+myfs /mnt
+@end example
+@c man end
+
+@ignore
+@setfilename virtiofsd
+@settitle QEMU virtio-fs shared file system daemon
+
+@c man begin AUTHOR
+Copyright (C) 2019 Red Hat, Inc.
+This is free software; see the
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On 8/29/19 5:15 PM, Daniel P. Berrangé wrote:
> On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote:
>> From: He Zhe
>>
>> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
>> handling for libgcrypt.
> Where are you seeing pkg-config files for libgcrypt ?
>
> The upstream project has (frustratingly) been hostile to any proposal to
> add pkg-config support saying people should stick with their custom
> libgcrypt-config tool
>
>https://dev.gnupg.org/T2037
>
> Even if this is something added by some distro downstream, what is the
> benefit in using it, compared with libgcrypt-confg which should already
> work & is portable.
IMHO, it could be easy for people to use pkg-config as a center to control
configurations for many different packages.
This is just an addition for qemu to be able to work in both cases. It does not
remove libgcrypt-confg and can fall back to libgcrypt-confg when pkg-config does
not work.
Zhe
>
>> Signed-off-by: He Zhe
>> ---
>> configure | 48
>> 1 file changed, 40 insertions(+), 8 deletions(-)
>>
>> diff --git a/configure b/configure
>> index e44e454..0f362a7 100755
>> --- a/configure
>> +++ b/configure
>> @@ -2875,6 +2875,30 @@ has_libgcrypt() {
>> return 0
>> }
>>
>> +has_libgcrypt_pkgconfig() {
>> +if ! has $pkg_config ; then
>> +return 1
>> +fi
>> +
>> +if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
>> +return 1
>> +fi
>> +
>> +if test -n "$cross_prefix" ; then
>> +host=$($pkg_config --variable=host libgcrypt)
>> +if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
>> +print_error "host($host) does not match
>> cross_prefix($cross_prefix)"
>> +return 1
>> +fi
>> +fi
>> +
>> +if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
>> +print_error "libgcrypt version is $($pkg_config --modversion
>> libgcrypt)"
>> +return 1
>> +fi
>> +
>> +return 0
>> +}
>>
>> if test "$nettle" != "no"; then
>> pass="no"
>> @@ -2902,7 +2926,14 @@ fi
>>
>> if test "$gcrypt" != "no"; then
>> pass="no"
>> -if has_libgcrypt; then
>> +if has_libgcrypt_pkgconfig; then
>> +gcrypt_cflags=$($pkg_config --cflags libgcrypt)
>> +if test "$static" = "yes" ; then
>> +gcrypt_libs=$($pkg_config --libs --static libgcrypt)
>> +else
>> +gcrypt_libs=$($pkg_config --libs libgcrypt)
>> +fi
>> +elif has_libgcrypt; then
>> gcrypt_cflags=$(libgcrypt-config --cflags)
>> gcrypt_libs=$(libgcrypt-config --libs)
>> # Debian has removed -lgpg-error from libgcrypt-config
>> @@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
>> then
>> gcrypt_libs="$gcrypt_libs -lgpg-error"
>> fi
>> +fi
>>
>> -# Link test to make sure the given libraries work (e.g for static).
>> -write_c_skeleton
>> -if compile_prog "" "$gcrypt_libs" ; then
>> -LIBS="$gcrypt_libs $LIBS"
>> -QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
>> -pass="yes"
>> -fi
>> +# Link test to make sure the given libraries work (e.g for static).
>> +write_c_skeleton
>> +if compile_prog "" "$gcrypt_libs" ; then
>> +LIBS="$gcrypt_libs $LIBS"
>> +QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
>> +pass="yes"
>> fi
>> +
>> if test "$pass" = "yes"; then
>> gcrypt="yes"
>> cat > $TMPC << EOF
>> --
>> 2.7.4
>>
> Regards,
> Daniel
[Qemu-devel] [PULL 3/3] usb-mtp: add sanity checks on rootdir
From: Bandan Das
Currently, we don't check if rootdir exists and is accessible.
Furthermore, a trailing slash results in a null "desc" string which
ends up in the share not visible in the guest. Add some simple
sanity checks for appropriate permissions. Also, bail out if the
user does not supply an absolute path.
Signed-off-by: Bandan Das
Message-id: jpga7bto3on@linux.bootlegged.copy
Signed-off-by: Gerd Hoffmann
---
hw/usb/dev-mtp.c | 38 --
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 9846e4b5130b..7c07295519d3 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -2038,26 +2038,36 @@ static void usb_mtp_realize(USBDevice *dev, Error
**errp)
{
MTPState *s = USB_MTP(dev);
-usb_desc_create_serial(dev);
-usb_desc_init(dev);
-QTAILQ_INIT(>objects);
-if (s->desc == NULL) {
-if (s->root == NULL) {
-error_setg(errp, "usb-mtp: rootdir property must be configured");
-return;
-}
-s->desc = strrchr(s->root, '/');
-if (s->desc && s->desc[0]) {
-s->desc = g_strdup(s->desc + 1);
-} else {
-s->desc = g_strdup("none");
-}
+if ((s->root == NULL) || !g_path_is_absolute(s->root)) {
+error_setg(errp, "usb-mtp: rootdir must be configured and be an
absolute path");
+return;
}
+
+if (access(s->root, R_OK) != 0) {
+error_setg(errp, "usb-mtp: rootdir does not exist/not readable");
+return;
+} else if (!s->readonly && access(s->root, W_OK) != 0) {
+error_setg(errp, "usb-mtp: rootdir does not have write permissions");
+return;
+}
+
/* Mark store as RW */
if (!s->readonly) {
s->flags |= (1 << MTP_FLAG_WRITABLE);
}
+if (s->desc == NULL) {
+/*
+ * This does not check if path exists
+ * but we have the checks above
+ */
+s->desc = g_path_get_basename(s->root);
+}
+
+usb_desc_create_serial(dev);
+usb_desc_init(dev);
+QTAILQ_INIT(>objects);
+
}
static const VMStateDescription vmstate_usb_mtp = {
--
2.18.1
[Qemu-devel] [PULL 1/3] xhci: Fix memory leak in xhci_address_slot
From: Ying Fang Address Sanitizer shows memory leak in xhci_address_slot hw/usb/hcd-xhci.c:2156 and the stack is as bellow: Direct leak of 64 byte(s) in 4 object(s) allocated from: #0 0x91c6f5ab in realloc (/lib64/libasan.so.4+0xd35ab) #1 0x91987243 in g_realloc (/lib64/libglib-2.0.so.0+0x57243) #2 0xb0b26a1f in qemu_iovec_add util/iov.c:296 #3 0xb07e5ce3 in xhci_address_slot hw/usb/hcd-xhci.c:2156 #4 0xb07e5ce3 in xhci_process_commands hw/usb/hcd-xhci.c:2493 #5 0xb00058d7 in memory_region_write_accessor qemu/memory.c:507 #6 0xbd87 in access_with_adjusted_size memory.c:573 #7 0xb000abcf in memory_region_dispatch_write memory.c:1516 #8 0xaff59947 in flatview_write_continue exec.c:3367 #9 0xaff59c33 in flatview_write exec.c:3406 #10 0xaff63b3b in address_space_write exec.c:3496 #11 0xb002f263 in kvm_cpu_exec accel/kvm/kvm-all.c:2288 #12 0xaffee427 in qemu_kvm_cpu_thread_fn cpus.c:1290 #13 0xb0b1a943 in qemu_thread_start util/qemu-thread-posix.c:502 #14 0x908ce8bb in start_thread (/lib64/libpthread.so.0+0x78bb) #15 0x908165cb in thread_start (/lib64/libc.so.6+0xd55cb) Cc: zhanghailiang Signed-off-by: Ying Fang Reviewed-by: Li Qiang Message-id: 20190827080209.2365-1-fangyi...@huawei.com Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index f5782649482b..471759cd4cc0 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2161,6 +2161,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, DeviceOutRequest | USB_REQ_SET_ADDRESS, slotid, 0, 0, NULL); assert(p.status != USB_RET_ASYNC); +usb_packet_cleanup(); } res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); -- 2.18.1
Re: [Qemu-devel] [PATCH] target/arm: Fix SMMLS argument order
Hi,
On Thu, Aug 29, 2019 at 3:33 AM Richard Henderson
wrote:
>
> The previous simplification got the order of operands to the
> subtraction wrong. Since the 64-bit product is the subtrahend,
> we must use a 64-bit subtract to properly compute the borrow
> from the low-part of the product.
>
> Fixes: 5f8cd06ebcf5 ("target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR")
> Reported-by: Laurent Desnogues
> Signed-off-by: Richard Henderson
Tested-by: Laurent Desnogues
Thanks,
Laurent
> ---
> target/arm/translate.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index cbe19b7a62..a0f7577f47 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8824,7 +8824,16 @@ static void disas_arm_insn(DisasContext *s, unsigned
> int insn)
> if (rd != 15) {
> tmp3 = load_reg(s, rd);
> if (insn & (1 << 6)) {
> -tcg_gen_sub_i32(tmp, tmp, tmp3);
> +/*
> + * For SMMLS, we need a 64-bit subtract.
> + * Borrow caused by a non-zero multiplicand
> + * lowpart, and the correct result lowpart
> + * for rounding.
> + */
> +TCGv_i32 zero = tcg_const_i32(0);
> +tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3,
> + tmp2, tmp);
> +tcg_temp_free_i32(zero);
> } else {
> tcg_gen_add_i32(tmp, tmp, tmp3);
> }
> @@ -10068,7 +10077,14 @@ static void disas_thumb2_insn(DisasContext *s,
> uint32_t insn)
> if (insn & (1 << 20)) {
> tcg_gen_add_i32(tmp, tmp, tmp3);
> } else {
> -tcg_gen_sub_i32(tmp, tmp, tmp3);
> +/*
> + * For SMMLS, we need a 64-bit subtract.
> + * Borrow caused by a non-zero multiplicand lowpart,
> + * and the correct result lowpart for rounding.
> + */
> +TCGv_i32 zero = tcg_const_i32(0);
> +tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp);
> +tcg_temp_free_i32(zero);
> }
> tcg_temp_free_i32(tmp3);
> }
> --
> 2.17.1
>
Re: [Qemu-devel] [RFC 2/3] intc/arm_gic: Support PPI injection for more than 256 vpus
Hi Zenghui,
On 8/29/19 4:53 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2019/8/28 0:05, Eric Auger wrote:
>> Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
>> allow injection of PPIs along with vcpu ids larger than 255. Let's
>> encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
>> ABI when needed.
>>
>> Without that patch qemu exits with "kvm_set_irq: Invalid argument"
>> message.
>>
>> Signed-off-by: Eric Auger
>> Reported-by: Zenghui Yu
>> ---
>> hw/intc/arm_gic_kvm.c | 10 +++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
>> index b56fda144f..889293e97f 100644
>> --- a/hw/intc/arm_gic_kvm.c
>> +++ b/hw/intc/arm_gic_kvm.c
>> @@ -56,6 +56,7 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq,
>> int level)
>> * CPU number and interrupt number.
>> */
>> int kvm_irq, irqtype, cpu;
>> + int cpu_idx1 = 0, cpu_idx2 = 0;
>> if (irq < (num_irq - GIC_INTERNAL)) {
>> /* External interrupt. The kernel numbers these like the GIC
>> @@ -63,17 +64,20 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int
>> irq, int level)
>> * internal ones.
>> */
>> irqtype = KVM_ARM_IRQ_TYPE_SPI;
>> - cpu = 0;
>> irq += GIC_INTERNAL;
>> } else {
>> /* Internal interrupt: decode into (cpu, interrupt id) */
>> irqtype = KVM_ARM_IRQ_TYPE_PPI;
>> irq -= (num_irq - GIC_INTERNAL);
>> cpu = irq / GIC_INTERNAL;
>> + cpu_idx2 = cpu / 256;
>> + cpu_idx1 = cpu % 256;
>> irq %= GIC_INTERNAL;
>> }
>> - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
>> - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
>> + kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) |
>> + (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) |
>> + ((cpu_idx2 & KVM_ARM_IRQ_VCPU2_MASK) <<
>> KVM_ARM_IRQ_VCPU2_SHIFT) |
>> + irq;
>> kvm_set_irq(kvm_state, kvm_irq, !!level);
>> }
>>
>
> For confirmation, should we also adjust the vcpu_index in
> arm_cpu_kvm_set_irq(), just like above?
I am not familiar with this path. in arm_cpu_initfn(), there is a
comment saying "VIRQ and VFIQ are unused with KVM but we add them to
maintain the same interface as non-KVM CPUs." So I don't know when that
code gets executed.
But maybe it would be more cautious to implement your suggestion here as
well.
Maybe Peter can provide more info here?
Thanks
Eric
>
>
> Thanks,
> zenghui
>
>
[Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10
From: Aleksandar Markovic
Clean up handling of CP0 register 10.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-12-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 50a7205..3797bdc 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -342,6 +342,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG10__ENTRYHI 0
#define CP0_REG10__GUESTCTL1 4
#define CP0_REG10__GUESTCTL2 5
+#define CP0_REG10__GUESTCTL3 6
/* CP0 Register 11 */
#define CP0_REG11__COMPARE 0
#define CP0_REG11__GUESTCTL0EXT4
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b79c58c..50863cf 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7155,7 +7155,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
@@ -7872,7 +7872,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -8631,7 +8631,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
@@ -9333,7 +9333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
--
2.7.4
[Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7
From: Aleksandar Markovic
Clean up handling of CP0 register 7.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-9-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a914fe4..cf2ba5a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7086,7 +7086,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -7818,7 +7818,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -8563,7 +8563,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -9277,7 +9277,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
--
2.7.4
[Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8
From: Aleksandar Markovic
Clean up handling of CP0 register 8.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-10-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 32
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a0c6a6f..50a7205 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -333,6 +333,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG08__BADVADDR0
#define CP0_REG08__BADINSTR1
#define CP0_REG08__BADINSTRP 2
+#define CP0_REG08__BADINSTRX 3
/* CP0 Register 09 */
#define CP0_REG09__COUNT 0
#define CP0_REG09__SAARI 6
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf2ba5a..d4faa75 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7097,22 +7097,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0x);
@@ -7830,19 +7830,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -8574,21 +8574,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0x);
@@ -9289,19 +9289,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
--
2.7.4
[Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019
From: Aleksandar Markovic The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052: target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200) are available in the git repository at: https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019 for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943: target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200) MIPS queue for August 29th, 2019 Highlights: - cleanup of handling of configuration register CP0 - fix for ST.W emulation (in system mode only) Aleksandar Markovic (31): target/mips: Clean up handling of CP0 register 0 target/mips: Clean up handling of CP0 register 1 target/mips: Clean up handling of CP0 register 2 target/mips: Clean up handling of CP0 register 3 target/mips: Clean up handling of CP0 register 4 target/mips: Clean up handling of CP0 register 5 target/mips: Clean up handling of CP0 register 6 target/mips: Clean up handling of CP0 register 7 target/mips: Clean up handling of CP0 register 8 target/mips: Clean up handling of CP0 register 9 target/mips: Clean up handling of CP0 register 10 target/mips: Clean up handling of CP0 register 11 target/mips: Clean up handling of CP0 register 12 target/mips: Clean up handling of CP0 register 13 target/mips: Clean up handling of CP0 register 14 target/mips: Clean up handling of CP0 register 15 target/mips: Clean up handling of CP0 register 16 target/mips: Clean up handling of CP0 register 17 target/mips: Clean up handling of CP0 register 18 target/mips: Clean up handling of CP0 register 19 target/mips: Clean up handling of CP0 register 20 target/mips: Clean up handling of CP0 register 23 target/mips: Clean up handling of CP0 register 24 target/mips: Clean up handling of CP0 register 25 target/mips: Clean up handling of CP0 register 26 target/mips: Clean up handling of CP0 register 27 target/mips: Clean up handling of CP0 register 28 target/mips: Clean up handling of CP0 register 29 target/mips: Clean up handling of CP0 register 30 target/mips: Clean up handling of CP0 register 31 target/mips: Fix emulation of ST.W in system mode target/mips/cpu.h | 113 - target/mips/op_helper.c | 16 +- target/mips/translate.c | 1142 --- 3 files changed, 685 insertions(+), 586 deletions(-) -- 2.7.4
[Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28
From: Aleksandar Markovic
Clean up handling of CP0 register 28.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-28-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 24 +++
target/mips/translate.c | 64 -
2 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 40b7cc6..de9e850 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLoDataHiErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLoDataHi KScratch
- * 3 TagLo TagHi KScratch
- * 4 DataLoDataHi KScratch
- * 5 TagLo TagHi KScratch
- * 6 DataLoDataHi KScratch
- * 7 TagLo TagHi KScratch
+ * 2 DataLo1 DataHi KScratch
+ * 3 TagLo1TagHi KScratch
+ * 4 DataLo2 DataHi KScratch
+ * 5 TagLo2TagHi KScratch
+ * 6 DataLo3 DataHi KScratch
+ * 7 TagLo3TagHi KScratch
*
*/
#define CP0_REGISTER_00 0
@@ -427,10 +427,14 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
-#define CP0_REG28__ITAGLO 0
-#define CP0_REG28__IDATALO 1
-#define CP0_REG28__DTAGLO 2
-#define CP0_REG28__DDATALO 3
+#define CP0_REG28__TAGLO 0
+#define CP0_REG28__DATALO 1
+#define CP0_REG28__TAGLO1 2
+#define CP0_REG28__DATALO1 3
+#define CP0_REG28__TAGLO2 4
+#define CP0_REG28__DATALO2 5
+#define CP0_REG28__TAGLO3 6
+#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c969c25..032e3b0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7476,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState,
CP0_TagLo));
@@ -7488,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -8231,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -8959,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
[Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25
From: Aleksandar Markovic
Clean up handling of CP0 register 25.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-25-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 64 -
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 515d04c..84aabf6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7418,35 +7418,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
/* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
-case 6:
+case CP0_REG25__PERFCTL3:
/* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
-case 7:
+case CP0_REG25__PERFCNT3:
/* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8175,35 +8175,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
-case 6:
+case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
-case 7:
+case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8906,35 +8906,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
Re: [Qemu-devel] [Qemu-ppc] [patch-for-4.2 PATCH v11 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests
On Thursday 29 August 2019 03:51 PM, Greg Kurz wrote: > On Wed, 14 Aug 2019 11:40:50 +0530 > Aravinda Prasad wrote: > >> This patch set adds support for FWNMI in PowerKVM guests. >> >> System errors such as SLB multihit and memory errors >> that cannot be corrected by hardware is passed on to >> the kernel for handling by raising machine check >> exception (an NMI). Upon such machine check exceptions, >> if the address in error belongs to guest then KVM >> invokes guests' 0x200 interrupt vector if the guest >> is not FWNMI capable. For FWNMI capable guest >> KVM passes the control to QEMU by exiting the guest. >> >> This patch series adds functionality to QEMU to pass >> on such machine check exceptions to the FWNMI capable >> guest kernel by building an error log and invoking >> the guest registered machine check handling routine. >> >> The KVM changes are now part of the upstream kernel >> (commit e20bbd3d). This series contain QEMU changes. >> >> Change Log v11: >> - Moved FWNMI SPAPR cap defaults to 4.2 class option >> - Fixed issues with handling fwnmi KVM capability >> > > Hi Aravinda, > > I'm afraid this series needs rebasing. It doesn't apply > cleanly on current ppc-for-4.2 (SHA1 b1e8156743). This was based on the latest 4.2 at the time of posting (14th Aug). Meanwhile may be due to changes to 4.2 it is not applying cleanly. I will rebase it to the latest 4.2 and post it again. Regards, Aravinda > > Cheers, > > -- > Greg > >> Change Log v10: >> - Reshuffled the patch sequence + minor fixes >> >> Change Log v9: >> - Fixed kvm cap and spapr cap issues >> >> Change Log v8: >> - Added functionality to check FWNMI capability during >> VM migration >> --- >> >> Aravinda Prasad (6): >> Wrapper function to wait on condition for the main loop mutex >> ppc: spapr: Introduce FWNMI capability >> target/ppc: Handle NMI guest exit >> target/ppc: Build rtas error log upon an MCE >> ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS >> calls >> migration: Include migration support for machine check handling >> >> >> cpus.c |5 + >> hw/ppc/spapr.c | 78 + >> hw/ppc/spapr_caps.c | 29 + >> hw/ppc/spapr_events.c| 268 >> ++ >> hw/ppc/spapr_rtas.c | 78 + >> include/hw/ppc/spapr.h | 25 >> include/qemu/main-loop.h |8 + >> target/ppc/cpu.h |1 >> target/ppc/kvm.c | 38 +++ >> target/ppc/kvm_ppc.h | 13 ++ >> target/ppc/trace-events |1 >> 11 files changed, 542 insertions(+), 2 deletions(-) >> >> -- >> Signature > > -- Regards, Aravinda
Re: [Qemu-devel] [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space configurable
Hi Igor,
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: 29 August 2019 09:45
> To: Shameerali Kolothum Thodi
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; sa...@linux.intel.com;
> ard.biesheu...@linaro.org; Linuxarm ;
> shannon.zha...@gmail.com; sebastien.bo...@intel.com; ler...@redhat.com
> Subject: Re: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> configurable
>
> On Thu, 15 Aug 2019 08:42:48 +
> Shameerali Kolothum Thodi wrote:
>
> > > -Original Message-
> > > From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of
> Shameer
> > > Kolothum
> > > Sent: 13 August 2019 22:05
> > > To: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > > eric.au...@redhat.com; imamm...@redhat.com
> > > Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> > > ard.biesheu...@linaro.org; Linuxarm ;
> > > shannon.zha...@gmail.com; sebastien.bo...@intel.com;
> ler...@redhat.com
> > > Subject: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > > configurable
> > >
> > > This is in preparation for adding support for ARM64 platforms
> > > where it doesn't use port mapped IO for ACPI IO space. We are
> > > making changes so that MMIO region can be accommodated
> > > and board can pass the base address into the aml build function.
> >
> > Looks like, this now breaks the "make check" on x86_64 and needs
> > updating bios-tables-test-allowed-diff.h with DSDT entries. But I am
> > not sure what changed now compared to v8(and older ones) that makes
> > it to complain now!.
>
> you could see diff of what's changed but running test manually with
> V=1 env var if you have 'iasl' installed
>
> V=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64
> tests/bios-tables-test
Thanks for that tip and please find below output.
/x86_64/acpi/piix4: Could not access KVM kernel module: No such file or
directory
qemu-system-x86_64: failed to initialize KVM: No such file or directory
qemu-system-x86_64: Back to tcg accelerator
acpi-test: Warning! DSDT binary file mismatch. Actual [aml:/tmp/aml-RGE76Z],
Expected [aml:tests/data/acpi/pc/DSDT].
acpi-test: Warning! DSDT mismatch. Actual [asl:/tmp/asl-TAE76Z.dsl,
aml:/tmp/aml-RGE76Z], Expected [asl:/tmp/asl-O6B76Z.dsl,
aml:tests/data/acpi/pc/DSDT].
diff --git a/tmp/asl-O6B76Z.dsl b/tmp/asl-TAE76Z.dsl
index 823ff002ec..4de5bd3221 100644
--- a/tmp/asl-O6B76Z.dsl
+++ b/tmp/asl-TAE76Z.dsl
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/pc/DSDT, Thu Aug 29 10:40:40 2019
+ * Disassembly of /tmp/aml-RGE76Z, Thu Aug 29 10:40:40 2019
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x140B (5131)
+ * Length 0x17E4 (6116)
* Revision 0x01 32-bit table (V1), no 64-bit math support
- * Checksum 0xB1
+ * Checksum 0x8B
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x0001 (1)
@@ -787,6 +787,206 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT",
0x0001)
\_SB.CPUS.CSCN ()
}
+Device (\_SB.PCI0.MHPD)
+{
+Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID:
Hardware ID
+Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+Name (_CRS, Reso
I think what happens is since we are now passing the memhp_io_base directly
into the
build_memory_hotplug_aml() and removed the "static uint16_t memhp_io_base", on
x86, memory hotplug aml code is always built by default irrespective of whether
acpi_memory_hotplug_init() is invoked or not.
I could either reintroduce a check in build_memory_hotplug_aml() to make sure
acpi_memory_hotplug_init() is called, or could do something like below,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 3995f9a40f..17756c2191 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1873,9 +1873,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
"\\_SB.PCI0", "\\_GPE._E02");
}
-build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
- "\\_GPE._E03", AML_SYSTEM_IO,
- pcms->memhp_io_base);
+
+if (acpi_enabled && pcms->acpi_dev && nr_mem) {
+build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
+ "\\_GPE._E03", AML_SYSTEM_IO,
+ pcms->memhp_io_base);
+}
I prefer the latter if there are no other issues with that. Please let me know.
Thanks,
Shameer
>
> > Patchew URL:
> https://patchew.org/QEMU/20190813210539.31164-1-shameerali.kolothum.t
> h...@huawei.com/
> >
> > ERROR:/tmp/qemu-test/src/tests/bios-tables-test.c:447:test_acpi_asl:
> assertion failed: (all_tables_match)
> >
> > Thanks,
> > Shameer
> >
> > >
Re: [Qemu-devel] [PATCH v9 05/13] block: move block_copy from block/backup.c to separate file
28.08.2019 19:16, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> Split block_copy to separate file, to be cleanly shared with backup-top >> filter driver in further commits. >> >> It's a clean movement, the only change is drop "static" from interface >> functions. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> include/block/block-copy.h | 59 +++ >> block/backup.c | 313 + >> block/block-copy.c | 307 >> block/Makefile.objs| 1 + >> block/trace-events | 2 + >> 5 files changed, 370 insertions(+), 312 deletions(-) >> create mode 100644 include/block/block-copy.h >> create mode 100644 block/block-copy.c > > May change depending on changes to the preceding patches, but FWIW > > Reviewed-by: Max Reitz > If you don't mind, I'll keep it until the patch doing simple nochange movement. -- Best regards, Vladimir
Re: [Qemu-devel] [PATCH v2 5/7] mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well
26.08.2019. 09.52, "David Hildenbrand" је написао/ла:
>
> Let's call it also for CONFIG_USER_ONLY. While at it, add a FIXME and get
> rid of one local variable.
>
> MIPS code probably needs a bigger refactoring in regards of
> ensure_writable_pages(), similar to s390x, so for example, watchpoints
> can be handled reliably later. The actually accessed addresses should
> be probed only, not full pages.
>
> Signed-off-by: David Hildenbrand
> ---
Reviewed-by: Aleksandar Markovic
> target/mips/op_helper.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 34bcc8d884..08d9a4f9f1 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -4537,16 +4537,14 @@ static inline void
ensure_writable_pages(CPUMIPSState *env,
> int mmu_idx,
> uintptr_t retaddr)
> {
> -#if !defined(CONFIG_USER_ONLY)
> -target_ulong page_addr;
> +/* FIXME: Probe the actual accesses (pass and use a size) */
> if (unlikely(MSA_PAGESPAN(addr))) {
> /* first page */
> probe_write(env, addr, 0, mmu_idx, retaddr);
> /* second page */
> -page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> -probe_write(env, page_addr, 0, mmu_idx, retaddr);
> +addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> +probe_write(env, addr, 0, mmu_idx, retaddr);
> }
> -#endif
> }
>
> void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
> --
> 2.21.0
>
>
[Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
If there was a disabled command, then qemu-ga used to report
CommandDisabled error class (among with human readable
description). This changed in v1.2.0-rc0~28^2~16 in favor of
GenericError class. While the change might work for other
classes, this one should not have been dropped because it helps
callers distinguish the root cause of the error.
A bit of background: up until very recently libvirt used qemu-ga
in all or nothing way. It didn't care why a qemu-ga command
failed. But very recently a new API was introduced which
implements 'best effort' approach (in some cases) and thus
libvirt must differentiate between: {CommandNotFound,
CommandDisabled} and some generic error. While the former classes
mean the API can issue some other commands the latter raises a
red flag causing the API to fail.
This reverts df1e608a01 partially.
Signed-off-by: Michal Privoznik
---
include/qapi/error.h | 1 +
qapi/error.json | 4 +++-
qapi/qmp-dispatch.c | 5 +++--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/qapi/error.h b/include/qapi/error.h
index 3f95141a01..7116b86a92 100644
--- a/include/qapi/error.h
+++ b/include/qapi/error.h
@@ -129,6 +129,7 @@
typedef enum ErrorClass {
ERROR_CLASS_GENERIC_ERROR = QAPI_ERROR_CLASS_GENERICERROR,
ERROR_CLASS_COMMAND_NOT_FOUND = QAPI_ERROR_CLASS_COMMANDNOTFOUND,
+ERROR_CLASS_COMMAND_DISABLED = QAPI_ERROR_CLASS_COMMANDDISABLED,
ERROR_CLASS_DEVICE_NOT_ACTIVE = QAPI_ERROR_CLASS_DEVICENOTACTIVE,
ERROR_CLASS_DEVICE_NOT_FOUND = QAPI_ERROR_CLASS_DEVICENOTFOUND,
ERROR_CLASS_KVM_MISSING_CAP = QAPI_ERROR_CLASS_KVMMISSINGCAP,
diff --git a/qapi/error.json b/qapi/error.json
index 3fad08f506..334d481399 100644
--- a/qapi/error.json
+++ b/qapi/error.json
@@ -14,6 +14,8 @@
#
# @CommandNotFound: the requested command has not been found
#
+# @CommandDisabled: the requested command has been disabled
+#
# @DeviceNotActive: a device has failed to be become active
#
# @DeviceNotFound: the requested device has not been found
@@ -25,5 +27,5 @@
##
{ 'enum': 'QapiErrorClass',
# Keep this in sync with ErrorClass in error.h
- 'data': [ 'GenericError', 'CommandNotFound',
+ 'data': [ 'GenericError', 'CommandNotFound', 'CommandDisabled',
'DeviceNotActive', 'DeviceNotFound', 'KVMMissingCap' ] }
diff --git a/qapi/qmp-dispatch.c b/qapi/qmp-dispatch.c
index 3037d353a4..913b3363cb 100644
--- a/qapi/qmp-dispatch.c
+++ b/qapi/qmp-dispatch.c
@@ -104,8 +104,9 @@ static QObject *do_qmp_dispatch(QmpCommandList *cmds,
QObject *request,
return NULL;
}
if (!cmd->enabled) {
-error_setg(errp, "The command %s has been disabled for this instance",
- command);
+error_set(errp, ERROR_CLASS_COMMAND_DISABLED,
+ "The command %s has been disabled for this instance",
+ command);
return NULL;
}
if (oob && !(cmd->options & QCO_ALLOW_OOB)) {
--
2.21.0
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote:
> From: He Zhe
>
> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
> handling for libgcrypt.
Where are you seeing pkg-config files for libgcrypt ?
The upstream project has (frustratingly) been hostile to any proposal to
add pkg-config support saying people should stick with their custom
libgcrypt-config tool
https://dev.gnupg.org/T2037
Even if this is something added by some distro downstream, what is the
benefit in using it, compared with libgcrypt-confg which should already
work & is portable.
>
> Signed-off-by: He Zhe
> ---
> configure | 48
> 1 file changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/configure b/configure
> index e44e454..0f362a7 100755
> --- a/configure
> +++ b/configure
> @@ -2875,6 +2875,30 @@ has_libgcrypt() {
> return 0
> }
>
> +has_libgcrypt_pkgconfig() {
> +if ! has $pkg_config ; then
> +return 1
> +fi
> +
> +if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
> +return 1
> +fi
> +
> +if test -n "$cross_prefix" ; then
> +host=$($pkg_config --variable=host libgcrypt)
> +if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
> +print_error "host($host) does not match
> cross_prefix($cross_prefix)"
> +return 1
> +fi
> +fi
> +
> +if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
> +print_error "libgcrypt version is $($pkg_config --modversion
> libgcrypt)"
> +return 1
> +fi
> +
> +return 0
> +}
>
> if test "$nettle" != "no"; then
> pass="no"
> @@ -2902,7 +2926,14 @@ fi
>
> if test "$gcrypt" != "no"; then
> pass="no"
> -if has_libgcrypt; then
> +if has_libgcrypt_pkgconfig; then
> +gcrypt_cflags=$($pkg_config --cflags libgcrypt)
> +if test "$static" = "yes" ; then
> +gcrypt_libs=$($pkg_config --libs --static libgcrypt)
> +else
> +gcrypt_libs=$($pkg_config --libs libgcrypt)
> +fi
> +elif has_libgcrypt; then
> gcrypt_cflags=$(libgcrypt-config --cflags)
> gcrypt_libs=$(libgcrypt-config --libs)
> # Debian has removed -lgpg-error from libgcrypt-config
> @@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
> then
> gcrypt_libs="$gcrypt_libs -lgpg-error"
> fi
> +fi
>
> -# Link test to make sure the given libraries work (e.g for static).
> -write_c_skeleton
> -if compile_prog "" "$gcrypt_libs" ; then
> -LIBS="$gcrypt_libs $LIBS"
> -QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
> -pass="yes"
> -fi
> +# Link test to make sure the given libraries work (e.g for static).
> +write_c_skeleton
> +if compile_prog "" "$gcrypt_libs" ; then
> + LIBS="$gcrypt_libs $LIBS"
> + QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
> + pass="yes"
> fi
> +
> if test "$pass" = "yes"; then
> gcrypt="yes"
> cat > $TMPC << EOF
> --
> 2.7.4
>
Regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
[Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16
From: Aleksandar Markovic
Clean up handling of CP0 register 16.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-18-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 ++-
target/mips/translate.c | 60 -
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8ecfdb3..d6405ad 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -375,7 +375,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 238066f..4808640 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7246,36 +7246,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
-case 1:
+case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
-case 2:
+case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
-case 3:
+case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
-case 4:
+case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
-case 5:
+case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
-case 6:
+case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
-case 7:
+case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -7971,45 +7971,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 1:
+case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
-case 2:
+case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 3:
+case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 4:
+case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
-case 5:
+case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
-case 6:
+case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
-case 7:
+case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8718,36 +8718,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
[Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19
From: Aleksandar Markovic
Clean up handling of CP0 register 19.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-21-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 4
target/mips/translate.c | 64 -
2 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6ea111..b4866a5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -395,6 +395,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG19__WATCHHI11
#define CP0_REG19__WATCHHI22
#define CP0_REG19__WATCHHI33
+#define CP0_REG19__WATCHHI44
+#define CP0_REG19__WATCHHI55
+#define CP0_REG19__WATCHHI66
+#define CP0_REG19__WATCHHI77
/* CP0 Register 20 */
#define CP0_REG20__XCONTEXT0
/* CP0 Register 21 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a11e8d..6d617f4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7323,14 +7323,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8058,14 +8058,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8795,14 +8795,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -9512,14 +9512,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
--
2.7.4
[Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29
From: Aleksandar Markovic
Clean up handling of CP0 register 29.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-29-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 22 ++---
target/mips/translate.c | 64 -
2 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index de9e850..6defbea 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLoDataHiErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo1 DataHi KScratch
- * 3 TagLo1TagHi KScratch
- * 4 DataLo2 DataHi KScratch
- * 5 TagLo2TagHi KScratch
- * 6 DataLo3 DataHi KScratch
- * 7 TagLo3TagHi KScratch
+ * 2 DataLo1 DataHi1 KScratch
+ * 3 TagLo1TagHi1 KScratch
+ * 4 DataLo2 DataHi2 KScratch
+ * 5 TagLo2TagHi2 KScratch
+ * 6 DataLo3 DataHi3 KScratch
+ * 7 TagLo3TagHi3 KScratch
*
*/
#define CP0_REGISTER_00 0
@@ -436,8 +436,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
-#define CP0_REG29__IDATAHI 1
-#define CP0_REG29__DDATAHI 3
+#define CP0_REG29__TAGHI 0
+#define CP0_REG29__DATAHI 1
+#define CP0_REG29__TAGHI1 2
+#define CP0_REG29__DATAHI1 3
+#define CP0_REG29__TAGHI2 4
+#define CP0_REG29__DATAHI2 5
+#define CP0_REG29__TAGHI3 6
+#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC0
/* CP0 Register 31 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 032e3b0..6d6fda6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7501,17 +7501,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -8251,17 +8251,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -8979,17 +8979,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -9715,17 +9715,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-
[Qemu-devel] [PULL 0/3] Usb 20190829 patches
The following changes since commit 23919ddfd56135cad3cb468a8f54d5a595f024f4: Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20190827' into staging (2019-08-27 15:52:36 +0100) are available in the Git repository at: git://git.kraxel.org/qemu tags/usb-20190829-pull-request for you to fetch changes up to e4c1c64112565a9be50008e6f28dbc41b53da740: usb-mtp: add sanity checks on rootdir (2019-08-29 07:31:12 +0200) usb: bugfixes for xhci and mtp. Bandan Das (1): usb-mtp: add sanity checks on rootdir Ying Fang (1): xhci: Fix memory leak in xhci_address_slot fangying (1): xhci: Fix memory leak in xhci_kick_epctx hw/usb/dev-mtp.c | 38 -- hw/usb/hcd-xhci.c | 2 ++ 2 files changed, 26 insertions(+), 14 deletions(-) -- 2.18.1
[Qemu-devel] [PULL 2/3] xhci: Fix memory leak in xhci_kick_epctx
From: fangying
Address Sanitizer shows memory leak in xhci_kick_epctx hw/usb/hcd-xhci.c:1912.
A sglist is leaked when a packet is retired and returns USB_RET_NAK status.
The leak stack is as bellow:
Direct leak of 2688 byte(s) in 168 object(s) allocated from:
#0 0xae8b11db in __interceptor_malloc (/lib64/libasan.so.4+0xd31db)
#1 0xae5c9163 in g_malloc (/lib64/libglib-2.0.so.0+0x57163)
#2 0xbb6fb3f7 in qemu_sglist_init dma-helpers.c:43
#3 0xbba705a7 in pci_dma_sglist_init include/hw/pci/pci.h:837
#4 0xbba705a7 in xhci_xfer_create_sgl hw/usb/hcd-xhci.c:1443
#5 0xbba705a7 in xhci_setup_packet hw/usb/hcd-xhci.c:1615
#6 0xbba77a6f in xhci_kick_epctx hw/usb/hcd-xhci.c:1912
#7 0xbbdaad27 in timerlist_run_timers util/qemu-timer.c:592
#8 0xbbdab19f in qemu_clock_run_timers util/qemu-timer.c:606
#9 0xbbdab19f in qemu_clock_run_all_timers util/qemu-timer.c:692
#10 0xbbdab9a3 in main_loop_wait util/main-loop.c:524
#11 0xbb6ff5e7 in main_loop vl.c:1806
#12 0xbb1e1453 in main vl.c:4488
Signed-off-by: Ying Fang
Message-id: 20190828062535.1573-1-fangyi...@huawei.com
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-xhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 471759cd4cc0..80988bb305a1 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -1914,6 +1914,7 @@ static void xhci_kick_epctx(XHCIEPContext *epctx,
unsigned int streamid)
}
usb_handle_packet(xfer->packet.ep->dev, >packet);
if (xfer->packet.status == USB_RET_NAK) {
+xhci_xfer_unmap(xfer);
return;
}
xhci_try_complete_packet(xfer);
--
2.18.1
Re: [Qemu-devel] [PATCH v1 8/9] accel/stubs: reduce headers from tcg-stub
Alex Bennée writes:
> We don't need much for these. However I do wonder why these aren't
> just null inlines in exec-all.h
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
> ---
> accel/stubs/tcg-stub.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
> index e2d23edafe0..75b10ab54be 100644
> --- a/accel/stubs/tcg-stub.c
> +++ b/accel/stubs/tcg-stub.c
> @@ -11,10 +11,8 @@
> */
>
> #include "qemu/osdep.h"
> -#include "qemu-common.h"
> #include "cpu.h"
> #include "tcg/tcg.h"
> -#include "exec/exec-all.h"
>
> void tb_flush(CPUState *cpu)
> {
I'll drop this one as it doesn't merge build cleanly against master on
Travis (but oddly built on my machine).
--
Alex Bennée
Re: [Qemu-devel] Cryptic errors from PIP install if missing openssl-devel
Hi Cleber, Lukáš, On 8/29/19 11:24 AM, Philippe Mathieu-Daudé wrote: > On 8/29/19 5:27 AM, Cleber Rosa wrote: >> On Thu, Aug 29, 2019 at 11:51:17AM +1000, David Gibson wrote: [...] >>> Fwiw, I also get an equally cryptic error that I haven't figured out >>> the cause for on my 32-bit Fedora container environment: >>> >>> VENV/home/dwg/src/qemu/build/i386/tests/venv >>> PIP /home/dwg/src/qemu/tests/requirements.txt >>> Failed building wheel for bcrypt >>> Could not build wheels for bcrypt which use PEP 517 and cannot be installed >>> directly >>> You are using pip version 19.0.3, however version 19.2.3 is available. >>> You should consider upgrading via the 'pip install --upgrade pip' command. >>> >> >> This is certainly caused by pip not being able to install paramiko on >> those systems. I have dealt with paramiko (and its many dependencies) >> before on the avocado remote runner plugin (which is not being used >> here) and it was not fun. >> >> My personal goal was to rely on the ssh binary as an ssh client, which >> should be more ubiquitous, and with that I added a simple wrapper to >> Avocado: >> >> >> https://avocado-framework.readthedocs.io/en/71.0/api/utils/avocado.utils.html#module-avocado.utils.ssh > > I did not know this module. class avocado.utils.ssh.Session(address, credentials) Parameters: credentials (tuple) username and path to a key for authentication purposes The current test uses username + password. Can we use this credentials with the Avocado module? (The image used is prebuilt). >> I guess we should consider changing the (few) tests that require >> paramiko to use that module instead. > > Clean way to resolve this issue.
Re: [Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
On 29.08.2019 11:02, Chao Gao wrote:
> Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's
> perspective, assigned devices cannot be reset. But some devices rely on PCI
> reset to recover from hardware hangs. When being assigned to a VM, those
> devices cannot be reset and won't work any longer if a hardware hang occurs.
> We have to reboot VM to trigger PCI reset on host to recover the device.
Did you consider a hot-unplug, reset (by host), hot-plug cycle instead?
> +static int xen_pt_devctl_reg_write(XenPCIPassthroughState *s,
> + XenPTReg *cfg_entry, uint16_t *val,
> + uint16_t dev_value, uint16_t valid_mask)
> +{
> +if (s->real_device.is_resetable && (*val & PCI_EXP_DEVCTL_BCR_FLR)) {
> +xen_pt_reset(s);
> +}
> +return xen_pt_word_reg_write(s, cfg_entry, val, dev_value, valid_mask);
I think you also need to clear the bit before handing on the request,
such that reads will always observe it clear.
Jan
[Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24
From: Aleksandar Markovic
Clean up handling of CP0 register 24.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-24-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 610631f..515d04c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7406,7 +7406,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
@@ -8164,7 +8164,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8895,7 +8895,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -9634,7 +9634,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
--
2.7.4
[Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
From: He Zhe
libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
handling for libgcrypt.
Signed-off-by: He Zhe
---
configure | 48
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index e44e454..0f362a7 100755
--- a/configure
+++ b/configure
@@ -2875,6 +2875,30 @@ has_libgcrypt() {
return 0
}
+has_libgcrypt_pkgconfig() {
+if ! has $pkg_config ; then
+return 1
+fi
+
+if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
+return 1
+fi
+
+if test -n "$cross_prefix" ; then
+host=$($pkg_config --variable=host libgcrypt)
+if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
+print_error "host($host) does not match
cross_prefix($cross_prefix)"
+return 1
+fi
+fi
+
+if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
+print_error "libgcrypt version is $($pkg_config --modversion
libgcrypt)"
+return 1
+fi
+
+return 0
+}
if test "$nettle" != "no"; then
pass="no"
@@ -2902,7 +2926,14 @@ fi
if test "$gcrypt" != "no"; then
pass="no"
-if has_libgcrypt; then
+if has_libgcrypt_pkgconfig; then
+gcrypt_cflags=$($pkg_config --cflags libgcrypt)
+if test "$static" = "yes" ; then
+gcrypt_libs=$($pkg_config --libs --static libgcrypt)
+else
+gcrypt_libs=$($pkg_config --libs libgcrypt)
+fi
+elif has_libgcrypt; then
gcrypt_cflags=$(libgcrypt-config --cflags)
gcrypt_libs=$(libgcrypt-config --libs)
# Debian has removed -lgpg-error from libgcrypt-config
@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
then
gcrypt_libs="$gcrypt_libs -lgpg-error"
fi
+fi
-# Link test to make sure the given libraries work (e.g for static).
-write_c_skeleton
-if compile_prog "" "$gcrypt_libs" ; then
-LIBS="$gcrypt_libs $LIBS"
-QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
-pass="yes"
-fi
+# Link test to make sure the given libraries work (e.g for static).
+write_c_skeleton
+if compile_prog "" "$gcrypt_libs" ; then
+ LIBS="$gcrypt_libs $LIBS"
+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+ pass="yes"
fi
+
if test "$pass" = "yes"; then
gcrypt="yes"
cat > $TMPC << EOF
--
2.7.4
Re: [Qemu-devel] [Qemu-block] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
On Thu, Aug 29, 2019 at 12:05:19PM +0200, Philippe Mathieu-Daudé wrote: > This series update the git.orderfile to order Python and shell > scripts before unordered files. > This is particularly useful for changes in tests/qemu-iotests. > > Regards, > > Phil. > > Philippe Mathieu-Daudé (2): > scripts/git.orderfile: Order Python files before unordered ones > scripts/git.orderfile: Order shell scripts before unordered files > > scripts/git.orderfile | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Stefano Garzarella Thanks, Stefano
Re: [Qemu-devel] [Slirp] [PATCH 1/2] Do not reassemble fragments pointing outside of the original payload
+-- On Mon, 26 Aug 2019, Samuel Thibault wrote --+
| Philippe Mathieu-Daudé, le ven. 23 août 2019 17:15:32 +0200, a ecrit:
| > > Did you make your test with commit 126c04acbabd ("Fix heap overflow in
| > > ip_reass on big packet input") applied?
| >
| > Yes, unfortunately it doesn't fix the issue.
|
| Ok.
|
| Could you try the attached patch? There was a use-after-free. Without
| it, I can indeed crash qemu with the given exploit. With it I don't
| seem to be able to crash it (trying in a loop for several minutes).
Considering that earlier fix was released/pulled into upstream QEMU v4.1.0, we
need to treat this one as a separate issue.
commit c59279437eda91841b9d26079c70b8a540d41204
Author: Samuel Thibault
Date: Mon Aug 26 00:55:03 2019 +0200
ip_reass: Fix use after free
Using ip_deq after m_free might read pointers from an allocation reuse.
I'll follow-up on that.
Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
Hi Peter, On 8/29/19 3:18 AM, Peter Xu wrote: > On Wed, Aug 28, 2019 at 02:59:45PM +0200, Auger Eric wrote: >> Hi Peter, > > Hi, Eric, > > [...] > >> In >> [PATCH v4 2/5] memory: Add IOMMU_ATTR_HW_NESTED_PAGING IOMMU memory >> region attribute (https://patchwork.kernel.org/patch/11109701/) > > [1] > >> >> [PATCH v4 3/5] hw/vfio/common: Fail on VFIO/HW nested paging detection >> (https://patchwork.kernel.org/patch/11109697/) >> >> I proposed to introduce a new IOMMU MR attribute to retrieve whether the >> vIOMMU uses HW nested paging to integrate with VFIO. I wonder whether >> this kind of solution would fit your need too. >> >> Assuming we would rename the attribute (whose name is challenged by >> Peter anyway) into something like IOMMU_ATTR_PHYS_MAP_MODE >> taking the possible values: NONE, CM, HW_NESTED_PAGING. SMMUv3 would >> return HW_NESTED_PAGING, Intel IOMMU would return CM if CM is enabled or >> NONE in the negative. Then we could implement the check directly in VFIO >> common.c. That way I don't think you would need the new notifiers and >> this would satisfy both requirements? > > IMHO it'll suffer from the similar issue we have now with > flag_changed, because at the very beginning of x86 system boots DMAR > is not yet enabled, the intel-iommu device is using the same mode as > its passthrough mode so there's no IOMMU memory region at all in the > DMA address spaces of the devices. Ah OK I did not get this initially. We don't have this issue with SMMUv3 as the IOMMU MR exists from the very beginning and does not depend on its enablement by the guest. Also it stays there. So the detection can be made immediatly. Hence even with patch [1] above we > still can't really reach the get_attr() check until DMAR enabled? > > Maybe we can figure out a good way to expose IOMMU attributes rather > than the IOMMU memory region attributes then we let vfio to pick that > up, but I'm not very sure whether that's clean enough. > > Thanks, > Thanks Eric
[Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's
perspective, assigned devices cannot be reset. But some devices rely on PCI
reset to recover from hardware hangs. When being assigned to a VM, those
devices cannot be reset and won't work any longer if a hardware hang occurs.
We have to reboot VM to trigger PCI reset on host to recover the device.
This patch exposes FLR capability to VMs if the assigned device can be reset on
host. When VM initiates an FLR to a device, qemu cleans up the device state,
(including disabling of intx and/or MSI and unmapping BARs from guest, deleting
emulated registers), then initiate PCI reset through 'reset' knob under the
device's sysfs, finally initialize the device again.
Signed-off-by: Chao Gao
---
Do we need to introduce an attribute, like "permissive" to explicitly
enable FLR capability emulation? During PCI reset, interrupts and BARs are
unmapped from the guest. It seems that guest cannot interact with the device
directly except access to device's configuration space which is emulated by
qemu. If proper method can be used to prevent qemu accessing the physical
device there is no new security hole caused by the FLR emulation.
VM's FLR may be backed by any reset function on host to the physical device,
for example: FLR, D3softreset, secondary bus reset. Not sure it is fine to mix
them. Given Linux kernel just uses an unified API to reset device and caller
cannot choose a specific one, it might be OK.
---
hw/xen/xen-host-pci-device.c | 30 ++
hw/xen/xen-host-pci-device.h | 3 +++
hw/xen/xen_pt.c | 9 +
hw/xen/xen_pt.h | 1 +
hw/xen/xen_pt_config_init.c | 30 +++---
5 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/hw/xen/xen-host-pci-device.c b/hw/xen/xen-host-pci-device.c
index 1b44dcafaf..d549656f42 100644
--- a/hw/xen/xen-host-pci-device.c
+++ b/hw/xen/xen-host-pci-device.c
@@ -198,6 +198,35 @@ static bool xen_host_pci_dev_is_virtfn(XenHostPCIDevice *d)
return !stat(path, );
}
+static bool xen_host_pci_resetable(XenHostPCIDevice *d)
+{
+char path[PATH_MAX];
+
+xen_host_pci_sysfs_path(d, "reset", path, sizeof(path));
+
+return !access(path, W_OK);
+}
+
+void xen_host_pci_reset(XenHostPCIDevice *d)
+{
+char path[PATH_MAX];
+int fd;
+
+xen_host_pci_sysfs_path(d, "reset", path, sizeof(path));
+
+fd = open(path, O_WRONLY);
+if (fd == -1) {
+XEN_HOST_PCI_LOG("Xen host pci reset: open error\n");
+return;
+}
+
+if (write(fd, "1", 1) != 1) {
+XEN_HOST_PCI_LOG("Xen host pci reset: write error\n");
+}
+
+return;
+}
+
static void xen_host_pci_config_open(XenHostPCIDevice *d, Error **errp)
{
char path[PATH_MAX];
@@ -377,6 +406,7 @@ void xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t
domain,
d->class_code = v;
d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
+d->is_resetable = xen_host_pci_resetable(d);
return;
diff --git a/hw/xen/xen-host-pci-device.h b/hw/xen/xen-host-pci-device.h
index 4d8d34ecb0..cacf9b3df8 100644
--- a/hw/xen/xen-host-pci-device.h
+++ b/hw/xen/xen-host-pci-device.h
@@ -32,6 +32,7 @@ typedef struct XenHostPCIDevice {
XenHostPCIIORegion rom;
bool is_virtfn;
+bool is_resetable;
int config_fd;
} XenHostPCIDevice;
@@ -55,4 +56,6 @@ int xen_host_pci_set_block(XenHostPCIDevice *d, int pos,
uint8_t *buf,
int xen_host_pci_find_ext_cap_offset(XenHostPCIDevice *s, uint32_t cap);
+void xen_host_pci_reset(XenHostPCIDevice *d);
+
#endif /* XEN_HOST_PCI_DEVICE_H */
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index 8fbaf2eae9..d750367c0a 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -938,6 +938,15 @@ static void xen_pt_unregister_device(PCIDevice *d)
xen_pt_destroy(d);
}
+void xen_pt_reset(XenPCIPassthroughState *s)
+{
+PCIDevice *d = PCI_DEVICE(s);
+
+xen_pt_unregister_device(d);
+xen_host_pci_reset(>real_device);
+xen_pt_realize(d, NULL);
+}
+
static Property xen_pci_passthrough_properties[] = {
DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr),
DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false),
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
index 9167bbaf6d..ed05bc0d39 100644
--- a/hw/xen/xen_pt.h
+++ b/hw/xen/xen_pt.h
@@ -332,4 +332,5 @@ int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
Error **errp);
+void xen_pt_reset(XenPCIPassthroughState *s);
#endif /* XEN_PT_H */
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index 31ec5add1d..435abd7286 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -852,6 +852,30 @@ static inline uint8_t
get_device_type(XenPCIPassthroughState *s,
return (flag &
[Qemu-devel] [PATCH v3] job: drop job_drain
In job_finish_sync job_enter should be enough for a job to make some
progress and draining is a wrong tool for it. So use job_enter directly
here and drop job_drain with all related staff not used more.
Suggested-by: Kevin Wolf
Signed-off-by: Vladimir Sementsov-Ogievskiy
Tested-by: John Snow
Reviewed-by: John Snow
---
v3: rebase on master
drop drain from test_simple_job_driver too
add John's r-b and t-b
include/block/blockjob_int.h | 19 ---
include/qemu/job.h | 13 -
block/backup.c | 19 +--
block/commit.c | 1 -
block/mirror.c | 28 +++-
block/stream.c | 1 -
blockjob.c | 13 -
job.c| 12 +---
tests/test-bdrv-drain.c | 3 ---
tests/test-block-iothread.c | 1 -
tests/test-blockjob-txn.c| 1 -
tests/test-blockjob.c| 2 --
12 files changed, 5 insertions(+), 108 deletions(-)
diff --git a/include/block/blockjob_int.h b/include/block/blockjob_int.h
index e4a318dd15..e2824a36a8 100644
--- a/include/block/blockjob_int.h
+++ b/include/block/blockjob_int.h
@@ -52,17 +52,6 @@ struct BlockJobDriver {
* besides job->blk to the new AioContext.
*/
void (*attached_aio_context)(BlockJob *job, AioContext *new_context);
-
-/*
- * If the callback is not NULL, it will be invoked when the job has to be
- * synchronously cancelled or completed; it should drain BlockDriverStates
- * as required to ensure progress.
- *
- * Block jobs must use the default implementation for job_driver.drain,
- * which will in turn call this callback after doing generic block job
- * stuff.
- */
-void (*drain)(BlockJob *job);
};
/**
@@ -107,14 +96,6 @@ void block_job_free(Job *job);
*/
void block_job_user_resume(Job *job);
-/**
- * block_job_drain:
- * Callback to be used for JobDriver.drain in all block jobs. Drains the main
- * block node associated with the block jobs and calls BlockJobDriver.drain for
- * job-specific actions.
- */
-void block_job_drain(Job *job);
-
/**
* block_job_ratelimit_get_delay:
*
diff --git a/include/qemu/job.h b/include/qemu/job.h
index 73c67d3175..bd59cd8944 100644
--- a/include/qemu/job.h
+++ b/include/qemu/job.h
@@ -220,13 +220,6 @@ struct JobDriver {
*/
void (*complete)(Job *job, Error **errp);
-/*
- * If the callback is not NULL, it will be invoked when the job has to be
- * synchronously cancelled or completed; it should drain any activities
- * as required to ensure progress.
- */
-void (*drain)(Job *job);
-
/**
* If the callback is not NULL, prepare will be invoked when all the jobs
* belonging to the same transaction complete; or upon this job's
completion
@@ -470,12 +463,6 @@ bool job_user_paused(Job *job);
*/
void job_user_resume(Job *job, Error **errp);
-/*
- * Drain any activities as required to ensure progress. This can be called in a
- * loop to synchronously complete a job.
- */
-void job_drain(Job *job);
-
/**
* Get the next element from the list of block jobs after @job, or the
* first one if @job is %NULL.
diff --git a/block/backup.c b/block/backup.c
index 2baf7bed65..2a81ed3d74 100644
--- a/block/backup.c
+++ b/block/backup.c
@@ -425,21 +425,6 @@ void backup_do_checkpoint(BlockJob *job, Error **errp)
bdrv_set_dirty_bitmap(backup_job->copy_bitmap, 0, backup_job->len);
}
-static void backup_drain(BlockJob *job)
-{
-BackupBlockJob *s = container_of(job, BackupBlockJob, common);
-
-/* Need to keep a reference in case blk_drain triggers execution
- * of backup_complete...
- */
-if (s->target) {
-BlockBackend *target = s->target;
-blk_ref(target);
-blk_drain(target);
-blk_unref(target);
-}
-}
-
static BlockErrorAction backup_error_action(BackupBlockJob *job,
bool read, int error)
{
@@ -588,13 +573,11 @@ static const BlockJobDriver backup_job_driver = {
.job_type = JOB_TYPE_BACKUP,
.free = block_job_free,
.user_resume= block_job_user_resume,
-.drain = block_job_drain,
.run= backup_run,
.commit = backup_commit,
.abort = backup_abort,
.clean = backup_clean,
-},
-.drain = backup_drain,
+}
};
static int64_t backup_calculate_cluster_size(BlockDriverState *target,
diff --git a/block/commit.c b/block/commit.c
index 408ae15389..bc8454463d 100644
--- a/block/commit.c
+++ b/block/commit.c
@@ -216,7 +216,6 @@ static const BlockJobDriver commit_job_driver = {
.job_type = JOB_TYPE_COMMIT,
.free = block_job_free,
.user_resume = block_job_user_resume,
-.drain
[Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15
From: Aleksandar Markovic
Clean up handling of CP0 register 15.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-17-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2a9c6d5..8ecfdb3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -367,6 +367,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index efedced..238066f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7223,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
-case 3:
+case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -7956,11 +7956,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8697,16 +8697,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
-case 3:
+case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9419,11 +9419,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
Re: [Qemu-devel] [PATCH v6 1/6] iotests: allow Valgrind checking all QEMU processes
On 29/08/2019 03:30, Eric Blake wrote:
> On 8/28/19 5:58 PM, John Snow wrote:
>
>>> +++ b/tests/qemu-iotests/common.rc
>>> @@ -60,61 +60,132 @@ if ! . ./common.config
>>> exit 1
>>> fi
>>>
>>> +# Unset the variables to turn Valgrind off for specific processes, e.g.
>
> That's not unsetting, that's setting to the empty string.
>
Thanks Eric, I will make the correction of the comment. Any string other
than "y", including the empty one, fits.
>>> +# $ VALGRIND_QEMU_IO= ./check -qcow2 -valgrind 015
>>> +
>>> +: ${VALGRIND_QEMU_VM='y'}
>>> +: ${VALGRIND_QEMU_IMG='y'}
>>> +: ${VALGRIND_QEMU_IO='y'}
>>> +: ${VALGRIND_QEMU_NBD='y'}
>>> +: ${VALGRIND_QEMU_VXHS='y'}
>>> +
>>
I am going to make the change:
: ${VALGRIND_QEMU_VM=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_IMG=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_IO=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_NBD=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_VXHS=$VALGRIND_QEMU}
and get rid of the local VALGRIND_ON="${VALGRIND_QEMU}"
so that the code will be optimized.
>> I have to admit to you that I'm not familiar with this trick. I'm
>> looking it up and I see := documented, but not = alone.
>
> It's been a repeated complaint to the bash developer that the manual is
> doing a disservice to its users by not documenting ${var=val} in an
> easily searchable form. It IS documented, but only by virtue of
> ${var:=val} occurring under a section header that states:
>
> When not performing substring expansion, using the forms
> documented
> below (e.g., :-), bash tests for a parameter that is unset or
> null.
> Omitting the colon results in a test only for a parameter
> that is
> unset.
>
> So the choice is whether you want to special case a variable set to an
> empty string the same as an unset variable, or the same as a variable
> with a non-empty value.
>
Thank you all for your reviews and comments. The purpose why I omitted
the colon is to allow a user writing the shorter command syntax like
$ VALGRIND_QEMU_IO= ./check -valgrind
rather than
$ VALGRIND_QEMU_IO=" 'no' or 'off' or else anything other than 'y' "
./check -valgrind
so, no need to strike the Shift key twice and guess at what else is
acceptable to type )))
The variable default value 'y' looks good to me to implement the new
functionality that is compatible with the existing one when we just set
the '-valgrind' switch. The general idea behind using the Valgrind is to
make a careful search for memory issues. Once found, a user can tune the
particular test with extra variables to save their development/testing
time as John suggested. Also, no need to specify all the five long name
variables each time a user writes the command if default values aren't set.
I am flexible to make a change that is good for all. So, what solution
will we come to?
Andrey
>>
>> It doesn't seem documented here at all:
>> https://www.gnu.org/software/bash/manual/html_node/Shell-Parameter-Expansion.html
>>
>> I see it here, though:
>> https://www.tldp.org/LDP/abs/html/parameter-substitution.html
>>
>> And it seems to work, but I'm not sure if this works with BSD or OSX's
>> sh. I see Eric comment on that compatibility a lot, so maybe I'll let
>> him chime in.
>
> It's quite portable; POSIX requires it, and autoconf relies on it.
>
--
With the best regards,
Andrey Shinkevich
[Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31
From: Aleksandar Markovic
Clean up handling of CP0 register 31.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-31-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 56 -
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6defbea..ca00f41 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -613,7 +613,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
-target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@@ -1024,6 +1023,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
+target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 93f7a20..f6d1424 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7532,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9009,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9746,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
--
2.7.4
Re: [Qemu-devel] [PATCH v8 01/37] target/mips: Add support for DSPRAM
Hi Aleksandar,
On 8/19/19 2:07 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch
> pad RAM
> used for temporary storage of data. The DSPRAM provides a connection to
> on-chip
> memory or memory-mapped registers, which are accessed in parallel with the L1
> data
> cache to minimize access latency
Can you point me to a vm/kernel image using this feature?
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/mips/cps.c| 29 +++-
> hw/misc/Makefile.objs| 1 +
> hw/misc/mips_dspram.c| 153
> +++
> include/hw/mips/cps.h| 2 +
> include/hw/misc/mips_dspram.h| 46
> target/mips/cpu.h| 9 ++-
> target/mips/internal.h | 3 +-
I suggest you to install scripts/git.orderfile, having files ordered
eases reviews.
> target/mips/op_helper.c | 18 +
> target/mips/translate.c | 8 ++
> target/mips/translate_init.inc.c | 2 +
> 10 files changed, 266 insertions(+), 5 deletions(-)
> create mode 100644 hw/misc/mips_dspram.c
> create mode 100644 include/hw/misc/mips_dspram.h
>
> diff --git a/hw/mips/cps.c b/hw/mips/cps.c
> index 0d459c4..c84bc64 100644
> --- a/hw/mips/cps.c
> +++ b/hw/mips/cps.c
> @@ -18,6 +18,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "qemu/module.h"
> #include "hw/mips/cps.h"
> @@ -91,7 +92,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
>
> cpu = MIPS_CPU(first_cpu);
> env = >env;
> -saar_present = (bool)env->saarp;
> +saar_present = env->saarp;
> +bool dspram_present = env->dspramp;
>
> /* Inter-Thread Communication Unit */
> if (itu_present) {
> @@ -102,7 +104,8 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
> object_property_set_bool(OBJECT(>itu), saar_present,
> "saar-present",
> );
> if (saar_present) {
> -qdev_prop_set_ptr(DEVICE(>itu), "saar", (void
> *)>CP0_SAAR);
> +qdev_prop_set_ptr(DEVICE(>itu), "saar",
> + (void *) >CP0_SAAR[0]);
> }
> object_property_set_bool(OBJECT(>itu), true, "realized", );
> if (err != NULL) {
> @@ -113,6 +116,28 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
> memory_region_add_subregion(>container, 0,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(>itu),
> 0));
> }
> +env->dspram = g_new0(MIPSDSPRAMState, 1);
Why not allocated this only if dspram_present?
> +
> +/* Data Scratch Pad RAM */
> +if (dspram_present) {
> +if (!saar_present) {
> +error_report("%s: DSPRAM requires SAAR registers", __func__);
> +return;
> +}
> +object_initialize(>dspram, sizeof(MIPSDSPRAMState),
> + TYPE_MIPS_DSPRAM);
> +qdev_set_parent_bus(DEVICE(>dspram), sysbus_get_default());
> +qdev_prop_set_ptr(DEVICE(>dspram), "saar",
> + >CP0_SAAR[1]);
> +object_property_set_bool(OBJECT(>dspram), true, "realized", );
> +if (err != NULL) {
> +error_report("%s: DSPRAM initialisation failed", __func__);
> +error_propagate(errp, err);
> +return;
> +}
> +memory_region_add_subregion(>container, 0,
> +sysbus_mmio_get_region(SYS_BUS_DEVICE(>dspram), 0));
> +}
>
> /* Cluster Power Controller */
> sysbus_init_child_obj(OBJECT(dev), "cpc", >cpc, sizeof(s->cpc),
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index e9aab51..5fcb4db 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
> obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
> obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
> obj-$(CONFIG_MIPS_ITU) += mips_itu.o
> +obj-$(CONFIG_MIPS_DSPRAM) += mips_dspram.o
> obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
> obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
>
> diff --git a/hw/misc/mips_dspram.c b/hw/misc/mips_dspram.c
> new file mode 100644
> index 000..9bc155b
> --- /dev/null
> +++ b/hw/misc/mips_dspram.c
> @@ -0,0 +1,153 @@
> +/*
> + * Data Scratch Pad RAM
> + *
> + * Copyright (c) 2017 Imagination Technologies
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Re: [Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
Michal Privoznik writes:
> If there was a disabled command, then qemu-ga used to report
> CommandDisabled error class (among with human readable
> description). This changed in v1.2.0-rc0~28^2~16 in favor of
> GenericError class.
Really? I believe it was slightly earlier in the same series:
93b91c59db qemu-ga: switch to the new error format on the wire
de253f1491 qmp: switch to the new error format on the wire
The commit you mention (df1e608a01e) is merely follow-up simplification.
> While the change might work for other
> classes, this one should not have been dropped because it helps
> callers distinguish the root cause of the error.
>
> A bit of background: up until very recently libvirt used qemu-ga
> in all or nothing way. It didn't care why a qemu-ga command
> failed. But very recently a new API was introduced which
> implements 'best effort' approach (in some cases) and thus
> libvirt must differentiate between: {CommandNotFound,
> CommandDisabled} and some generic error. While the former classes
> mean the API can issue some other commands the latter raises a
> red flag causing the API to fail.
Why do you need to distinguish CommandNotFound from CommandDisabled?
> This reverts df1e608a01 partially.
>
> Signed-off-by: Michal Privoznik
Re: [Qemu-devel] [PATCH v1 0/2] Add live migration support in the PVRDMA device
On Wed, Aug 28, 2019 at 07:53:26PM +0530, Sukrit Bhatnagar wrote: > This series enables the migration of various GIDs used by the device. > This is in addition to the successful migration of PCI and MSIX states > as well as various DMA addresses and ring page information. > > We have a setup having two hosts and two VMs running atop them. > Migrations are performed over the local network. > > We also have performed various ping-pong tests (ibv_rc_pingpong) in the > guest(s) after adding GID migration support and this is the current status: > > - ping-pong to localhost succeeds, when performed before starting the > migration and after the completion of migration. > - ping-pong to a peer succeeds, both before and after migration as above, > provided that both VMs are running on/migrated to the same host. > So, if two VMs were started on two different hosts, and one of them > was migrated to the other host, the ping-pong was successful. This limitation looks to me like wrongly configured network. This patch-set should enable any migration. After our last meeting, please confirm. In addition, i don't see why non-VM peer (i.e. Bare-metal) is not supported. Can you run a test and update with the results? > Similarly, if two VMs are migrated to the same host, then after migration, > > the ping-pong was successful. > - ping-pong to a peer on the remote host is not working as of now. > > Our next goal is to achieve successful migration with live traffic. > > This is the same as the RFC v3 series posted earlier: > https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg04752.html > https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg04753.html > https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg04754.html > > > Sukrit Bhatnagar (2): > hw/pvrdma: make DSR mapping idempotent in load_dsr() > hw/pvrdma: add live migration support > > hw/rdma/vmw/pvrdma_main.c | 94 +++ > 1 file changed, 86 insertions(+), 8 deletions(-) > > -- > 2.21.0 > >
Re: [Qemu-devel] [PATCH for-4.2 v10 05/15] virtio-iommu: Add the iommu regions
Hi Peter,
On 8/16/19 6:00 AM, Peter Xu wrote:
> On Tue, Jul 30, 2019 at 07:21:27PM +0200, Eric Auger wrote:
>
> [...]
>
>> static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t
>> *config_data)
>> {
>> VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev);
>> @@ -266,6 +333,15 @@ static void virtio_iommu_device_realize(DeviceState
>> *dev, Error **errp)
>> virtio_add_feature(>features, VIRTIO_IOMMU_F_MAP_UNMAP);
>> virtio_add_feature(>features, VIRTIO_IOMMU_F_BYPASS);
>> virtio_add_feature(>features, VIRTIO_IOMMU_F_MMIO);
>> +
>> +memset(s->as_by_bus_num, 0, sizeof(s->as_by_bus_num));
>> +s->as_by_busptr = g_hash_table_new(NULL, NULL);
>
> VT-d was using g_hash_table_new_full() so that potentially VTDBus can
> still be freed. Here for IOMMUPCIBus allocated in
> virtio_iommu_find_add_as() I think it'll be leaked if we remove
> entries in the hash table?
>
> So I started to wonder whether PCI/PCIe buses are allowed to be
> plugged/unplugged after all because I never tried. With latest
> 5.3.0-rc4 guest I gave it a shot and I see the error below. It could
> be something that I did wrong or it could be simply that it's not
> working at all. Have you tried anything like that? Michael/Alex?
I have never tried this on my end.
However looking at docs/pcie_pci_bridge.txt it seems possible to hotplug
a pcie_pci_bridge downstream to a pcie-root-port under specific
conditions (see limitations section). So I guess the situation you
describe may happen. I switched to _full version.
Thanks
Eric
>
> bin=x86_64-softmmu/qemu-system-x86_64
> $bin -M q35,accel=kvm,kernel-irqchip=on -smp 8 -m 2G -cpu host \
> -monitor telnet::,server,nowait -nographic \
> -device e1000,netdev=net0 \
> -netdev user,id=net0,hostfwd=tcp::-:22 \
> -device pcie-pci-bridge,bus=pcie.0,id=pci.1 \
> -drive file=/images/default.qcow2,if=none,cache=none,id=drive0 \
> -device virtio-blk,drive=drive0
>
> (qemu) device_add pci-bridge,bus=pci.1,id=pci.2,chassis_nr=1,addr=1.0
>
> [ 66.172352] pci :01:01.0: [1b36:0001] type 01 class 0x060400
> [ 66.176897] pci :01:01.0: reg 0x10: [mem 0x-0x00ff 64bit]
> [ 66.186130] pci :01:01.0: No bus number available for hot-added bridge
> [ 66.189489] shpchp :00:03.0: BAR 14: assigned [mem
> 0x8000-0x800f]
> [ 66.193235] pci :01:01.0: BAR 0: assigned [mem 0x8000-0x80ff
> 64bit]
> [ 66.198587] shpchp :00:03.0: PCI bridge to [bus 01]
> [ 66.204113] shpchp :00:03.0: bridge window [mem
> 0x8000-0x800f]
> [ 66.215212] shpchp :01:01.0: HPC vendor_id 1b36 device_id 1 ss_vid 0
> ss_did 0
> [ 66.218531] shpchp :01:01.0: enabling device ( -> 0002)
> [ 66.229204] BUG: kernel NULL pointer dereference, address: 00e2
> [ 66.232124] #PF: supervisor write access in kernel mode
> [ 66.234369] #PF: error_code(0x0002) - not-present page
> [ 66.236585] PGD 0 P4D 0
> [ 66.237431] Oops: 0002 [#1] SMP PTI
> [ 66.238617] CPU: 2 PID: 277 Comm: kworker/2:1 Kdump: loaded Not tainted
> 5.3.0-rc4 #85
> [ 66.241200] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS
> rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.org 04/01/2014
> [ 66.244916] Workqueue: shpchp-1 shpchp_pushbutton_thread
> [ 66.246583] RIP: 0010:shpc_init.cold+0x5c3/0x8a1
> [ 66.248041] Code: 24 90 01 00 00 8b 49 08 40 80 fe 02 0f 85 f4 01 00 00 f7
> c1 00 00 00 f0 0f 84 b2 01 00 00 b9 13 00 00 00 80 3d 33 40 38 02 00 <88> 8a
> e26
> [ 66.253771] RSP: 0018:c925bb68 EFLAGS: 00010246
> [ 66.255418] RAX: 00ff RBX: RCX:
>
> [ 66.257763] RDX: RSI: 826bcd01 RDI:
> 826bcd60
> [ 66.260065] RBP: R08: 0001 R09:
>
> [ 66.263184] R10: 0005 R11: R12:
> 888032425400
> [ 66.265706] R13: c917109c R14: 888033da7000 R15:
> 001f
> [ 66.268200] FS: () GS:88807fc8()
> knlGS:
> [ 66.270826] CS: 0010 DS: ES: CR0: 80050033
> [ 66.272731] CR2: 00e2 CR3: 33afc002 CR4:
> 00360ee0
> [ 66.275373] DR0: DR1: DR2:
>
> [ 66.277947] DR3: DR6: fffe0ff0 DR7:
> 0400
> [ 66.279965] Call Trace:
> [ 66.280627] shpc_probe+0x91/0x32b
> [ 66.281644] local_pci_probe+0x42/0x80
> [ 66.282752] pci_device_probe+0x107/0x1a0
> [ 66.283877] really_probe+0xf0/0x380
> [ 66.284862] driver_probe_device+0x59/0xd0
> [ 66.285988] ? driver_allows_async_probing+0x50/0x50
> [ 66.287937] bus_for_each_drv+0x7e/0xc0
> [ 66.289752] __device_attach+0xe1/0x160
> [ 66.292076] pci_bus_add_device+0x4b/0x70
> [ 66.295244] pci_bus_add_devices+0x2c/0x64
> [ 66.297429] shpchp_configure_device+0xc1/0xe0
> [
Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
On 2019/8/29 上午4:43, Richard Henderson wrote: On 8/28/19 11:54 AM, Richard Henderson wrote: But it might be reasonable to include (VSTART == 0 && VL == VLMAX) as a single bit. BTW, it is reasonable to check VSTART == 0 always. Quoting the spec: # Implementations are permitted to raise illegal instruction exceptions # when attempting to execute a vector instruction with a value of vstart # that the implementation can never produce when executing that same # instruction with the same vtype setting. Since qemu will never interrupt a single instruction, each vector instruction will always run to completion, which clears VSTART. Since QEMU will never produce a non-zero value of VSTART, it is allowed to trap on any non-zero setting of VSTART. I.e. it can be handled at translation time alongside VILL. Hi, Richard I am so sorry for the inconvenience. It is very kind of you to review the horrible long code and give so many comments. Even in qemu, it may be some situations that VSTART != 0. For example, a load instruction leads to a page fault exception in a middle position. If VSTART == 0, some elements that had been loaded before the exception will be loaded once again. Specially, it may be a mistake if the instruction restores execution with VSTART== 0. When lmul == 1, "vlb v0 ,(a0), v0.t" As v0 is the mask register, if it is modified, some part of it can't be used again. It will take some time to address the other comments. After that I will split the patch into patch set with a cover letter in V2. Thank you again for your review! Best Regards, Zhiwei r~
Re: [Qemu-devel] [PATCH v6 1/3] target/ppc: Optimize emulation of vpkpx instruction
On 27.8.19. 20:52, Richard Henderson wrote:
On 8/27/19 2:37 AM, Stefan Brankovic wrote:
+for (i = 0; i < 4; i++) {
+switch (i) {
+case 0:
+/*
+ * Get high doubleword of vA to perfrom 6-5-5 pack of pixels
+ * 1 and 2.
+ */
+get_avr64(avr, VA, true);
+tcg_gen_movi_i64(result, 0x0ULL);
+break;
+case 1:
+/*
+ * Get low doubleword of vA to perfrom 6-5-5 pack of pixels
+ * 3 and 4.
+ */
+get_avr64(avr, VA, false);
+break;
+case 2:
+/*
+ * Get high doubleword of vB to perfrom 6-5-5 pack of pixels
+ * 5 and 6.
+ */
+get_avr64(avr, VB, true);
+tcg_gen_movi_i64(result, 0x0ULL);
+break;
+case 3:
+/*
+ * Get low doubleword of vB to perfrom 6-5-5 pack of pixels
+ * 7 and 8.
+ */
+get_avr64(avr, VB, false);
+break;
+}
+/* Perform the packing for 2 pixels(each iteration for 1). */
+tcg_gen_movi_i64(tmp, 0x0ULL);
+for (j = 0; j < 2; j++) {
+tcg_gen_shri_i64(shifted, avr, (j * 16 + 3));
+tcg_gen_andi_i64(shifted, shifted, mask1 << (j * 16));
+tcg_gen_or_i64(tmp, tmp, shifted);
+
+tcg_gen_shri_i64(shifted, avr, (j * 16 + 6));
+tcg_gen_andi_i64(shifted, shifted, mask2 << (j * 16));
+tcg_gen_or_i64(tmp, tmp, shifted);
+
+tcg_gen_shri_i64(shifted, avr, (j * 16 + 9));
+tcg_gen_andi_i64(shifted, shifted, mask3 << (j * 16));
+tcg_gen_or_i64(tmp, tmp, shifted);
+}
+if ((i == 0) || (i == 2)) {
+tcg_gen_shli_i64(tmp, tmp, 32);
+}
+tcg_gen_or_i64(result, result, tmp);
+if (i == 1) {
+/* Place packed pixels 1:4 to high doubleword of vD. */
+tcg_gen_mov_i64(result1, result);
+}
+if (i == 3) {
+/* Place packed pixels 5:8 to low doubleword of vD. */
+tcg_gen_mov_i64(result2, result);
+}
+}
+set_avr64(VT, result1, true);
+set_avr64(VT, result2, false);
I really have a hard time believing that it is worthwhile to inline all of this
code. By my count this is 82 non-move opcodes. That is a *lot* of inline
expansion.
However, I can well imagine that the existing out-of-line helper is less than
optimal.
-void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
-{
-int i, j;
-ppc_avr_t result;
-#if defined(HOST_WORDS_BIGENDIAN)
-const ppc_avr_t *x[2] = { a, b };
-#else
-const ppc_avr_t *x[2] = { b, a };
-#endif
-
-VECTOR_FOR_INORDER_I(i, u64) {
-VECTOR_FOR_INORDER_I(j, u32) {
-uint32_t e = x[i]->u32[j];
Double indirect loads?
-
-result.u16[4 * i + j] = (((e >> 9) & 0xfc00) |
- ((e >> 6) & 0x3e0) |
- ((e >> 3) & 0x1f));
Store to temporary ...
-}
-}
-*r = result;
... and then copy?
Try replacing the existing helper with something like the following.
r~
static inline uint64_t pkpx_1(uint64_t a, int shr, int shl)
{
uint64_t r;
r = ((a >> (shr + 9)) & 0x3f) << shl;
r |= ((a >> (shr + 6)) & 0x1f) << shl;
r |= ((a >> (shr + 3)) & 0x1f) << shl;
return r;
}
static inline uint64_t pkpx_2(uint64_t ah, uint64_t al)
{
return pkpx_1(ah, 32, 48)
| pkpx_1(ah, 0, 32)
| pkpx_1(al, 32, 16)
| pkpx_1(al, 0, 0);
}
void helper_vpkpx(uint64_t *r, uint64_t *a, uint64_t *b)
{
uint64_t rh = pkpx_2(a->VsrD(0), a->VsrD(1));
uint64_t rl = pkpx_2(b->VsrD(0), b->VsrD(1));
r->VsrD(0) = rh;
r->VsrD(1) = rl;
}
I implemented vpkpx as you suggested above with small modifications(so
it builds and gives correct result). It looks like this:
static inline uint64_t pkpx_1(uint64_t a, int shr, int shl)
{
uint64_t r;
r = ((a >> (shr + 9)) & 0xfc00) << shl;
r |= ((a >> (shr + 6)) & 0x3e0) << shl;
r |= ((a >> (shr + 3)) & 0x1f) << shl;
return r;
}
static inline uint64_t pkpx_2(uint64_t ah, uint64_t al)
{
return pkpx_1(ah, 32, 48)
| pkpx_1(ah, 0, 32)
| pkpx_1(al, 32, 16)
| pkpx_1(al, 0, 0);
}
void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
uint64_t rh = pkpx_2(a->u64[1], a->u64[0]);
uint64_t rl = pkpx_2(b->u64[1], b->u64[0]);
r->u64[1] = rh;
r->u64[0] = rl;
}
I also noticed that this would work only for little_endian hosts, so we
would need to modify it in order to support big_endian hosts (this
shouldn't affect performance results).
Then I run my performance tests and I got following results(test is
calling vpkpx 10 times):
1) Current helper implementation: ~ 157 ms
2) helper implementation you suggested: ~94 ms
[Qemu-devel] [PATCH] tests/docker: upgrade docker.py to python3
The recent podman changes (9459f754134bb) imported enum which is part
of the python3 standard library but only available as an external
library for python2. This causes problems on the fairly restricted
environment such as shippable. Lets bite the bullet and make the
script a fully python3 one. To that end:
- drop the from __future__ import (we are there now ;-)
- avoid the StringIO import hack
- be consistent with the mode we read/write dockerfiles
- s/iteritems/items/
- ensure check_output returns strings for processing
Signed-off-by: Alex Bennée
Cc: Marc-André Lureau
---
tests/docker/docker.py | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/tests/docker/docker.py b/tests/docker/docker.py
index ac5baab4cad..4bba29e104e 100755
--- a/tests/docker/docker.py
+++ b/tests/docker/docker.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2
+#!/usr/bin/env python3
#
# Docker controlling module
#
@@ -11,7 +11,6 @@
# or (at your option) any later version. See the COPYING file in
# the top-level directory.
-from __future__ import print_function
import os
import sys
import subprocess
@@ -25,10 +24,7 @@ import tempfile
import re
import signal
from tarfile import TarFile, TarInfo
-try:
-from StringIO import StringIO
-except ImportError:
-from io import StringIO
+from io import StringIO
from shutil import copy, rmtree
from pwd import getpwuid
from datetime import datetime, timedelta
@@ -62,11 +58,13 @@ USE_ENGINE = EngineEnum.AUTO
def _text_checksum(text):
"""Calculate a digest string unique to the text content"""
-return hashlib.sha1(text).hexdigest()
+return hashlib.sha1(text.encode('utf-8')).hexdigest()
+def _read_dockerfile(path):
+return open(path, 'rt', encoding='utf-8').read()
def _file_checksum(filename):
-return _text_checksum(open(filename, 'rb').read())
+return _text_checksum(_read_dockerfile(filename))
def _guess_engine_command():
@@ -192,7 +190,7 @@ def _read_qemu_dockerfile(img_name):
df = os.path.join(os.path.dirname(__file__), "dockerfiles",
img_name + ".docker")
-return open(df, "r").read()
+return _read_dockerfile(df)
def _dockerfile_preprocess(df):
@@ -262,6 +260,7 @@ class Docker(object):
def _output(self, cmd, **kwargs):
return subprocess.check_output(self._command + cmd,
stderr=subprocess.STDOUT,
+ encoding='utf-8',
**kwargs)
def inspect_tag(self, tag):
@@ -283,7 +282,9 @@ class Docker(object):
if argv is None:
argv = []
-tmp_df = tempfile.NamedTemporaryFile(dir=docker_dir, suffix=".docker")
+tmp_df = tempfile.NamedTemporaryFile(mode="w+t",
+ encoding='utf-8',
+ dir=docker_dir, suffix=".docker")
tmp_df.write(dockerfile)
if user:
@@ -396,7 +397,7 @@ class BuildCommand(SubCommand):
help="Dockerfile name")
def run(self, args, argv):
-dockerfile = open(args.dockerfile, "rb").read()
+dockerfile = _read_dockerfile(args.dockerfile)
tag = args.tag
dkr = Docker()
@@ -442,7 +443,7 @@ class BuildCommand(SubCommand):
cksum += [(filename, _file_checksum(filename))]
argv += ["--build-arg=" + k.lower() + "=" + v
- for k, v in os.environ.iteritems()
+ for k, v in os.environ.items()
if k.lower() in FILTERED_ENV_NAMES]
dkr.build_image(tag, docker_dir, dockerfile,
quiet=args.quiet, user=args.user, argv=argv,
@@ -611,7 +612,7 @@ class CheckCommand(SubCommand):
print("Need a dockerfile for tag:%s" % (tag))
return 1
-dockerfile = open(args.dockerfile, "rb").read()
+dockerfile = _read_dockerfile(args.dockerfile)
if dkr.image_matches_dockerfile(tag, dockerfile):
if not args.quiet:
--
2.20.1
Re: [Qemu-devel] [PATCH 2/2] qapi: deprecate implicit filters
On Wed, Aug 28, 2019 at 13:48:10 -0400, John Snow wrote:
> (Peter: search for "pkrempa" down below.)
>
> On 8/28/19 5:20 AM, Vladimir Sementsov-Ogievskiy wrote:
[]
> So that's a bit of a change, but only visually. The "reality" is still
> the same, we just report it more "accurately." libvirt MIGHT need a
> heads up here. I'm looping pkrempa back in for comment.
>
>
> Would libvirt be negatively impacted by the revelation of formerly
> internal ("implicit") nodes created by mirror and commit via query block
> commands? At the moment, QEMU hides them from you if you do not name them.
Currently we would not be able to handle that properly at least
definitely in the pre-blockdev case. In blockdev case I must make sure
that it will work.
The thing is that I didn't really want to touch the pre-blockdev case
code any more, but if you decide that we should do it I'm willing to
investigate this case also for the old commands.
>
>
> > 3. bdrv_refresh_filename, bdrv_reopen_parse_backing, bdrv_drop_intermediate:
> >I think it's not a problem, just drop special case for implicit fitlers
> >
>
> I'm much less certain about what the impact of this would be and would
> need to audit it (and don't have the time to, personally.)
>
> Do you have a POC or RFC patch that demonstrates dropping these special
> cases? It might be nice to see as proof that it's safe to deprecate.
>
> > So, seems the only real change is query-block and query-blockstats output
> > when mirror or commit is started
> > without specifying filter-node-name (filter would be on top)
> >
> > So, how should we deprecate this, or can we just change it?
> >
>
> I'm not sure if it's worth it yet, what does dropping the implicit field
> buy us? Conceptually I understand that it's simpler without the notion
> of implicit fields, but I imagine there's some cleanup in particular
> that motivated this.
>
> I'd say to just change the behavior, we should:
>
> - Give a standard three-release warning that the behavior will change in
> an incompatible way
> - Demonstrate with an RFC patch that special cases around ->implicit in
> block.c can be removed and do not make the code more complex,
> - Get blessings from Peter Krempa.
>
> As always: Libvirt is not the end-all be-all of QEMU management, but if
> libvirt is capable of working around design changes then I believe any
> project out there today also could, so it's a good litmus test.
For libvirt we really care more whether a node is format/protocol
related or not rather than whether it's implicit or not.
In this case we could filter it by the known protocol and format driver
types and filter out the rest in cases when we e.g. detect the node
names for the pre-blockdev era cases.
(Note that even with new qemu, if an SD card is used blockdev will be
disabled).
signature.asc
Description: PGP signature
Re: [Qemu-devel] [PATCH v9 13/13] block/backup: use backup-top instead of write notifiers
28.08.2019 22:50, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> Drop write notifiers and use filter node instead. >> >> = Changes = >> >> 1. add filter-node-name argument for backup qmp api. We have to do it >> in this commit, as 257 needs to be fixed. > > I feel a bit bad about it not being an implicit node. But I know you > don’t like them, they’re probably just broken altogether and because > libvirt doesn’t use backup (yet), probably nobody cares. > >> 2. there no move write notifiers here, so is_write_notifier parameter > > s/there/there are/, I suppose? > >> is dropped from block-copy paths. >> >> 3. Intersecting requests handling changed, now synchronization between >> backup-top, backup and guest writes are all done in block/block-copy.c >> and works as follows: >> >> On copy operation, we work only with dirty areas. If bits are dirty it >> means that there are no requests intersecting with this area. We clear >> dirty bits and take bdrv range lock (bdrv_co_try_lock) on this area to >> prevent further operations from interaction with guest (only with >> guest, as neither backup nor backup-top will touch non-dirty area). If >> copy-operation failed we set dirty bits back together with releasing >> the lock. >> >> The actual difference with old scheme is that on guest writes we >> don't lock the whole region but only dirty-parts, and to be more >> precise: only dirty-part we are currently operate on. In old scheme >> guest write to non-dirty area (which may be safely ignored by backup) >> may wait for intersecting request, touching some other area which is >> dirty. >> >> 4. To sync with in-flight requests at job finish we now have drained >> removing of the filter, we don't need rw-lock. >> >> = Notes = >> >> Note the consequence of three objects appearing: backup-top, backup job >> and block-copy-state: >> >> 1. We want to insert backup-top before job creation, to behave similar >> with mirror and commit, where job is started upon filter. >> >> 2. We also have to create block-copy-state after filter injection, as >> we don't want it's source child be replaced by fitler. Instead we want > > s/it's/its/, s/filter/filter/ (although “fitler” does have an amusing > ring to it) > >> to keep BCS.source to be real source node, as we want to use >> bdrv_co_try_lock in CBW operations and it can't be used on filter, as >> on filter we already have in-flight (write) request from upper layer. > > Reasonable, even more so as I suppose BCS.source should eventually be a > BdrvChild of backup-top. > > What looks wrong is that the sync_bitmap is created on the source (“bs” > in backup_job_create()), but backup_cleanup_sync_bitmap() still assumes > it is on blk_bs(job->common.blk) (which is no longer true). > >> So, we firstly create inject backup-top, then create job and BCS. BCS >> is the latest just to not create extra variable for it. Finally we set >> bcs for backup-top filter. >> >> = Iotest changes = >> >> 56: op-blocker doesn't shot now, as we set it on source, but then check > > s/shot/show/? > >> on filter, when trying to start second backup, so error caught in >> test_dismiss_collision is changed. It's OK anyway, as this test-case >> seems to test that after some collision we can dismiss first job and >> successfully start the second one. So, the change is that collision is >> changed from op-blocker to file-posix locks. > > Well, but the op blocker belongs to the source, which should be covered > by internal permissions. The fact that it now shows up as a file-posix > error thus shows that the conflict also moves from the source to the > target. It’s OK because we actually don’t have a conflict on the source. > > But I wonder whether it would be better for test_dismiss_collision() to > do a blockdev-backup instead where we can see the collision on the target. > > Hm. On second thought, why do we even get a conflict on the target? > block-copy does share the WRITE permission for it... Not sure, but assume that this is because in file-posix.c in raw_co_create we do want RESIZE perm. I can instead move this test to use specified job-id, to move the collision to "job-id already exists" error. Is it better? I'm afraid that posix locks will not work if disable them in config. > >> However, it's obvious now that we'd better drop this op-blocker at all >> and add a test-case for two backups from one node (to different >> destinations) actually works. But not in these series. >> >> 257: The test wants to emulate guest write during backup. They should >> go to filter node, not to original source node, of course. Therefore we >> need to specify filter node name and use it. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> qapi/block-core.json | 8 +- >> include/block/block-copy.h | 2 +- >> include/block/block_int.h | 1 + >> block/backup-top.c | 14 +- >> block/backup.c | 113 +++--- >>
Re: [Qemu-devel] [qemu-s390x] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On 29.08.19 14:04, Igor Mammedov wrote:
> On Thu, 29 Aug 2019 08:47:49 +0200
> Christian Borntraeger wrote:
>
>> On 27.08.19 14:56, Igor Mammedov wrote:
>>> On Tue, 20 Aug 2019 18:07:27 +0200
>>> Cornelia Huck wrote:
>>>
On Wed, 7 Aug 2019 11:32:41 -0400
Igor Mammedov wrote:
> Max memslot size supported by kvm on s390 is 8Tb,
> move logic of splitting RAM in chunks upto 8T to KVM code.
>
> This way it will hide KVM specific restrictions in KVM code
> and won't affect baord level design decisions. Which would allow
> us to avoid misusing memory_region_allocate_system_memory() API
> and eventually use a single hostmem backend for guest RAM.
>
> Signed-off-by: Igor Mammedov
> ---
> v5:
> * move computation 'size -= slot_size' inside of loop body
> (David Hildenbrand )
> v4:
> * fix compilation issue
> (Christian Borntraeger )
> * advance HVA along with GPA in kvm_set_phys_mem()
> (Christian Borntraeger )
>
> patch prepares only KVM side for switching to single RAM memory region
> another patch will take care of dropping manual RAM partitioning in
> s390 code.
I may have lost track a bit -- what is the status of this patch (and
the series)?
>>>
>>> Christian,
>>>
>>> could you test it on a host that have sufficient amount of RAM?
>>
>>
>> This version looks good. I was able to start a 9TB guest.
>> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
>> guest_phys_addr=0, memory_size=8796091973632, userspace_addr=0x3ffee70})
>> = 0
>> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
>> guest_phys_addr=0x7f0, memory_size=1099512676352,
>> userspace_addr=0xbffee60}) = 0
>>
>> The only question is if we want to fix the weird alignment (0x7f0)
>> when
>> we already add a migration barrier for uber-large guests.
>> Maybe we could split at 4TB to avoid future problem with larger page sizes?
> That probably should be a separate patch on top.
Right. The split in KVM code is transparent to migration and other parts of
QEMU, correct?
Re: [Qemu-devel] [qemu-s390x] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On Thu, 29 Aug 2019 14:07:44 +0200
Christian Borntraeger wrote:
> On 29.08.19 14:04, Igor Mammedov wrote:
> > On Thu, 29 Aug 2019 08:47:49 +0200
> > Christian Borntraeger wrote:
> >
> >> On 27.08.19 14:56, Igor Mammedov wrote:
> >>> On Tue, 20 Aug 2019 18:07:27 +0200
> >>> Cornelia Huck wrote:
> >>>
> On Wed, 7 Aug 2019 11:32:41 -0400
> Igor Mammedov wrote:
>
> > Max memslot size supported by kvm on s390 is 8Tb,
> > move logic of splitting RAM in chunks upto 8T to KVM code.
> >
> > This way it will hide KVM specific restrictions in KVM code
> > and won't affect baord level design decisions. Which would allow
> > us to avoid misusing memory_region_allocate_system_memory() API
> > and eventually use a single hostmem backend for guest RAM.
> >
> > Signed-off-by: Igor Mammedov
> > ---
> > v5:
> > * move computation 'size -= slot_size' inside of loop body
> > (David Hildenbrand )
> > v4:
> > * fix compilation issue
> > (Christian Borntraeger )
> > * advance HVA along with GPA in kvm_set_phys_mem()
> > (Christian Borntraeger )
> >
> > patch prepares only KVM side for switching to single RAM memory region
> > another patch will take care of dropping manual RAM partitioning in
> > s390 code.
>
> I may have lost track a bit -- what is the status of this patch (and
> the series)?
> >>>
> >>> Christian,
> >>>
> >>> could you test it on a host that have sufficient amount of RAM?
> >>
> >>
> >> This version looks good. I was able to start a 9TB guest.
> >> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
> >> guest_phys_addr=0, memory_size=8796091973632,
> >> userspace_addr=0x3ffee70}) = 0
> >> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
> >> guest_phys_addr=0x7f0, memory_size=1099512676352,
> >> userspace_addr=0xbffee60}) = 0
>
> >> The only question is if we want to fix the weird alignment (0x7f0)
> >> when
> >> we already add a migration barrier for uber-large guests.
> >> Maybe we could split at 4TB to avoid future problem with larger page
> >> sizes?
> > That probably should be a separate patch on top.
>
> Right. The split in KVM code is transparent to migration and other parts of
> QEMU, correct?
it should not affect other QEMU parts and migration (to my limited
understanding of it),
we are passing to KVM memory slots upto KVM_SLOT_MAX_BYTES as we were doing
before by
creating several memory regions instead of one as described in [2/2] commit
message.
Also could you also test migration of +9Tb guest, to check that nothing where
broken by
accident in QEMU migration code?
Re: [Qemu-devel] [PATCH v1 2/2] hw/pvrdma: add live migration support
On Wed, Aug 28, 2019 at 07:53:28PM +0530, Sukrit Bhatnagar wrote:
> vmstate_pvrdma describes the PCI and MSIX states as well as the dma
> address for dsr and the gid table of device.
> vmstate_pvrdma_gids describes each gid in the gid table.
>
> pvrdma_post_save() does the job of unregistering gid entries from the
> backend device in the source host.
>
> pvrdma_post_load() maps to dsr using the loaded dma address, registers
> each loaded gid into the backend device, and finally calls load_dsr()
> to perform other mappings and ring init operations.
I think it worth to mention that the dma address is kept in driver/device
shared memory (dsr->dma) which is migrated as part of memory migration and
it is out of the scope of this change and so we do not need to save/load
the dma address during migration.
Also you should specifically comment that this migration-support does not
includes QP migration. This means that support for life migration *during*
traffic is not yet supported.
>
> Cc: Marcel Apfelbaum
> Cc: Yuval Shaia
> Signed-off-by: Sukrit Bhatnagar
> ---
> hw/rdma/vmw/pvrdma_main.c | 77 +++
> 1 file changed, 77 insertions(+)
>
> diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
> index 6c90db96f9..6f8b56dea3 100644
> --- a/hw/rdma/vmw/pvrdma_main.c
> +++ b/hw/rdma/vmw/pvrdma_main.c
> @@ -28,6 +28,7 @@
> #include "sysemu/sysemu.h"
> #include "monitor/monitor.h"
> #include "hw/rdma/rdma.h"
> +#include "migration/register.h"
>
> #include "../rdma_rm.h"
> #include "../rdma_backend.h"
> @@ -593,6 +594,81 @@ static void pvrdma_shutdown_notifier(Notifier *n, void
> *opaque)
> pvrdma_fini(pci_dev);
> }
>
> +static int pvrdma_post_save(void *opaque)
> +{
> +int i, rc;
> +PVRDMADev *dev = opaque;
> +
> +for (i = 0; i < MAX_GIDS; i++) {
> +
Empty line is redundant here.
> +if (!dev->rdma_dev_res.port.gid_tbl[i].gid.global.interface_id) {
> +continue;
> +}
> +rc = rdma_backend_del_gid(>backend_dev,
> + dev->backend_eth_device_name,
> + >rdma_dev_res.port.gid_tbl[i].gid);
> +if (rc) {
> +return -EINVAL;
Some error report will help here i guess.
> +}
> +}
> +
> +return 0;
> +}
> +
> +static int pvrdma_post_load(void *opaque, int version_id)
> +{
> +int i, rc;
> +PVRDMADev *dev = opaque;
> +PCIDevice *pci_dev = PCI_DEVICE(dev);
> +DSRInfo *dsr_info = >dsr_info;
> +
> +dsr_info->dsr = rdma_pci_dma_map(pci_dev, dsr_info->dma,
> +sizeof(struct pvrdma_device_shared_region));
> +if (!dsr_info->dsr) {
> +rdma_error_report("Failed to map to DSR");
> +return -ENOMEM;
> +}
> +
> +for (i = 0; i < MAX_GIDS; i++) {
> +
Empty line is redundant here.
> +if (!dev->rdma_dev_res.port.gid_tbl[i].gid.global.interface_id) {
> +continue;
> +}
> +
> +rc = rdma_backend_add_gid(>backend_dev,
> + dev->backend_eth_device_name,
> + >rdma_dev_res.port.gid_tbl[i].gid);
> +if (rc) {
> +return -EINVAL;
> +}
> +}
> +
> +return load_dsr(dev);
> +}
> +
> +static const VMStateDescription vmstate_pvrdma_gids = {
> +.name = "pvrdma-gids",
> +.fields = (VMStateField[]) {
> +VMSTATE_UINT8_ARRAY_V(gid.raw, RdmaRmGid, 16, 0),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
> +static const VMStateDescription vmstate_pvrdma = {
> +.name = PVRDMA_HW_NAME,
> +.post_save = pvrdma_post_save,
> +.post_load = pvrdma_post_load,
> +.fields = (VMStateField[]) {
> +VMSTATE_PCI_DEVICE(parent_obj, PVRDMADev),
> +VMSTATE_MSIX(parent_obj, PVRDMADev),
> +VMSTATE_UINT64(dsr_info.dma, PVRDMADev),
> +VMSTATE_STRUCT_ARRAY(rdma_dev_res.port.gid_tbl, PVRDMADev,
> + MAX_PORT_GIDS, 0, vmstate_pvrdma_gids,
> + RdmaRmGid),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
> static void pvrdma_realize(PCIDevice *pdev, Error **errp)
> {
> int rc = 0;
> @@ -688,6 +764,7 @@ static void pvrdma_class_init(ObjectClass *klass, void
> *data)
>
> dc->desc = "RDMA Device";
> dc->props = pvrdma_dev_properties;
> +dc->vmsd = _pvrdma;
> set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
>
> ir->print_statistics = pvrdma_print_statistics;
> --
> 2.21.0
>
>
Re: [Qemu-devel] [PATCH v2] pc: Don't make die-id mandatory unless necessary
On Wed, Aug 28, 2019 at 18:57:18 +0200, Igor Mammedov wrote:
> On Wed, 28 Aug 2019 11:35:24 -0300
> Eduardo Habkost wrote:
>
> > On Wed, Aug 28, 2019 at 08:52:28AM +0200, Markus Armbruster wrote:
> > > Eduardo Habkost writes:
> > >
> > > > We have this issue reported when using libvirt to hotplug CPUs:
> > > > https://bugzilla.redhat.com/show_bug.cgi?id=1741451
> > > >
> > > > Basically, libvirt is not copying die-id from
> > > > query-hotpluggable-cpus, but die-id is now mandatory.
> > > >
> > > > We could blame libvirt and say it is not following the documented
> > > > interface, because we have this buried in the QAPI schema
> > > > documentation:
> > > >
> > > >> Note: currently there are 5 properties that could be present
> > > >> but management should be prepared to pass through other
> > > >> properties with device_add command to allow for future
> > > >> interface extension. This also requires the filed names to be kept in
> > > >> sync with the properties passed to -device/device_add.
> > > >
> > > > But I don't think this would be reasonable from us. We can just
> > > > make QEMU more flexible and let die-id to be omitted when there's
> > > > no ambiguity. This will allow us to keep compatibility with
> > > > existing libvirt versions.
> > > >
> > > > Test case included to ensure we don't break this again.
> > > >
> > > > Fixes: commit 176d2cda0dee ("i386/cpu: Consolidate die-id validity in
> > > > smp context")
> > > > Signed-off-by: Eduardo Habkost
> > > > ---
> > > > Changes v1 -> v2:
> > > > * v1 was "pc: Don't make CPU properties mandatory unless necessary"
> > > > * Make only die-id optional (Igor Mammedov)
> > > > ---
> > > > hw/i386/pc.c | 8 ++
> > > > tests/acceptance/pc_cpu_hotplug_props.py | 35
> > > > 2 files changed, 43 insertions(+)
> > > > create mode 100644 tests/acceptance/pc_cpu_hotplug_props.py
> > > >
> > > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > > > index 3ab4bcb3ca..9c3f6ae828 100644
> > > > --- a/hw/i386/pc.c
> > > > +++ b/hw/i386/pc.c
> > > > @@ -2406,6 +2406,14 @@ static void pc_cpu_pre_plug(HotplugHandler
> > > > *hotplug_dev,
> > > > int max_socket = (ms->smp.max_cpus - 1) /
> > > > smp_threads / smp_cores /
> > > > pcms->smp_dies;
> > > >
> > > > +/*
> > > > + * die-id was optional in QEMU 4.0 and older, so keep it
> > > > optional
> > > > + * if there's only one die per socket.
> > > > + */
> > >
> > > Is this comment worth its keep?
> >
> > It's not obvious from the code why die-id is optional and all the
> > other properties are not. The purpose of the comment is to
> > clarify that.
> >
> > >
> > > > +if (cpu->die_id < 0 && pcms->smp_dies == 1) {
> > > > +cpu->die_id = 0;
> > > > +}
> > > > +
> > > > if (cpu->socket_id < 0) {
> > > > error_setg(errp, "CPU socket-id is not set");
> > > > return;
> > > > diff --git a/tests/acceptance/pc_cpu_hotplug_props.py
> > > > b/tests/acceptance/pc_cpu_hotplug_props.py
> > > > new file mode 100644
> > > > index 00..08b7e632c6
> > > > --- /dev/null
> > > > +++ b/tests/acceptance/pc_cpu_hotplug_props.py
> > > > @@ -0,0 +1,35 @@
> > > > +#
> > > > +# Ensure CPU die-id can be omitted on -device
> > > > +#
> > > > +# Copyright (c) 2019 Red Hat Inc
> > > > +#
> > > > +# Author:
> > > > +# Eduardo Habkost
> > > > +#
> > > > +# This library is free software; you can redistribute it and/or
> > > > +# modify it under the terms of the GNU Lesser General Public
> > > > +# License as published by the Free Software Foundation; either
> > > > +# version 2 of the License, or (at your option) any later version.
> > > > +#
> > > > +# This library is distributed in the hope that it will be useful,
> > > > +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > > > +# Lesser General Public License for more details.
> > > > +#
> > > > +# You should have received a copy of the GNU Lesser General Public
> > > > +# License along with this library; if not, see
> > > >
Re: [Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
On 8/29/19 8:04 AM, Michal Privoznik wrote:
>>> A bit of background: up until very recently libvirt used qemu-ga
>>> in all or nothing way. It didn't care why a qemu-ga command
>>> failed. But very recently a new API was introduced which
>>> implements 'best effort' approach (in some cases) and thus
>>> libvirt must differentiate between: {CommandNotFound,
>>> CommandDisabled} and some generic error. While the former classes
>>> mean the API can issue some other commands the latter raises a
>>> red flag causing the API to fail.
>>
>> Why do you need to distinguish CommandNotFound from CommandDisabled?
>
> I don't. That's why I've put them both in curly braces. Perhaps this
> says its better:
>
> switch (klass) {
> case CommandNotFound:
> case CommandDisabled:
> /* okay */
> break;
>
So the obvious counter-question - why not use class CommandNotFound for
a command that was disabled, rather than readding another class that has
no distinctive purpose?
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
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Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v9 07/13] iotests: prepare 124 and 257 bitmap querying for backup-top filter
28.08.2019 19:40, Max Reitz wrote:
> On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote:
>> After backup-top filter appearing it's not possible to see dirty
>> bitmaps in top node, so use node-name instead.
>>
>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>> ---
>> tests/qemu-iotests/124| 3 +-
>> tests/qemu-iotests/257| 39 +---
>> tests/qemu-iotests/257.out| 364 +-
>> tests/qemu-iotests/iotests.py | 22 ++
>> 4 files changed, 173 insertions(+), 255 deletions(-)
>>
>> diff --git a/tests/qemu-iotests/124 b/tests/qemu-iotests/124
>> index 3440f54781..8b6024769c 100755
>> --- a/tests/qemu-iotests/124
>> +++ b/tests/qemu-iotests/124
>> @@ -749,8 +749,7 @@ class
>> TestIncrementalBackupBlkdebug(TestIncrementalBackupBase):
>>
>> # Bitmap Status Check
>> query = self.vm.qmp('query-block')
>> -ret = [bmap for bmap in query['return'][0]['dirty-bitmaps']
>> - if bmap.get('name') == bitmap.name][0]
>> +ret = self.vm.get_bitmap(None, drive0['id'], bitmap.name)
>> self.assert_qmp(ret, 'count', 458752)
>> self.assert_qmp(ret, 'granularity', 65536)
>> self.assert_qmp(ret, 'status', 'frozen')
>
> I see a couple more instances of querying the bitmaps through
> query-block here. Wouldn’t it make sense to replace them all with
> get_bitmap()?
>
> [...]
>
>> diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py
>> index 84438e837c..9381964d9f 100644
>> --- a/tests/qemu-iotests/iotests.py
>> +++ b/tests/qemu-iotests/iotests.py
>> @@ -643,6 +643,28 @@ class VM(qtest.QEMUQtestMachine):
>> return x
>> return None
>>
>> +def query_bitmaps(self):
>> +res = self.qmp("query-named-block-nodes")
>> +return {"bitmaps": {device['node-name']: device['dirty-bitmaps']
>> +for device in res['return']
>> +if 'dirty-bitmaps' in device}}
>
> I’d leave the wrapping in {"bitmaps": x} to the callers, if they need it.
>
>> +
>> +def get_bitmap(self, bitmaps, node_name, name, recording=None):
>> +"""
>> +get a specific bitmap from the object returned by query_bitmaps.
>> +:param recording: If specified, filter results by the specified
>> value.
>> +"""
>> +if bitmaps is None:
>> +bitmaps = self.query_bitmaps()
>> +
>> +for bitmap in bitmaps['bitmaps'][node_name]:
>> +if bitmap.get('name', '') == name:
>> +if recording is None:
>> +return bitmap
>> +elif bitmap.get('recording') == recording:
>> +return bitmap
>
> Maybe add a “break” or “return None” here?
>
> (Yes, yes, you just moved existing code. Still.)
>
No, as we may have several unnamed bitmaps, which should be selected by
"recording"..
>
>> +return None
>> +
>>
>> index_re = re.compile(r'([^\[]+)\[([^\]]+)\]')
>>
>>
>
>
--
Best regards,
Vladimir
Re: [Qemu-devel] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On Thu, 29 Aug 2019 08:47:49 +0200
Christian Borntraeger wrote:
> On 27.08.19 14:56, Igor Mammedov wrote:
> > On Tue, 20 Aug 2019 18:07:27 +0200
> > Cornelia Huck wrote:
> >
> >> On Wed, 7 Aug 2019 11:32:41 -0400
> >> Igor Mammedov wrote:
> >>
> >>> Max memslot size supported by kvm on s390 is 8Tb,
> >>> move logic of splitting RAM in chunks upto 8T to KVM code.
> >>>
> >>> This way it will hide KVM specific restrictions in KVM code
> >>> and won't affect baord level design decisions. Which would allow
> >>> us to avoid misusing memory_region_allocate_system_memory() API
> >>> and eventually use a single hostmem backend for guest RAM.
> >>>
> >>> Signed-off-by: Igor Mammedov
> >>> ---
> >>> v5:
> >>> * move computation 'size -= slot_size' inside of loop body
> >>> (David Hildenbrand )
> >>> v4:
> >>> * fix compilation issue
> >>> (Christian Borntraeger )
> >>> * advance HVA along with GPA in kvm_set_phys_mem()
> >>> (Christian Borntraeger )
> >>>
> >>> patch prepares only KVM side for switching to single RAM memory region
> >>> another patch will take care of dropping manual RAM partitioning in
> >>> s390 code.
> >>
> >> I may have lost track a bit -- what is the status of this patch (and
> >> the series)?
> >
> > Christian,
> >
> > could you test it on a host that have sufficient amount of RAM?
>
>
> This version looks good. I was able to start a 9TB guest.
> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
> guest_phys_addr=0, memory_size=8796091973632, userspace_addr=0x3ffee70})
> = 0
> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
> guest_phys_addr=0x7f0, memory_size=1099512676352,
> userspace_addr=0xbffee60}) = 0
>
> The only question is if we want to fix the weird alignment (0x7f0)
> when
> we already add a migration barrier for uber-large guests.
> Maybe we could split at 4TB to avoid future problem with larger page sizes?
That probably should be a separate patch on top.
Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
On 2019/8/29 上午5:34, Alistair Francis wrote: On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote: Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25 Signed-off-by: liuzhiwei --- fpu/softfloat.c | 119 + include/fpu/softfloat.h | 4 + linux-user/riscv/cpu_loop.c | 8 +- target/riscv/Makefile.objs | 2 +- target/riscv/cpu.h |30 + target/riscv/cpu_bits.h |15 + target/riscv/cpu_helper.c | 7 + target/riscv/csr.c |65 +- target/riscv/helper.h | 354 + target/riscv/insn32.decode | 374 +- target/riscv/insn_trans/trans_rvv.inc.c | 484 + target/riscv/translate.c| 1 + target/riscv/vector_helper.c| 26563 ++ 13 files changed, 28017 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c Hello, Thanks for the patch! As others have pointed out you will need to split the patch up into multiple smaller patches, otherwise it is too hard to review almost 30,000 lines of code. Hi, Alistair I'm so sorry for the inconvenience. It will be a patch set with a cover letter in V2. Can you also include a cover letter with your patch series describing how you are testing this? AFAIK vector extension support isn't in any compiler so I'm assuming you are handwriting the assembly or have toolchain patches. Either way it will help if you can share that so others can test your implementation. Yes, it's handwriting assembly. The assembler in Binutils has support Vector extension. First define an function test_vadd_vv_8 in assembly and then it can be called from a C program. The function is something like /* vadd.vv */ TEST_FUNC(test_vadd_vv_8) vsetvli t1, x0, e8, m2 vlb.v v6, (a4) vsb.v v6, (a3) vsetvli t1, a0, e8, m2 vlb.v v0, (a1) vlb.v v2, (a2) vadd.vv v4, v0, v2 vsb.v v4, (a3) ret .size test_vadd_vv_8, .-test_vadd_vv_8 It takes more time to test than to implement the instructions. Maybe there is some better test method or some forced test cases in QEMU. Could you give me some advice for testing? Best Regards, Zhiwei Alex and Richard have kindly started the review. Once you have addressed their comments and split this patch up into smaller patches you can send a v2 and we can go from there. Once again thanks for doing this implementation for QEMU! Alistair
Re: [Qemu-devel] [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space configurable
On Thu, 29 Aug 2019 11:04:27 +
Shameerali Kolothum Thodi wrote:
> Hi Igor,
>
> > -Original Message-
> > From: Igor Mammedov [mailto:imamm...@redhat.com]
> > Sent: 29 August 2019 09:45
> > To: Shameerali Kolothum Thodi
> > Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > eric.au...@redhat.com; peter.mayd...@linaro.org; sa...@linux.intel.com;
> > ard.biesheu...@linaro.org; Linuxarm ;
> > shannon.zha...@gmail.com; sebastien.bo...@intel.com; ler...@redhat.com
> > Subject: Re: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > configurable
> >
> > On Thu, 15 Aug 2019 08:42:48 +
> > Shameerali Kolothum Thodi wrote:
> >
> > > > -Original Message-
> > > > From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of
> > Shameer
> > > > Kolothum
> > > > Sent: 13 August 2019 22:05
> > > > To: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > > > eric.au...@redhat.com; imamm...@redhat.com
> > > > Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> > > > ard.biesheu...@linaro.org; Linuxarm ;
> > > > shannon.zha...@gmail.com; sebastien.bo...@intel.com;
> > ler...@redhat.com
> > > > Subject: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > > > configurable
> > > >
> > > > This is in preparation for adding support for ARM64 platforms
> > > > where it doesn't use port mapped IO for ACPI IO space. We are
> > > > making changes so that MMIO region can be accommodated
> > > > and board can pass the base address into the aml build function.
> > >
> > > Looks like, this now breaks the "make check" on x86_64 and needs
> > > updating bios-tables-test-allowed-diff.h with DSDT entries. But I am
> > > not sure what changed now compared to v8(and older ones) that makes
> > > it to complain now!.
> >
> > you could see diff of what's changed but running test manually with
> > V=1 env var if you have 'iasl' installed
> >
> > V=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64
> > tests/bios-tables-test
>
> Thanks for that tip and please find below output.
>
> /x86_64/acpi/piix4: Could not access KVM kernel module: No such file or
> directory
> qemu-system-x86_64: failed to initialize KVM: No such file or directory
> qemu-system-x86_64: Back to tcg accelerator
> acpi-test: Warning! DSDT binary file mismatch. Actual [aml:/tmp/aml-RGE76Z],
> Expected [aml:tests/data/acpi/pc/DSDT].
> acpi-test: Warning! DSDT mismatch. Actual [asl:/tmp/asl-TAE76Z.dsl,
> aml:/tmp/aml-RGE76Z], Expected [asl:/tmp/asl-O6B76Z.dsl,
> aml:tests/data/acpi/pc/DSDT].
>
> diff --git a/tmp/asl-O6B76Z.dsl b/tmp/asl-TAE76Z.dsl
> index 823ff002ec..4de5bd3221 100644
> --- a/tmp/asl-O6B76Z.dsl
> +++ b/tmp/asl-TAE76Z.dsl
> @@ -5,13 +5,13 @@
> *
> * Disassembling to symbolic ASL+ operators
> *
> - * Disassembly of tests/data/acpi/pc/DSDT, Thu Aug 29 10:40:40 2019
> + * Disassembly of /tmp/aml-RGE76Z, Thu Aug 29 10:40:40 2019
> *
> * Original Table Header:
> * Signature"DSDT"
> - * Length 0x140B (5131)
> + * Length 0x17E4 (6116)
> * Revision 0x01 32-bit table (V1), no 64-bit math support
> - * Checksum 0xB1
> + * Checksum 0x8B
> * OEM ID "BOCHS "
> * OEM Table ID "BXPCDSDT"
> * OEM Revision 0x0001 (1)
> @@ -787,6 +787,206 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT",
> 0x0001)
> \_SB.CPUS.CSCN ()
> }
>
> +Device (\_SB.PCI0.MHPD)
> +{
> +Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID:
> Hardware ID
> +Name (_UID, "Memory hotplug resources") // _UID: Unique ID
> +Name (_CRS, Reso
>
> I think what happens is since we are now passing the memhp_io_base directly
> into the
> build_memory_hotplug_aml() and removed the "static uint16_t memhp_io_base",
> on
> x86, memory hotplug aml code is always built by default irrespective of
> whether
> acpi_memory_hotplug_init() is invoked or not.
>
> I could either reintroduce a check in build_memory_hotplug_aml() to make sure
> acpi_memory_hotplug_init() is called, or could do something like below,
fix looks fine to me, see minor comment below
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 3995f9a40f..17756c2191 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -1873,9 +1873,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
> "\\_SB.PCI0", "\\_GPE._E02");
> }
> -build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
> - "\\_GPE._E03", AML_SYSTEM_IO,
> - pcms->memhp_io_base);
> +
> +if (acpi_enabled && pcms->acpi_dev && nr_mem) {
double-check call path and see if
acpi_enabled && pcms->acpi_dev
is really necessary
> +build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
> +
Re: [Qemu-devel] [PATCH v1 2/2] hw/pvrdma: add live migration support
On Wed, Aug 28, 2019 at 07:53:28PM +0530, Sukrit Bhatnagar wrote:
> vmstate_pvrdma describes the PCI and MSIX states as well as the dma
> address for dsr and the gid table of device.
> vmstate_pvrdma_gids describes each gid in the gid table.
>
> pvrdma_post_save() does the job of unregistering gid entries from the
> backend device in the source host.
>
> pvrdma_post_load() maps to dsr using the loaded dma address, registers
> each loaded gid into the backend device, and finally calls load_dsr()
> to perform other mappings and ring init operations.
>
> Cc: Marcel Apfelbaum
> Cc: Yuval Shaia
> Signed-off-by: Sukrit Bhatnagar
> ---
> hw/rdma/vmw/pvrdma_main.c | 77 +++
> 1 file changed, 77 insertions(+)
>
> diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
> index 6c90db96f9..6f8b56dea3 100644
> --- a/hw/rdma/vmw/pvrdma_main.c
> +++ b/hw/rdma/vmw/pvrdma_main.c
> @@ -28,6 +28,7 @@
> #include "sysemu/sysemu.h"
> #include "monitor/monitor.h"
> #include "hw/rdma/rdma.h"
> +#include "migration/register.h"
>
> #include "../rdma_rm.h"
> #include "../rdma_backend.h"
> @@ -593,6 +594,81 @@ static void pvrdma_shutdown_notifier(Notifier *n, void
> *opaque)
> pvrdma_fini(pci_dev);
> }
>
> +static int pvrdma_post_save(void *opaque)
> +{
> +int i, rc;
> +PVRDMADev *dev = opaque;
> +
> +for (i = 0; i < MAX_GIDS; i++) {
> +
> +if (!dev->rdma_dev_res.port.gid_tbl[i].gid.global.interface_id) {
> +continue;
> +}
> +rc = rdma_backend_del_gid(>backend_dev,
> + dev->backend_eth_device_name,
> + >rdma_dev_res.port.gid_tbl[i].gid);
> +if (rc) {
> +return -EINVAL;
> +}
> +}
> +
> +return 0;
> +}
> +
> +static int pvrdma_post_load(void *opaque, int version_id)
> +{
> +int i, rc;
> +PVRDMADev *dev = opaque;
> +PCIDevice *pci_dev = PCI_DEVICE(dev);
> +DSRInfo *dsr_info = >dsr_info;
> +
> +dsr_info->dsr = rdma_pci_dma_map(pci_dev, dsr_info->dma,
> +sizeof(struct pvrdma_device_shared_region));
> +if (!dsr_info->dsr) {
> +rdma_error_report("Failed to map to DSR");
> +return -ENOMEM;
> +}
> +
> +for (i = 0; i < MAX_GIDS; i++) {
> +
> +if (!dev->rdma_dev_res.port.gid_tbl[i].gid.global.interface_id) {
> +continue;
> +}
> +
> +rc = rdma_backend_add_gid(>backend_dev,
> + dev->backend_eth_device_name,
> + >rdma_dev_res.port.gid_tbl[i].gid);
> +if (rc) {
> +return -EINVAL;
> +}
> +}
> +
> +return load_dsr(dev);
This check is better performed before any gid manipulation on the host
because no one will undo it if load_dsr fails.
> +}
> +
> +static const VMStateDescription vmstate_pvrdma_gids = {
> +.name = "pvrdma-gids",
> +.fields = (VMStateField[]) {
> +VMSTATE_UINT8_ARRAY_V(gid.raw, RdmaRmGid, 16, 0),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
> +static const VMStateDescription vmstate_pvrdma = {
> +.name = PVRDMA_HW_NAME,
> +.post_save = pvrdma_post_save,
> +.post_load = pvrdma_post_load,
> +.fields = (VMStateField[]) {
> +VMSTATE_PCI_DEVICE(parent_obj, PVRDMADev),
> +VMSTATE_MSIX(parent_obj, PVRDMADev),
> +VMSTATE_UINT64(dsr_info.dma, PVRDMADev),
> +VMSTATE_STRUCT_ARRAY(rdma_dev_res.port.gid_tbl, PVRDMADev,
> + MAX_PORT_GIDS, 0, vmstate_pvrdma_gids,
> + RdmaRmGid),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
> static void pvrdma_realize(PCIDevice *pdev, Error **errp)
> {
> int rc = 0;
> @@ -688,6 +764,7 @@ static void pvrdma_class_init(ObjectClass *klass, void
> *data)
>
> dc->desc = "RDMA Device";
> dc->props = pvrdma_dev_properties;
> +dc->vmsd = _pvrdma;
> set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
>
> ir->print_statistics = pvrdma_print_statistics;
> --
> 2.21.0
>
>
[Qemu-devel] [PATCH] block/vhdx: add check for truncated image files
qemu is currently not able to detect truncated vhdx image files.
Add a basic check if all allocated blocks are reachable to vhdx_co_check.
Signed-off-by: Jan-Hendrik Frintrop
Signed-off-by: Peter Lieven
---
block/vhdx.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/block/vhdx.c b/block/vhdx.c
index 6a09d0a55c..4382b1375d 100644
--- a/block/vhdx.c
+++ b/block/vhdx.c
@@ -2068,10 +2068,29 @@ static int coroutine_fn vhdx_co_check(BlockDriverState
*bs,
BdrvCheckMode fix)
{
BDRVVHDXState *s = bs->opaque;
+VHDXSectorInfo sinfo;
+int64_t file_size = bdrv_get_allocated_file_size(bs);
+int64_t sector_num;
if (s->log_replayed_on_open) {
result->corruptions_fixed++;
}
+
+for (sector_num = 0; sector_num < bs->total_sectors;
+ sector_num += s->block_size / BDRV_SECTOR_SIZE) {
+int nb_sectors = MIN(bs->total_sectors - sector_num,
+ s->block_size / BDRV_SECTOR_SIZE);
+vhdx_block_translate(s, sector_num, nb_sectors, );
+if ((s->bat[sinfo.bat_idx] & VHDX_BAT_STATE_BIT_MASK) ==
+PAYLOAD_BLOCK_FULLY_PRESENT) {
+if (sinfo.file_offset +
+sinfo.sectors_avail * BDRV_SECTOR_SIZE > file_size) {
+/* block is past the end of file, image has been truncated. */
+result->corruptions++;
+}
+}
+}
+
return 0;
}
--
2.17.1
Re: [Qemu-devel] [PATCH for-4.2 v10 07/15] virtio-iommu: Implement attach/detach command
Hi Peter,
On 8/16/19 6:27 AM, Peter Xu wrote:
> On Tue, Jul 30, 2019 at 07:21:29PM +0200, Eric Auger wrote:
>> This patch implements the endpoint attach/detach to/from
>> a domain.
>>
>> Signed-off-by: Eric Auger
>>
>> ---
>> ---
>> hw/virtio/virtio-iommu.c | 40 ++--
>> 1 file changed, 34 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
>> index 77dccecc0a..5ea0930cc2 100644
>> --- a/hw/virtio/virtio-iommu.c
>> +++ b/hw/virtio/virtio-iommu.c
>> @@ -80,8 +80,8 @@ static void
>> virtio_iommu_detach_endpoint_from_domain(viommu_endpoint *ep)
>> ep->domain = NULL;
>> }
>>
>> -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id);
>> -viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s, uint32_t ep_id)
>
> These lines were just introduced in previous patch, I wanted to ask
> why the definition was needed but I don't know whether it'll be used
> in follow up patches. Looks like it wasn't really used.
>
> I would prefer patches like these to be squashed together not only to
> avoid the maintainance of diffs like this between patches, but also as
> a reviewer it'll be easier too when with all the contexts together.
> But I won't ask for it because it can be a personal preference only...
Yes that's a tradeoff. I tried to split the series to ease the review;
helpers were introduced separately in previous patch but not yet used.
Here I introduce call sites and they become static.
>
>> +static viommu_endpoint *virtio_iommu_get_endpoint(VirtIOIOMMU *s,
>> + uint32_t ep_id)
>> {
>> viommu_endpoint *ep;
>>
>> @@ -110,8 +110,8 @@ static void virtio_iommu_put_endpoint(gpointer data)
>> g_free(ep);
>> }
>>
>> -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id);
>> -viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s, uint32_t domain_id)
>> +static viommu_domain *virtio_iommu_get_domain(VirtIOIOMMU *s,
>> + uint32_t domain_id)
>> {
>> viommu_domain *domain;
>>
>> @@ -187,10 +187,27 @@ static int virtio_iommu_attach(VirtIOIOMMU *s,
>> {
>> uint32_t domain_id = le32_to_cpu(req->domain);
>> uint32_t ep_id = le32_to_cpu(req->endpoint);
>> +viommu_domain *domain;
>> +viommu_endpoint *ep;
>>
>> trace_virtio_iommu_attach(domain_id, ep_id);
>>
>> -return VIRTIO_IOMMU_S_UNSUPP;
>> +ep = virtio_iommu_get_endpoint(s, ep_id);
>> +if (ep->domain) {
>> +/*
>> + * the device is already attached to a domain,
>> + * detach it first
>> + */
>> +virtio_iommu_detach_endpoint_from_domain(ep);
>
> Hmm... so this can be called without virtio_iommu_put_endpoint().
> Then I think we'd better move:
>
> g_tree_unref(ep->domain->mappings);
>
> From virtio_iommu_put_endpoint() to inside
> virtio_iommu_detach_endpoint_from_domain() otherwise domain refs might
> leak?
I agree with you. I Also removed g_tree_destroy from
virtio_iommu_put_domain as detaching all its end points should now do
the job.
Thanks
Eric
>
>> +}
>> +
>> +domain = virtio_iommu_get_domain(s, domain_id);
>> +QLIST_INSERT_HEAD(>endpoint_list, ep, next);
>> +
>> +ep->domain = domain;
>> +g_tree_ref(domain->mappings);
>> +
>> +return VIRTIO_IOMMU_S_OK;
>> }
>
> Regards,
>
Re: [Qemu-devel] [qemu-s390x] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On 29.08.19 14:31, Igor Mammedov wrote:
> On Thu, 29 Aug 2019 14:07:44 +0200
> Christian Borntraeger wrote:
>
>> On 29.08.19 14:04, Igor Mammedov wrote:
>>> On Thu, 29 Aug 2019 08:47:49 +0200
>>> Christian Borntraeger wrote:
>>>
On 27.08.19 14:56, Igor Mammedov wrote:
> On Tue, 20 Aug 2019 18:07:27 +0200
> Cornelia Huck wrote:
>
>> On Wed, 7 Aug 2019 11:32:41 -0400
>> Igor Mammedov wrote:
>>
>>> Max memslot size supported by kvm on s390 is 8Tb,
>>> move logic of splitting RAM in chunks upto 8T to KVM code.
>>>
>>> This way it will hide KVM specific restrictions in KVM code
>>> and won't affect baord level design decisions. Which would allow
>>> us to avoid misusing memory_region_allocate_system_memory() API
>>> and eventually use a single hostmem backend for guest RAM.
>>>
>>> Signed-off-by: Igor Mammedov
>>> ---
>>> v5:
>>> * move computation 'size -= slot_size' inside of loop body
>>> (David Hildenbrand )
>>> v4:
>>> * fix compilation issue
>>> (Christian Borntraeger )
>>> * advance HVA along with GPA in kvm_set_phys_mem()
>>> (Christian Borntraeger )
>>>
>>> patch prepares only KVM side for switching to single RAM memory region
>>> another patch will take care of dropping manual RAM partitioning in
>>> s390 code.
>>
>> I may have lost track a bit -- what is the status of this patch (and
>> the series)?
>
> Christian,
>
> could you test it on a host that have sufficient amount of RAM?
This version looks good. I was able to start a 9TB guest.
[pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
guest_phys_addr=0, memory_size=8796091973632,
userspace_addr=0x3ffee70}) = 0
[pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
guest_phys_addr=0x7f0, memory_size=1099512676352,
userspace_addr=0xbffee60}) = 0
>>
The only question is if we want to fix the weird alignment (0x7f0)
when
we already add a migration barrier for uber-large guests.
Maybe we could split at 4TB to avoid future problem with larger page
sizes?
>>> That probably should be a separate patch on top.
>>
>> Right. The split in KVM code is transparent to migration and other parts of
>> QEMU, correct?
>
> it should not affect other QEMU parts and migration (to my limited
> understanding of it),
> we are passing to KVM memory slots upto KVM_SLOT_MAX_BYTES as we were doing
> before by
> creating several memory regions instead of one as described in [2/2] commit
> message.
>
> Also could you also test migration of +9Tb guest, to check that nothing where
> broken by
> accident in QEMU migration code?
I only have one server that is large enough :-/
Re: [Qemu-devel] [PATCH v2] pc: Don't make die-id mandatory unless necessary
On Thu, Aug 29, 2019 at 15:12:33 +0200, Peter Krempa wrote: > On Wed, Aug 28, 2019 at 18:57:18 +0200, Igor Mammedov wrote: > > On Wed, 28 Aug 2019 11:35:24 -0300 [...] > > Also if we would need to change implicit values logic down the road > > it would be a pain like with any default parameters in QEMU, which is > > a good reason against relaxing rule. > > Hi, > > after a discussion with Igor I'm preparing patches which take the > 'props' verbatim and use it for hotplug. It's a fairly simple change in > libvirt. Originally I've opted to reconstruct the props from internal > data since it was simpler as the values were already parsed into > internal structures anyways. > > With some persuation we could even get it into libvirt during the freeze > so that with new libvirt the released stuff will not break any more. https://www.redhat.com/archives/libvir-list/2019-August/msg01322.html signature.asc Description: PGP signature
Re: [Qemu-devel] [PATCH] tests/docker: upgrade docker.py to python3
On Thu, Aug 29, 2019 at 03:41:20PM +0100, Alex Bennée wrote: > The recent podman changes (9459f754134bb) imported enum which is part > of the python3 standard library but only available as an external > library for python2. This causes problems on the fairly restricted > environment such as shippable. Lets bite the bullet and make the > script a fully python3 one. To that end: > > - drop the from __future__ import (we are there now ;-) > - avoid the StringIO import hack > - be consistent with the mode we read/write dockerfiles > - s/iteritems/items/ > - ensure check_output returns strings for processing > > Signed-off-by: Alex Bennée > Cc: Marc-André Lureau > --- > tests/docker/docker.py | 27 ++- > 1 file changed, 14 insertions(+), 13 deletions(-) Reviewed-by: Daniel P. Berrangé Regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [Qemu-devel] [PATCH v1 1/2] hw/pvrdma: make DSR mapping idempotent in load_dsr()
On Wed, Aug 28, 2019 at 07:53:27PM +0530, Sukrit Bhatnagar wrote:
> Map to DSR only when there is no mapping done already i.e., when
> dev->dsr_info.dsr is NULL. This allows the rest of mappings and
> ring inits to be done by calling load_dsr() when DSR has already
> been mapped to, somewhere else.
>
> Move free_dsr() out of load_dsr() and call it before the latter
> as and when needed. This aids the case where load_dsr() is called
> having DSR mapping already done, but the rest of map and init
> operations are pending, and prevents an unmap of the DSR.
>
> Cc: Marcel Apfelbaum
> Cc: Yuval Shaia
> Signed-off-by: Sukrit Bhatnagar
> ---
> hw/rdma/vmw/pvrdma_main.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
> index adcf79cd63..6c90db96f9 100644
> --- a/hw/rdma/vmw/pvrdma_main.c
> +++ b/hw/rdma/vmw/pvrdma_main.c
> @@ -172,15 +172,15 @@ static int load_dsr(PVRDMADev *dev)
> DSRInfo *dsr_info;
> struct pvrdma_device_shared_region *dsr;
>
> -free_dsr(dev);
> -
> -/* Map to DSR */
> -dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
> - sizeof(struct pvrdma_device_shared_region));
> if (!dev->dsr_info.dsr) {
> -rdma_error_report("Failed to map to DSR");
> -rc = -ENOMEM;
> -goto out;
> +/* Map to DSR */
> +dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
> + sizeof(struct
> pvrdma_device_shared_region));
> +if (!dev->dsr_info.dsr) {
> +rdma_error_report("Failed to map to DSR");
> +rc = -ENOMEM;
> +goto out;
> +}
> }
>
> /* Shortcuts */
> @@ -402,6 +402,7 @@ static void pvrdma_regs_write(void *opaque, hwaddr addr,
> uint64_t val,
> case PVRDMA_REG_DSRHIGH:
> trace_pvrdma_regs_write(addr, val, "DSRHIGH", "");
> dev->dsr_info.dma |= val << 32;
> +free_dsr(dev);
> load_dsr(dev);
> init_dsr_dev_caps(dev);
> break;
LGTM, thanks.
Reviewed-by: Yuval Shaia
> --
> 2.21.0
>
>
Re: [Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
On 8/29/19 2:10 PM, Markus Armbruster wrote:
> Michal Privoznik writes:
>
>> If there was a disabled command, then qemu-ga used to report
>> CommandDisabled error class (among with human readable
>> description). This changed in v1.2.0-rc0~28^2~16 in favor of
>> GenericError class.
>
> Really? I believe it was slightly earlier in the same series:
>
> 93b91c59db qemu-ga: switch to the new error format on the wire
> de253f1491 qmp: switch to the new error format on the wire
Ah, you're right. It's the first commit that you reference.
>
> The commit you mention (df1e608a01e) is merely follow-up simplification.
>
>> While the change might work for other
>> classes, this one should not have been dropped because it helps
>> callers distinguish the root cause of the error.
>>
>> A bit of background: up until very recently libvirt used qemu-ga
>> in all or nothing way. It didn't care why a qemu-ga command
>> failed. But very recently a new API was introduced which
>> implements 'best effort' approach (in some cases) and thus
>> libvirt must differentiate between: {CommandNotFound,
>> CommandDisabled} and some generic error. While the former classes
>> mean the API can issue some other commands the latter raises a
>> red flag causing the API to fail.
>
> Why do you need to distinguish CommandNotFound from CommandDisabled?
I don't. That's why I've put them both in curly braces. Perhaps this
says its better:
switch (klass) {
case CommandNotFound:
case CommandDisabled:
/* okay */
break;
default:
/* bad, error out */
break;
}
>
>> This reverts df1e608a01 partially.
>>
>> Signed-off-by: Michal Privoznik
Michal
Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
Hi, Alex
On 2019/8/28 下午5:08, Alex Bennée wrote:
liuzhiwei writes:
Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25
Signed-off-by: liuzhiwei
---
fpu/softfloat.c | 119 +
include/fpu/softfloat.h | 4 +
Changes to softfloat should be in a separate patch, but see bellow.
linux-user/riscv/cpu_loop.c | 8 +-
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h |30 +
target/riscv/cpu_bits.h |15 +
target/riscv/cpu_helper.c | 7 +
target/riscv/csr.c |65 +-
target/riscv/helper.h | 354 +
target/riscv/insn32.decode | 374 +-
target/riscv/insn_trans/trans_rvv.inc.c | 484 +
target/riscv/translate.c| 1 +
target/riscv/vector_helper.c| 26563 ++
This is likely too big to be reviewed. Is it possible to split the patch
up into more discrete chunks, for example support pieces and then maybe
a class at a time?
Yes, a patch set with cover letter will be sent later.
13 files changed, 28017 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 2ba36ec..da155ea 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -433,6 +433,16 @@ static inline int extractFloat16Exp(float16 a)
}
/*
+| Returns the sign bit of the half-precision floating-point value `a'.
+**/
+
+static inline flag extractFloat16Sign(float16 a)
+{
+return float16_val(a) >> 0xf;
+}
+
We are trying to avoid this sort of bit fiddling for new code when we
already have generic decompose functions that can extract all the parts
into a common format.
+
+/*
| Returns the fraction bits of the single-precision floating-point value `a'.
**/
@@ -4790,6 +4800,35 @@ int float32_eq(float32 a, float32 b, float_status
*status)
}
/*
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+**/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+flag aSign, bSign;
+uint16_t av, bv;
+a = float16_squash_input_denormal(a, status);
+b = float16_squash_input_denormal(b, status);
+
+if (( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+float_raise(float_flag_invalid, status);
+return 0;
+}
+aSign = extractFloat16Sign( a );
+bSign = extractFloat16Sign( b );
+av = float16_val(a);
+bv = float16_val(b);
+if ( aSign != bSign ) return aSign || ( (uint16_t) ( ( av | bv )<<1 ) == 0
);
+return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}
What does this provide that:
float16_compare(a, b, status) == float_relation_less;
doesn't?
+
+/*
| Returns 1 if the single-precision floating-point value `a' is less than
| or equal to the corresponding value `b', and 0 otherwise. The invalid
| exception is raised if either operand is a NaN. The comparison is performed
@@ -4825,6 +4864,35 @@ int float32_le(float32 a, float32 b, float_status
*status)
| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
**/
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+flag aSign, bSign;
+uint16_t av, bv;
+a = float16_squash_input_denormal(a, status);
+b = float16_squash_input_denormal(b, status);
+
+if (( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+float_raise(float_flag_invalid, status);
+return 0;
+}
+aSign = extractFloat16Sign( a );
+bSign = extractFloat16Sign( b );
+av = float16_val(a);
+bv = float16_val(b);
+if ( aSign != bSign ) return aSign && ( (uint16_t) ( ( av | bv )<<1 ) != 0
);
+return ( av != bv ) && ( aSign ^ ( av < bv ) );
+
+}
+
Re: [Qemu-devel] [PATCH for-4.2 v10 03/15] virtio-iommu: Add skeleton
Hi Peter,
First of all, please forgive me for the delay.
On 8/15/19 3:54 PM, Peter Xu wrote:
> On Tue, Jul 30, 2019 at 07:21:25PM +0200, Eric Auger wrote:
>> +static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
>> +{
>> +VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
>> +struct virtio_iommu_req_head head;
>> +struct virtio_iommu_req_tail tail;
>
> [1]
>
>> +VirtQueueElement *elem;
>> +unsigned int iov_cnt;
>> +struct iovec *iov;
>> +size_t sz;
>> +
>> +for (;;) {
>> +elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
>> +if (!elem) {
>> +return;
>> +}
>> +
>> +if (iov_size(elem->in_sg, elem->in_num) < sizeof(tail) ||
>> +iov_size(elem->out_sg, elem->out_num) < sizeof(head)) {
>> +virtio_error(vdev, "virtio-iommu bad head/tail size");
>> +virtqueue_detach_element(vq, elem, 0);
>> +g_free(elem);
>> +break;
>> +}
>> +
>> +iov_cnt = elem->out_num;
>> +iov = g_memdup(elem->out_sg, sizeof(struct iovec) * elem->out_num);
>
> Could I ask why memdup is needed here?
Indeed I don't think it is needed and besides iov is not freed!
I got inspired from hw/net/virtio-net.c. To be honest I don't get why
the g_memdup is needed there either. The out_sg gets duplicated and
commands work on the duplicated data and not in place.
>
>> +sz = iov_to_buf(iov, iov_cnt, 0, , sizeof(head));
>> +if (unlikely(sz != sizeof(head))) {
>> +tail.status = VIRTIO_IOMMU_S_DEVERR;
>
> Do you need to zero the reserved bits to make sure it won't contain
> garbage? Same question to below uses of tail.
yes. I initialized tail.
>
>> +goto out;
>> +}
>> +qemu_mutex_lock(>mutex);
>> +switch (head.type) {
>> +case VIRTIO_IOMMU_T_ATTACH:
>> +tail.status = virtio_iommu_handle_attach(s, iov, iov_cnt);
>> +break;
>> +case VIRTIO_IOMMU_T_DETACH:
>> +tail.status = virtio_iommu_handle_detach(s, iov, iov_cnt);
>> +break;
>> +case VIRTIO_IOMMU_T_MAP:
>> +tail.status = virtio_iommu_handle_map(s, iov, iov_cnt);
>> +break;
>> +case VIRTIO_IOMMU_T_UNMAP:
>> +tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
>> +break;
>> +default:
>> +tail.status = VIRTIO_IOMMU_S_UNSUPP;
>> +}
>> +qemu_mutex_unlock(>mutex);
>> +
>> +out:
>> +sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
>> + , sizeof(tail));
>> +assert(sz == sizeof(tail));
>> +
>> +virtqueue_push(vq, elem, sizeof(tail));
>
> s/tail/head/ (though they are the same size)?
That's unclear to me. Similarly when checking against virtio-net.c, the
element is pushed back to the used ring and len is set to the size of
the status with:
/*
* Control virtqueue data structures
*
* The control virtqueue expects a header in the first sg entry
* and an ack/status response in the last entry. Data for the
* command goes in between.
*/
>
>> +virtio_notify(vdev, vq);
>> +g_free(elem);
>> +}
>> +}
>
> [...]
>
>> +static void virtio_iommu_set_features(VirtIODevice *vdev, uint64_t val)
>> +{
>> +VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev);
>> +
>> +dev->acked_features = val;
>> +trace_virtio_iommu_set_features(dev->acked_features);
>> +}
>> +
>> +static const VMStateDescription vmstate_virtio_iommu_device = {
>> +.name = "virtio-iommu-device",
>> +.unmigratable = 1,
>
> Curious, is there explicit reason to not support migration from the
> first version? :)
The state is made of red black trees, lists. For the former there is no
VMSTATE* ready. I am working on it but I think this should be handled
separately
>
>> +};
>> +
>> +static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
>> +{
>> +VirtIODevice *vdev = VIRTIO_DEVICE(dev);
>> +VirtIOIOMMU *s = VIRTIO_IOMMU(dev);
>> +
>> +virtio_init(vdev, "virtio-iommu", VIRTIO_ID_IOMMU,
>> +sizeof(struct virtio_iommu_config));
>> +
>> +s->req_vq = virtio_add_queue(vdev, VIOMMU_DEFAULT_QUEUE_SIZE,
>> + virtio_iommu_handle_command);
>> +s->event_vq = virtio_add_queue(vdev, VIOMMU_DEFAULT_QUEUE_SIZE, NULL);
>> +
>> +s->config.page_size_mask = TARGET_PAGE_MASK;
>> +s->config.input_range.end = -1UL;
>> +s->config.domain_range.start = 0;
>
> Zero input_range.start = 0? After all domain_range.start is zeroed.
virtio_init does:
if (vdev->config_len) {
vdev->config = g_malloc0(config_size);
but I should be homogeneous and then remove s->config.domain_range.start
= 0;
>
>> +s->config.domain_range.end = 32;
>> +
>> +virtio_add_feature(>features, VIRTIO_RING_F_EVENT_IDX);
>> +virtio_add_feature(>features, VIRTIO_RING_F_INDIRECT_DESC);
>> +virtio_add_feature(>features,
Re: [Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
On 8/29/19 3:12 PM, Eric Blake wrote:
On 8/29/19 8:04 AM, Michal Privoznik wrote:
A bit of background: up until very recently libvirt used qemu-ga
in all or nothing way. It didn't care why a qemu-ga command
failed. But very recently a new API was introduced which
implements 'best effort' approach (in some cases) and thus
libvirt must differentiate between: {CommandNotFound,
CommandDisabled} and some generic error. While the former classes
mean the API can issue some other commands the latter raises a
red flag causing the API to fail.
Why do you need to distinguish CommandNotFound from CommandDisabled?
I don't. That's why I've put them both in curly braces. Perhaps this
says its better:
switch (klass) {
case CommandNotFound:
case CommandDisabled:
/* okay */
break;
So the obvious counter-question - why not use class CommandNotFound for
a command that was disabled, rather than readding another class that has
no distinctive purpose?
Because disabling a command is not the same as nonexistent command.
While a command can be disabled by user/sysadmin, they are disabled at
runtime by qemu-ga itself for a short period of time (e.g. on FS freeze
some commands are disabled - typically those which require write disk
access). And I guess reporting CommandNotFound for a command that does
exist only is disabled temporarily doesn't reflect the reality, does it?
On the other hand, CommandNotFound would fix the issue for libvirt, so
if you don't want to invent a new error class, then that's the way to go.
Michal
