[PATCH v11 16/61] target/riscv: vector integer comparison instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c| 123 4 files changed, 246 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1ec2202814..2bcb6c7889 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -445,3 +445,60 @@ DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 435415f9f9..5d022ff414 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -337,6 +337,26 @@ vnsrl_vi101100 . . . 011 . 1010111 @r_vm vnsra_vv101101 . . . 000 . 1010111 @r_vm vnsra_vx101101 . . . 100 . 1010111 @r_vm vnsra_vi101101 . . . 011 . 1010111 @r_vm +vmseq_vv011000 . . . 000 . 1010111 @r_vm +vmseq_vx011000 . . . 100 . 1010111 @r_vm +vmseq_vi011000 . . . 011 . 1010111 @r_vm +vmsne_vv011001 . . . 000 . 1010111 @r_vm +vmsne_vx011001 . . . 100 . 1010111 @r_vm
[PATCH v11 18/61] target/riscv: vector single-width integer multiply instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 + target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 163 4 files changed, 214 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9c576e1220..c2de0d29ba 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -535,3 +535,36 @@ DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3d8986c74d..6b29aad4d2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -365,6 +365,14 @@ vmaxu_vv000110 . . . 000 . 1010111 @r_vm vmaxu_vx000110 . . . 100 . 1010111 @r_vm vmax_vv 000111 . . . 000 . 1010111 @r_vm vmax_vx 000111 . . . 100 . 1010111 @r_vm +vmul_vv 100101 . . . 010 . 1010111 @r_vm +vmul_vx 100101 . . . 110 . 1010111 @r_vm +vmulh_vv100111 . . . 010 . 1010111 @r_vm +vmulh_vx100111 . . . 110 . 1010111 @r_vm +vmulhu_vv 100100 . . . 010 . 1010111 @r_vm +vmulhu_vx 100100 . . . 110 . 1010111 @r_vm +vmulhsu_vv 100110 . . . 010 . 1010111 @r_vm +vmulhsu_vx 100110 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 861fd3bf1a..b5ea1c59a1 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1571,3 +1571,13 @@ GEN_OPIVX_TRANS(vminu_vx, opivx_check) GEN_OPIVX_TRANS(vmin_vx, opivx_check) GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) GEN_OPIVX_TRANS(vmax_vx, opivx_check) + +/* Vector Single-Width Integer Multiply Instructions */ +GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) +GEN_OPIVV_TRANS(vmulh_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) +GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) +GEN_OPIVX_TRANS(vmulh_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cb41daa3ac..ce4aae8753 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -859,6 +859,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
[PATCH v11 21/61] target/riscv: vector single-width integer multiply-add instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88 + 4 files changed, 139 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 60c436616a..a65a38596b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -620,3 +620,36 @@ DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 877d999129..f01cf14777 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -387,6 +387,14 @@ vwmulsu_vv 111010 . . . 010 . 1010111 @r_vm vwmulsu_vx 111010 . . . 110 . 1010111 @r_vm vwmul_vv111011 . . . 010 . 1010111 @r_vm vwmul_vx111011 . . . 110 . 1010111 @r_vm +vmacc_vv101101 . . . 010 . 1010111 @r_vm +vmacc_vx101101 . . . 110 . 1010111 @r_vm +vnmsac_vv 10 . . . 010 . 1010111 @r_vm +vnmsac_vx 10 . . . 110 . 1010111 @r_vm +vmadd_vv101001 . . . 010 . 1010111 @r_vm +vmadd_vx101001 . . . 110 . 1010111 @r_vm +vnmsub_vv 101011 . . . 010 . 1010111 @r_vm +vnmsub_vx 101011 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 9cd31ba1d8..0f549f7a19 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1599,3 +1599,13 @@ GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) GEN_OPIVX_WIDEN_TRANS(vwmul_vx) GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +GEN_OPIVV_TRANS(vmacc_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsac_vv, opivv_check) +GEN_OPIVV_TRANS(vmadd_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsub_vv, opivv_check) +GEN_OPIVX_TRANS(vmacc_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) +GEN_OPIVX_TRANS(vmadd_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 03ce667c5e..0f3ae3c31a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1891,3 +1891,91 @@ GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq) + +/* Vector
[PATCH v11 24/61] target/riscv: vector single-width saturating add and subtract
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385 4 files changed, 444 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9851086730..85bd4b91bc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -692,3 +692,36 @@ DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32) + +DEF_HELPER_6(vsaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 238aa014d1..70df42de9a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -409,6 +409,16 @@ vmv_v_i 010111 1 0 . 011 . 1010111 @r2 vmerge_vvm 010111 0 . . 000 . 1010111 @r_vm_0 vmerge_vxm 010111 0 . . 100 . 1010111 @r_vm_0 vmerge_vim 010111 0 . . 011 . 1010111 @r_vm_0 +vsaddu_vv 10 . . . 000 . 1010111 @r_vm +vsaddu_vx 10 . . . 100 . 1010111 @r_vm +vsaddu_vi 10 . . . 011 . 1010111 @r_vm +vsadd_vv11 . . . 000 . 1010111 @r_vm +vsadd_vx11 . . . 100 . 1010111 @r_vm +vsadd_vi11 . . . 011 . 1010111 @r_vm +vssubu_vv 100010 . . . 000 . 1010111 @r_vm +vssubu_vx 100010 . . . 100 . 1010111 @r_vm +vssub_vv100011 . . . 000 . 1010111 @r_vm +vssub_vx100011 . . . 100 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index f9532ebc71..a2ab14ade0 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1731,3 +1731,19 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +GEN_OPIVV_TRANS(vsaddu_vv, opivv_check) +GEN_OPIVV_TRANS(vsadd_vv, opivv_check) +GEN_OPIVV_TRANS(vssubu_vv, opivv_check) +GEN_OPIVV_TRANS(vssub_vv, opivv_check) +GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) +GEN_OPIVX_TRANS(vsadd_vx, opivx_check) +GEN_OPIVX_TRANS(vssubu_vx, opivx_check) +GEN_OPIVX_TRANS(vssub_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index
[PATCH v11 23/61] target/riscv: vector integer merge and move instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113
target/riscv/vector_helper.c| 88 ++
4 files changed, 225 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1249ee274d..9851086730 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -675,3 +675,20 @@ DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_b, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_h, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_w, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_d, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 843c15f8fa..238aa014d1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -71,6 +71,7 @@
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd
+@r_vm_0 .. . . . ... . ... vm=0 %rs2 %rs1 %rd
@r_wdvm . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
@r2_zimm . zimm:11 . ... . ... %rs1 %rd
@@ -402,6 +403,12 @@ vwmacc_vx 01 . . . 110 . 1010111
@r_vm
vwmaccsu_vv 10 . . . 010 . 1010111 @r_vm
vwmaccsu_vx 10 . . . 110 . 1010111 @r_vm
vwmaccus_vx 11 . . . 110 . 1010111 @r_vm
+vmv_v_v 010111 1 0 . 000 . 1010111 @r2
+vmv_v_x 010111 1 0 . 100 . 1010111 @r2
+vmv_v_i 010111 1 0 . 011 . 1010111 @r2
+vmerge_vvm 010111 0 . . 000 . 1010111 @r_vm_0
+vmerge_vxm 010111 0 . . 100 . 1010111 @r_vm_0
+vmerge_vim 010111 0 . . 011 . 1010111 @r_vm_0
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 24e43c615c..f9532ebc71 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1618,3 +1618,116 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
+
+/* Vector Integer Merge and Move Instructions */
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs1, false)) {
+
+if (s->vl_eq_vlmax) {
+tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+} else {
+uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+static gen_helper_gvec_2_ptr * const fns[4] = {
+gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+};
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+gen_set_label(over);
+}
+return true;
+}
+return false;
+}
+
+typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
+static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false)) {
+
+TCGv s1;
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+s1 = tcg_temp_new();
+
[PATCH v11 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 107
4 files changed, 122 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index db9e2024ae..b2fc71c2ea 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -742,3 +742,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 57228242aa..1dfc5f7ca0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -424,6 +424,8 @@ vaadd_vx100100 . . . 100 . 1010111 @r_vm
vaadd_vi100100 . . . 011 . 1010111 @r_vm
vasub_vv100110 . . . 000 . 1010111 @r_vm
vasub_vx100110 . . . 100 . 1010111 @r_vm
+vsmul_vv100111 . . . 000 . 1010111 @r_vm
+vsmul_vx100111 . . . 100 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 354a802518..8e85a2aed3 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1754,3 +1754,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
+GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8bb8fe159a..bfd2312b61 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2597,3 +2597,110 @@ GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+{
+uint8_t round;
+int16_t res;
+
+res = (int16_t)a * (int16_t)b;
+round = get_round(vxrm, res, 7);
+res = (res >> 7) + round;
+
+if (res > INT8_MAX) {
+env->vxsat = 0x1;
+return INT8_MAX;
+} else if (res < INT8_MIN) {
+env->vxsat = 0x1;
+return INT8_MIN;
+} else {
+return res;
+}
+}
+
+static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+{
+uint8_t round;
+int32_t res;
+
+res = (int32_t)a * (int32_t)b;
+round = get_round(vxrm, res, 15);
+res = (res >> 15) + round;
+
+if (res > INT16_MAX) {
+env->vxsat = 0x1;
+return INT16_MAX;
+} else if (res < INT16_MIN) {
+env->vxsat = 0x1;
+return INT16_MIN;
+} else {
+return res;
+}
+}
+
+static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+{
+uint8_t round;
+int64_t res;
+
+res = (int64_t)a * (int64_t)b;
+round = get_round(vxrm, res, 31);
+res = (res >> 31) + round;
+
+if (res > INT32_MAX) {
+env->vxsat = 0x1;
+return INT32_MAX;
+} else if (res < INT32_MIN) {
+env->vxsat = 0x1;
+return INT32_MIN;
+} else {
+return res;
+}
+}
+
+static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+{
+uint8_t round;
+uint64_t hi_64, lo_64;
+int64_t res;
+
+if (a == INT64_MIN && b == INT64_MIN) {
+env->vxsat = 1;
+return INT64_MAX;
+}
+
+muls64(_64, _64, a, b);
+round = get_round(vxrm, lo_64, 63);
+/*
+ * Cannot overflow, as there are always
+ * 2 sign bits after multiply.
+ */
+res = (hi_64 << 1) | (lo_64 >> 63);
+if (round) {
+if (res == INT64_MAX) {
+env->vxsat = 1;
+} else {
+res += 1;
+}
+
[PATCH v11 28/61] target/riscv: vector single-width scaling shift instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 117
4 files changed, 148 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f123302b82..78438f1ad6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -773,3 +773,20 @@ DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8cc2bf4864..7d5dfeb5c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -433,6 +433,12 @@ vwsmacc_vx 01 . . . 100 . 1010111
@r_vm
vwsmaccsu_vv10 . . . 000 . 1010111 @r_vm
vwsmaccsu_vx10 . . . 100 . 1010111 @r_vm
vwsmaccus_vx11 . . . 100 . 1010111 @r_vm
+vssrl_vv101010 . . . 000 . 1010111 @r_vm
+vssrl_vx101010 . . . 100 . 1010111 @r_vm
+vssrl_vi101010 . . . 011 . 1010111 @r_vm
+vssra_vv101011 . . . 000 . 1010111 @r_vm
+vssra_vx101011 . . . 100 . 1010111 @r_vm
+vssra_vi101011 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 5e36ee8de5..31be40f4ba 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1767,3 +1767,11 @@ GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
+
+/* Vector Single-Width Scaling Shift Instructions */
+GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
+GEN_OPIVV_TRANS(vssra_vv, opivv_check)
+GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
+GEN_OPIVX_TRANS(vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 61e819eb2f..b22651d7d5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2909,3 +2909,120 @@ RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4,
vwsmaccus32)
GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
+
+/* Vector Single-Width Scaling Shift Instructions */
+static inline uint8_t
+vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+{
+uint8_t round, shift = b & 0x7;
+uint8_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint16_t
+vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b)
+{
+uint8_t round, shift = b & 0xf;
+uint16_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint32_t
+vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b)
+{
+uint8_t round, shift = b & 0x1f;
+uint32_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint64_t
+vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b)
+{
+uint8_t round, shift = b & 0x3f;
+uint64_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
+RVVCALL(OPIVV2_RM, vssrl_vv_h,
[PATCH v11 30/61] target/riscv: vector single-width floating-point add/subtract instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 118
target/riscv/vector_helper.c| 111 ++
4 files changed, 250 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5fa4330200..ba8a3710e1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -803,3 +803,19 @@ DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 78e6da6205..9e26ed36e7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -445,6 +445,11 @@ vnclipu_vi 101110 . . . 011 . 1010111
@r_vm
vnclip_vv 10 . . . 000 . 1010111 @r_vm
vnclip_vx 10 . . . 100 . 1010111 @r_vm
vnclip_vi 10 . . . 011 . 1010111 @r_vm
+vfadd_vv00 . . . 001 . 1010111 @r_vm
+vfadd_vf00 . . . 101 . 1010111 @r_vm
+vfsub_vv10 . . . 001 . 1010111 @r_vm
+vfsub_vf10 . . . 101 . 1010111 @r_vm
+vfrsub_vf 100111 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index b9d29f4051..55a6e514a9 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1783,3 +1783,121 @@ GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
GEN_OPIVX_NARROW_TRANS(vnclip_vx)
GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+
+/*
+ *** Vector Float Point Arithmetic Instructions
+ */
+/* Vector Single-Width Floating-Point Add/Subtract Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised.
+ */
+static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_reg(s, a->rs1, false) &&
+(s->sew != 0));
+}
+
+/* OPFVV without GVEC IR */
+#define GEN_OPFVV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+if (CHECK(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_4_ptr * const fns[3] = {\
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+gen_helper_##NAME##_d, \
+}; \
+TCGLabel *over = gen_new_label(); \
+gen_set_rm(s, 7); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd)
[PATCH v11 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 49 + 4 files changed, 77 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 828b145150..94305bd870 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -836,3 +836,19 @@ DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_6(vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 42d8a967d0..5db02f0c0a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -458,6 +458,11 @@ vfwsub_vv 110010 . . . 001 . 1010111 @r_vm vfwsub_vf 110010 . . . 101 . 1010111 @r_vm vfwsub_wv 110110 . . . 001 . 1010111 @r_vm vfwsub_wf 110110 . . . 101 . 1010111 @r_vm +vfmul_vv100100 . . . 001 . 1010111 @r_vm +vfmul_vf100100 . . . 101 . 1010111 @r_vm +vfdiv_vv10 . . . 001 . 1010111 @r_vm +vfdiv_vf10 . . . 101 . 1010111 @r_vm +vfrdiv_vf 11 . . . 101 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 0224b66962..be9a9a8295 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2050,3 +2050,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) + +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) +GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) +GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) +GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 85d1f08bd0..8538a63419 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3361,3 +3361,52 @@ RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl) GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq) + +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) +RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) +RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) +GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) +RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) +RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) +GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq) + +RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) +RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) +RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) +RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) +RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) +GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq) + +static uint16_t
[PATCH v9 59/61] target/riscv: vector register gather instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 3 +
target/riscv/insn_trans/trans_rvv.inc.c | 78 +
target/riscv/vector_helper.c| 60 +++
4 files changed, 150 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6a5e32d1e4..3da863ac13 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1130,3 +1130,12 @@ DEF_HELPER_6(vslide1down_vx_b, void, ptr, ptr, tl, ptr,
env, i32)
DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 34ccad53a9..e07ff7eff6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -572,6 +572,9 @@ vslide1up_vx001110 . . . 110 . 1010111 @r_vm
vslidedown_vx 00 . . . 100 . 1010111 @r_vm
vslidedown_vi 00 . . . 011 . 1010111 @r_vm
vslide1down_vx 00 . . . 110 . 1010111 @r_vm
+vrgather_vv 001100 . . . 000 . 1010111 @r_vm
+vrgather_vx 001100 . . . 100 . 1010111 @r_vm
+vrgather_vi 001100 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index ffb9835d07..f6547f7e6d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2776,3 +2776,81 @@ GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx,
slideup_check)
GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
+
+/* Vector Register Gather Instruction */
+static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs1, false) &&
+vext_check_reg(s, a->rs2, false) &&
+(a->rd != a->rs2) && (a->rd != a->rs1));
+}
+
+GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
+
+static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+(a->rd != a->rs2));
+}
+
+/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
+static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
+{
+if (!vrgather_vx_check(s, a)) {
+return false;
+}
+
+if (a->vm && s->vl_eq_vlmax) {
+int vlmax = s->vlen / s->mlen;
+TCGv_i64 dest = tcg_temp_new_i64();
+
+if (a->rs1 == 0) {
+vec_element_loadi(s, dest, a->rs2, 0);
+} else {
+vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
+}
+
+tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), dest);
+tcg_temp_free_i64(dest);
+} else {
+static gen_helper_opivx * const fns[4] = {
+gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
+gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
+};
+return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
+}
+return true;
+}
+
+/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
+static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
+{
+if (!vrgather_vx_check(s, a)) {
+return false;
+}
+
+if (a->vm && s->vl_eq_vlmax) {
+if (a->rs1 >= s->vlen / s->mlen) {
+tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), 0);
+} else {
+tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
+
[PATCH v9 60/61] target/riscv: vector compress instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 26
4 files changed, 64 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3da863ac13..8d97114d81 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1139,3 +1139,8 @@ DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e07ff7eff6..a37e205eb7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,6 +575,7 @@ vslide1down_vx 00 . . . 110 . 1010111 @r_vm
vrgather_vv 001100 . . . 000 . 1010111 @r_vm
vrgather_vx 001100 . . . 100 . 1010111 @r_vm
vrgather_vi 001100 . . . 011 . 1010111 @r_vm
+vcompress_vm010111 - . . 010 . 1010111 @r
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index f6547f7e6d..ebc4e8174f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2854,3 +2854,35 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
}
return true;
}
+
+/* Vector Compress Instruction */
+static bool vcompress_vm_check(DisasContext *s, arg_r *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
+(a->rd != a->rs2));
+}
+
+static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
+{
+if (vcompress_vm_check(s, a)) {
+uint32_t data = 0;
+static gen_helper_gvec_4_ptr * const fns[4] = {
+gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
+gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
+};
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+gen_set_label(over);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 220fa76d54..e9e0b1e7a8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4871,3 +4871,29 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb)
GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh)
GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl)
GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
+
+/* Vector Compress Instruction */
+#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+uint32_t mlen = vext_mlen(desc); \
+uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+uint32_t vl = env->vl;\
+uint32_t num = 0, i; \
+ \
+for (i = 0; i < vl; i++) {\
+if (!vext_elem_mask(vs1, mlen, i)) { \
+continue; \
+} \
+*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
+num++;\
+} \
+CLEAR_FN(vd, num, num *
[PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 19 +++
4 files changed, 54 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7ae41ebc2c..e78298e479 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1097,3 +1097,5 @@ DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env,
i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index decb7f773f..4c7706561a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -554,6 +554,7 @@ vmnor_mm00 - . . 010 . 1010111 @r
vmornot_mm 011100 - . . 010 . 1010111 @r
vmxnor_mm 01 - . . 010 . 1010111 @r
vmpopc_m010100 . . - 010 . 1010111 @r2_vm
+vmfirst_m 010101 . . - 010 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index d1c8c6a11f..735ae8377e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2421,3 +2421,35 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
}
return false;
}
+
+/* vmfirst find-first-set mask bit */
+static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+{
+if (vext_check_isa_ill(s)) {
+TCGv_ptr src2, mask;
+TCGv dst;
+TCGv_i32 desc;
+uint32_t data = 0;
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, VM, a->vm);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+mask = tcg_temp_new_ptr();
+src2 = tcg_temp_new_ptr();
+dst = tcg_temp_new();
+desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
+gen_set_gpr(a->rd, dst);
+
+tcg_temp_free_ptr(mask);
+tcg_temp_free_ptr(src2);
+tcg_temp_free(dst);
+tcg_temp_free_i32(desc);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f572388981..d178ed4c0b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4562,3 +4562,22 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2,
CPURISCVState *env,
}
return cnt;
}
+
+/* vmfirst find-first-set mask bit*/
+target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+uint32_t mlen = vext_mlen(desc);
+uint32_t vm = vext_vm(desc);
+uint32_t vl = env->vl;
+int i;
+
+for (i = 0; i < vl; i++) {
+if (vm || vext_elem_mask(v0, mlen, i)) {
+if (vext_elem_mask(vs2, mlen, i)) {
+return i;
+}
+}
+}
+return -1LL;
+}
--
2.23.0
[PATCH v9 56/61] target/riscv: integer scalar move instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 60 +
target/riscv/internals.h| 6 +++
3 files changed, 67 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 26dd0f1b1b..0741a25540 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -562,6 +562,7 @@ vmsof_m 010110 . . 00010 010 . 1010111
@r2_vm
viota_m 010110 . . 1 010 . 1010111 @r2_vm
vid_v 010110 . 0 10001 010 . 1010111 @r1_vm
vext_x_v001100 1 . . 010 . 1010111 @r
+vmv_s_x 001101 1 0 . 110 . 1010111 @r2
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 0dedf4983d..e67eff0a7f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2649,3 +2649,63 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
tcg_temp_free_i64(tmp);
return true;
}
+
+/* Integer Scalar Move Instruction */
+
+static void store_element(TCGv_i64 val, TCGv_ptr base,
+ int ofs, int sew)
+{
+switch (sew) {
+case MO_8:
+tcg_gen_st8_i64(val, base, ofs);
+break;
+case MO_16:
+tcg_gen_st16_i64(val, base, ofs);
+break;
+case MO_32:
+tcg_gen_st32_i64(val, base, ofs);
+break;
+case MO_64:
+tcg_gen_st_i64(val, base, ofs);
+break;
+default:
+g_assert_not_reached();
+break;
+}
+}
+
+/*
+ * Store vreg[idx] = val.
+ * The index must be in range of VLMAX.
+ */
+static void vec_element_storei(DisasContext *s, int vreg,
+ int idx, TCGv_i64 val)
+{
+store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+/* vmv.s.x vd, rs1 # vd[0] = rs1 */
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+if (vext_check_isa_ill(s)) {
+/* This instruction ignores LMUL and vector register groups */
+int maxsz = s->vlen >> 3;
+TCGv_i64 t1;
+TCGLabel *over = gen_new_label();
+
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
+if (a->rs1 == 0) {
+goto done;
+}
+
+t1 = tcg_temp_new_i64();
+tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+vec_element_storei(s, a->rd, 0, t1);
+tcg_temp_free_i64(t1);
+done:
+gen_set_label(over);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f3cea478f7..37d33820ad 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -32,4 +32,10 @@ FIELD(VDATA, WD, 11, 1)
target_ulong fclass_h(uint64_t frs1);
target_ulong fclass_s(uint64_t frs1);
target_ulong fclass_d(uint64_t frs1);
+
+#define SEW8 0
+#define SEW16 1
+#define SEW32 2
+#define SEW64 3
+
#endif
--
2.23.0
[PATCH v9 53/61] target/riscv: vector iota instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 27 +++
target/riscv/vector_helper.c| 29 +
4 files changed, 62 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ae93b6018d..90e6d31d78 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1103,3 +1103,8 @@ DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsof_m, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(viota_m_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(viota_m_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(viota_m_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(viota_m_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b2bc6ab3dd..37756fa76d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -558,6 +558,7 @@ vmfirst_m 010101 . . - 010 . 1010111
@r2_vm
vmsbf_m 010110 . . 1 010 . 1010111 @r2_vm
vmsif_m 010110 . . 00011 010 . 1010111 @r2_vm
vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
+viota_m 010110 . . 1 010 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 3b59170bed..b109732d11 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2481,3 +2481,30 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)
+
+/* Vector Iota Instruction */
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
+(a->vm != 0 || a->rd != 0)) {
+uint32_t data = 0;
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, VM, a->vm);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+static gen_helper_gvec_3_ptr * const fns[4] = {
+gen_helper_viota_m_b, gen_helper_viota_m_h,
+gen_helper_viota_m_w, gen_helper_viota_m_d,
+};
+tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fns[s->sew]);
+gen_set_label(over);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6a579a6300..d6283053f1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4644,3 +4644,32 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2,
CPURISCVState *env,
{
vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
}
+
+/* Vector Iota Instruction */
+#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN)\
+void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+uint32_t mlen = vext_mlen(desc); \
+uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+uint32_t vm = vext_vm(desc); \
+uint32_t vl = env->vl;\
+uint32_t sum = 0; \
+int i;\
+ \
+for (i = 0; i < vl; i++) {\
+if (!vm && !vext_elem_mask(v0, mlen, i)) {\
+continue; \
+} \
+*((ETYPE *)vd + H(i)) = sum; \
+if (vext_elem_mask(vs2, mlen, i)) { \
+sum++;\
+} \
+} \
+CLEAR_FN
[PATCH v9 54/61] target/riscv: vector element index instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 25 +
target/riscv/vector_helper.c| 24
4 files changed, 56 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 90e6d31d78..9e80e4ca23 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1108,3 +1108,8 @@ DEF_HELPER_5(viota_m_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_4(vid_v_b, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vid_v_h, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vid_v_w, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vid_v_d, void, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 37756fa76d..1231628cb2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -70,6 +70,7 @@
@r2 ... . . ... . ... %rs1 %rd
@r2_nfvm ... ... vm:1 . . ... . ... %nf %rs1 %rd
@r2_vm .. vm:1 . . ... . ... %rs2 %rd
+@r1_vm .. vm:1 . . ... . ... %rd
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd
@@ -559,6 +560,7 @@ vmsbf_m 010110 . . 1 010 . 1010111
@r2_vm
vmsif_m 010110 . . 00011 010 . 1010111 @r2_vm
vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
viota_m 010110 . . 1 010 . 1010111 @r2_vm
+vid_v 010110 . 0 10001 010 . 1010111 @r1_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index b109732d11..e73e9dac33 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2508,3 +2508,28 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m
*a)
}
return false;
}
+
+/* Vector Element Index Instruction */
+static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false)) {
+uint32_t data = 0;
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, VM, a->vm);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+static gen_helper_gvec_2_ptr * const fns[4] = {
+gen_helper_vid_v_b, gen_helper_vid_v_h,
+gen_helper_vid_v_w, gen_helper_vid_v_d,
+};
+tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+gen_set_label(over);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d6283053f1..1dc2a1ccb1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4673,3 +4673,27 @@ GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
+
+/* Vector Element Index Instruction */
+#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
+{ \
+uint32_t mlen = vext_mlen(desc); \
+uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+uint32_t vm = vext_vm(desc); \
+uint32_t vl = env->vl;\
+int i;\
+ \
+for (i = 0; i < vl; i++) {\
+if (!vm && !vext_elem_mask(v0, mlen, i)) {\
+continue; \
+} \
+*((ETYPE *)vd + H(i)) = i;\
+} \
+
[PATCH v9 58/61] target/riscv: vector slide instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18
target/riscv/vector_helper.c| 114
4 files changed, 156 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9e80e4ca23..6a5e32d1e4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1113,3 +1113,20 @@ DEF_HELPER_4(vid_v_b, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_h, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_w, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_d, void, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vslideup_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 79f9b37b29..34ccad53a9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -72,6 +72,7 @@
@r2_vm .. vm:1 . . ... . ... %rs2 %rd
@r1_vm .. vm:1 . . ... . ... %rd
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
+@r2rd... . . ... . ... %rs2 %rd
@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd
@r_vm_0 .. . . . ... . ... vm=0 %rs2 %rs1 %rd
@@ -565,6 +566,12 @@ vext_x_v001100 1 . . 010 . 1010111 @r
vmv_s_x 001101 1 0 . 110 . 1010111 @r2
vfmv_f_s001100 1 . 0 001 . 1010111 @r2rd
vfmv_s_f001101 1 0 . 101 . 1010111 @r2
+vslideup_vx 001110 . . . 100 . 1010111 @r_vm
+vslideup_vi 001110 . . . 011 . 1010111 @r_vm
+vslide1up_vx001110 . . . 110 . 1010111 @r_vm
+vslidedown_vx 00 . . . 100 . 1010111 @r_vm
+vslidedown_vi 00 . . . 011 . 1010111 @r_vm
+vslide1down_vx 00 . . . 110 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 884ad910b1..ffb9835d07 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2758,3 +2758,21 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f
*a)
}
return false;
}
+
+/* Vector Slide Instructions */
+static bool slideup_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+(a->rd != a->rs2));
+}
+
+GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
+GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
+
+GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
+GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1dc2a1ccb1..28b54d2589 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4697,3 +4697,117 @@ GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh)
GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl)
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
+
+/*
+ *** Vector Permutation Instructions
+ */
+
+/* Vector Slide Instructions */
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN)\
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{
[PATCH v9 57/61] target/riscv: floating-point scalar move instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 49 +
2 files changed, 51 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0741a25540..79f9b37b29 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -563,6 +563,8 @@ viota_m 010110 . . 1 010 . 1010111
@r2_vm
vid_v 010110 . 0 10001 010 . 1010111 @r1_vm
vext_x_v001100 1 . . 010 . 1010111 @r
vmv_s_x 001101 1 0 . 110 . 1010111 @r2
+vfmv_f_s001100 1 . 0 001 . 1010111 @r2rd
+vfmv_s_f001101 1 0 . 101 . 1010111 @r2
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index e67eff0a7f..884ad910b1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2709,3 +2709,52 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x
*a)
}
return false;
}
+
+/* Floating-Point Scalar Move Instructions */
+static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
+{
+if (!s->vill && has_ext(s, RVF) &&
+(s->mstatus_fs != 0) && (s->sew != 0)) {
+unsigned int len = 8 << s->sew;
+
+vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
+if (len < 64) {
+tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+MAKE_64BIT_MASK(len, 64 - len));
+}
+
+mark_fs_dirty(s);
+return true;
+}
+return false;
+}
+
+/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
+static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
+{
+if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
+TCGv_i64 t1;
+/* The instructions ignore LMUL and vector register group. */
+uint32_t vlmax = s->vlen >> 3;
+
+/* if vl == 0, skip vector register write back */
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+/* zeroed all elements */
+tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
+
+/* NaN-box f[rs1] as necessary for SEW */
+t1 = tcg_temp_new_i64();
+if (s->sew == MO_64 && !has_ext(s, RVD)) {
+tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
+} else {
+tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
+}
+vec_element_storei(s, a->rd, 0, t1);
+tcg_temp_free_i64(t1);
+gen_set_label(over);
+return true;
+}
+return false;
+}
--
2.23.0
[PATCH v9 55/61] target/riscv: integer extract instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 116
2 files changed, 117 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1231628cb2..26dd0f1b1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -561,6 +561,7 @@ vmsif_m 010110 . . 00011 010 . 1010111
@r2_vm
vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
viota_m 010110 . . 1 010 . 1010111 @r2_vm
vid_v 010110 . 0 10001 010 . 1010111 @r1_vm
+vext_x_v001100 1 . . 010 . 1010111 @r
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index e73e9dac33..0dedf4983d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2533,3 +2533,119 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
}
return false;
}
+
+/*
+ *** Vector Permutation Instructions
+ */
+
+/* Integer Extract Instruction */
+
+static void load_element(TCGv_i64 dest, TCGv_ptr base,
+ int ofs, int sew)
+{
+switch (sew) {
+case MO_8:
+tcg_gen_ld8u_i64(dest, base, ofs);
+break;
+case MO_16:
+tcg_gen_ld16u_i64(dest, base, ofs);
+break;
+case MO_32:
+tcg_gen_ld32u_i64(dest, base, ofs);
+break;
+case MO_64:
+tcg_gen_ld_i64(dest, base, ofs);
+break;
+default:
+g_assert_not_reached();
+break;
+}
+}
+
+/* offset of the idx element with base regsiter r */
+static uint32_t endian_ofs(DisasContext *s, int r, int idx)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
+#else
+return vreg_ofs(s, r) + (idx << s->sew);
+#endif
+}
+
+/* adjust the index according to the endian */
+static void endian_adjust(TCGv_i32 ofs, int sew)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
+#endif
+}
+
+/* Load idx >= VLMAX ? 0 : vreg[idx] */
+static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
+ int vreg, TCGv idx, int vlmax)
+{
+TCGv_i32 ofs = tcg_temp_new_i32();
+TCGv_ptr base = tcg_temp_new_ptr();
+TCGv_i64 t_idx = tcg_temp_new_i64();
+TCGv_i64 t_vlmax, t_zero;
+
+/*
+ * Mask the index to the length so that we do
+ * not produce an out-of-range load.
+ */
+tcg_gen_trunc_tl_i32(ofs, idx);
+tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
+
+/* Convert the index to an offset. */
+endian_adjust(ofs, s->sew);
+tcg_gen_shli_i32(ofs, ofs, s->sew);
+
+/* Convert the index to a pointer. */
+tcg_gen_ext_i32_ptr(base, ofs);
+tcg_gen_add_ptr(base, base, cpu_env);
+
+/* Perform the load. */
+load_element(dest, base,
+ vreg_ofs(s, vreg), s->sew);
+tcg_temp_free_ptr(base);
+tcg_temp_free_i32(ofs);
+
+/* Flush out-of-range indexing to zero. */
+t_vlmax = tcg_const_i64(vlmax);
+t_zero = tcg_const_i64(0);
+tcg_gen_extu_tl_i64(t_idx, idx);
+
+tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
+t_vlmax, dest, t_zero);
+
+tcg_temp_free_i64(t_vlmax);
+tcg_temp_free_i64(t_zero);
+tcg_temp_free_i64(t_idx);
+}
+
+static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
+ int vreg, int idx)
+{
+load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+static bool trans_vext_x_v(DisasContext *s, arg_r *a)
+{
+TCGv_i64 tmp = tcg_temp_new_i64();
+TCGv dest = tcg_temp_new();
+
+if (a->rs1 == 0) {
+/* Special case vmv.x.s rd, vs2. */
+vec_element_loadi(s, tmp, a->rs2, 0);
+} else {
+/* This instruction ignores LMUL and vector register groups */
+int vlmax = s->vlen >> (3 + s->sew);
+vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
+}
+tcg_gen_trunc_i64_tl(dest, tmp);
+gen_set_gpr(a->rd, dest);
+
+tcg_temp_free(dest);
+tcg_temp_free_i64(tmp);
+return true;
+}
--
2.23.0
[PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line
Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
"-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".
vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default value is 64 bit.
vext_spec is the vector specification version, default value is v0.7.1.
These properties can be specified with other values.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 43 +++
target/riscv/cpu.h | 4 +++-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1af79404fa..33483acd25 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -457,6 +457,45 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+if (cpu->cfg.ext_v) {
+target_misa |= RVV;
+if (!is_power_of_2(cpu->cfg.vlen)) {
+error_setg(errp,
+"Vector extension VLEN must be power of 2");
+return;
+}
+if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+error_setg(errp,
+"Vector extension implementation only supports VLEN "
+"in the range [128, %d]", RV_VLEN_MAX);
+return;
+}
+if (!is_power_of_2(cpu->cfg.elen)) {
+error_setg(errp,
+"Vector extension ELEN must be power of 2");
+return;
+}
+if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
+error_setg(errp,
+"Vector extension implementation only supports ELEN "
+"in the range [8, 64]");
+return;
+}
+if (cpu->cfg.vext_spec) {
+if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
+vext_version = VEXT_VERSION_0_07_1;
+} else {
+error_setg(errp,
+ "Unsupported vector spec version '%s'",
+ cpu->cfg.vext_spec);
+return;
+}
+} else {
+qemu_log("vector verison is not specified, "
+"use the default value v0.7.1\n");
+}
+set_vext_version(env, vext_version);
+}
set_misa(env, RVXLEN | target_misa);
}
@@ -496,10 +535,14 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ad51c6580..eef20ca6e5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -92,7 +92,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
-#define RV_VLEN_MAX 512
+#define RV_VLEN_MAX 256
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
@@ -279,12 +279,14 @@ typedef struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+bool ext_v;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
char *priv_spec;
char *user_spec;
+char *vext_spec;
uint16_t vlen;
uint16_t elen;
bool mmu;
--
2.23.0
[PATCH v9 52/61] target/riscv: set-X-first mask bit
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 28 +++
target/riscv/vector_helper.c| 63 +
4 files changed, 98 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e78298e479..ae93b6018d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1099,3 +1099,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env,
i32)
DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vmsof_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4c7706561a..b2bc6ab3dd 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -555,6 +555,9 @@ vmornot_mm 011100 - . . 010 . 1010111 @r
vmxnor_mm 01 - . . 010 . 1010111 @r
vmpopc_m010100 . . - 010 . 1010111 @r2_vm
vmfirst_m 010101 . . - 010 . 1010111 @r2_vm
+vmsbf_m 010110 . . 1 010 . 1010111 @r2_vm
+vmsif_m 010110 . . 00011 010 . 1010111 @r2_vm
+vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 735ae8377e..3b59170bed 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2453,3 +2453,31 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
}
return false;
}
+
+/* vmsbf.m set-before-first mask bit */
+/* vmsif.m set-includ-first mask bit */
+/* vmsof.m set-only-first mask bit */
+#define GEN_M_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+if (vext_check_isa_ill(s)) { \
+uint32_t data = 0; \
+gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
+TCGLabel *over = gen_new_label(); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), vreg_ofs(s, a->rs2),\
+ cpu_env, 0, s->vlen / 8, data, fn); \
+gen_set_label(over); \
+return true; \
+} \
+return false; \
+}
+
+GEN_M_TRANS(vmsbf_m)
+GEN_M_TRANS(vmsif_m)
+GEN_M_TRANS(vmsof_m)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d178ed4c0b..6a579a6300 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4581,3 +4581,66 @@ target_ulong HELPER(vmfirst_m)(void *v0, void *vs2,
CPURISCVState *env,
}
return -1LL;
}
+
+enum set_mask_type {
+ONLY_FIRST = 1,
+INCLUDE_FIRST,
+BEFORE_FIRST,
+};
+
+static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc, enum set_mask_type type)
+{
+uint32_t mlen = vext_mlen(desc);
+uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;
+uint32_t vm = vext_vm(desc);
+uint32_t vl = env->vl;
+int i;
+bool first_mask_bit = false;
+
+for (i = 0; i < vl; i++) {
+if (!vm && !vext_elem_mask(v0, mlen, i)) {
+continue;
+}
+/* write a zero to all following active elements */
+if (first_mask_bit) {
+vext_set_elem_mask(vd, mlen, i, 0);
+continue;
+}
+if (vext_elem_mask(vs2, mlen, i)) {
+first_mask_bit = true;
+if (type == BEFORE_FIRST) {
+vext_set_elem_mask(vd, mlen, i, 0);
+} else {
+vext_set_elem_mask(vd, mlen, i, 1);
+}
+} else {
+if (type == ONLY_FIRST) {
+vext_set_elem_mask(vd, mlen, i, 0);
+} else {
+vext_set_elem_mask(vd, mlen, i, 1);
+}
+}
+}
+for (; i < vlmax;
[PATCH v9 50/61] target/riscv: vector mask population count vmpopc
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 20
4 files changed, 55 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9bb4d8efd5..7ae41ebc2c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1095,3 +1095,5 @@ DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a4128c26a0..decb7f773f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -553,6 +553,7 @@ vmor_mm 011010 - . . 010 . 1010111 @r
vmnor_mm00 - . . 010 . 1010111 @r
vmornot_mm 011100 - . . 010 . 1010111 @r
vmxnor_mm 01 - . . 010 . 1010111 @r
+vmpopc_m010100 . . - 010 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 13e2c31421..d1c8c6a11f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2389,3 +2389,35 @@ GEN_MM_TRANS(vmor_mm)
GEN_MM_TRANS(vmnor_mm)
GEN_MM_TRANS(vmornot_mm)
GEN_MM_TRANS(vmxnor_mm)
+
+/* Vector mask population count vmpopc */
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+{
+if (vext_check_isa_ill(s)) {
+TCGv_ptr src2, mask;
+TCGv dst;
+TCGv_i32 desc;
+uint32_t data = 0;
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+data = FIELD_DP32(data, VDATA, VM, a->vm);
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+mask = tcg_temp_new_ptr();
+src2 = tcg_temp_new_ptr();
+dst = tcg_temp_new();
+desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
+tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
+gen_set_gpr(a->rd, dst);
+
+tcg_temp_free_ptr(mask);
+tcg_temp_free_ptr(src2);
+tcg_temp_free(dst);
+tcg_temp_free_i32(desc);
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 54c1b2e739..f572388981 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4542,3 +4542,23 @@ GEN_VEXT_MASK_VV(vmor_mm, DO_OR)
GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
+
+/* Vector mask population count vmpopc */
+target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
+{
+target_ulong cnt = 0;
+uint32_t mlen = vext_mlen(desc);
+uint32_t vm = vext_vm(desc);
+uint32_t vl = env->vl;
+int i;
+
+for (i = 0; i < vl; i++) {
+if (vm || vext_elem_mask(v0, mlen, i)) {
+if (vext_elem_mask(vs2, mlen, i)) {
+cnt++;
+}
+}
+}
+return cnt;
+}
--
2.23.0
[PATCH v9 02/61] target/riscv: implementation-defined constant parameters
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.h | 5 +
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3a6d202d03..1af79404fa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -106,6 +106,11 @@ static void set_priv_version(CPURISCVState *env, int
priv_ver)
env->priv_ver = priv_ver;
}
+static void set_vext_version(CPURISCVState *env, int vext_ver)
+{
+env->vext_ver = vext_ver;
+}
+
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
@@ -361,6 +366,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = >env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -384,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
+set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0018a79fa3..302e0859a0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,6 +78,8 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define VEXT_VERSION_0_07_1 0x0701
+
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
@@ -113,6 +115,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -275,6 +278,8 @@ typedef struct RISCVCPU {
char *priv_spec;
char *user_spec;
+uint16_t vlen;
+uint16_t elen;
bool mmu;
bool pmp;
} cfg;
--
2.23.0
[PATCH v9 04/61] target/riscv: add vector configure instruction
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 63 +---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 79 +
target/riscv/translate.c| 17 +-
target/riscv/vector_helper.c| 53 +
7 files changed, 209 insertions(+), 12 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ff651f69f6..ff38df6219 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o
gdbstub.o
+obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o
vector_helper.o gdbstub.o
obj-$(CONFIG_SOFTMMU) += pmp.o
ifeq ($(CONFIG_SOFTMMU),y)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 302e0859a0..0ad51c6580 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -21,6 +21,7 @@
#define RISCV_CPU_H
#include "hw/core/cpu.h"
+#include "hw/registerfields.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
@@ -93,6 +94,12 @@ typedef struct CPURISCVState CPURISCVState;
#define RV_VLEN_MAX 512
+FIELD(VTYPE, VLMUL, 0, 2)
+FIELD(VTYPE, VSEW, 2, 3)
+FIELD(VTYPE, VEDIV, 5, 2)
+FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
@@ -352,19 +359,62 @@ void riscv_cpu_set_fflags(CPURISCVState *env,
target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+typedef CPURISCVState CPUArchState;
+typedef RISCVCPU ArchCPU;
+#include "exec/cpu-all.h"
+
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
+FIELD(TB_FLAGS, LMUL, 3, 2)
+FIELD(TB_FLAGS, SEW, 5, 3)
+FIELD(TB_FLAGS, VILL, 8, 1)
+
+/*
+ * A simplification for VLMAX
+ * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
+ * = (VLEN << LMUL) / (8 << SEW)
+ * = (VLEN << LMUL) >> (SEW + 3)
+ * = VLEN >> (SEW + 3 - LMUL)
+ */
+static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
+{
+uint8_t sew, lmul;
+
+sew = FIELD_EX64(vtype, VTYPE, VSEW);
+lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
+return cpu->cfg.vlen >> (sew + 3 - lmul);
+}
+
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-target_ulong *cs_base, uint32_t *flags)
+target_ulong *cs_base, uint32_t
*pflags)
{
+uint32_t flags = 0;
+
*pc = env->pc;
*cs_base = 0;
+
+if (riscv_has_ext(env, RVV)) {
+uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+flags = FIELD_DP32(flags, TB_FLAGS, VILL,
+FIELD_EX64(env->vtype, VTYPE, VILL));
+flags = FIELD_DP32(flags, TB_FLAGS, SEW,
+FIELD_EX64(env->vtype, VTYPE, VSEW));
+flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+FIELD_EX64(env->vtype, VTYPE, VLMUL));
+flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+} else {
+flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+}
+
#ifdef CONFIG_USER_ONLY
-*flags = TB_FLAGS_MSTATUS_FS;
+flags |= TB_FLAGS_MSTATUS_FS;
#else
-*flags = cpu_mmu_index(env, 0);
+flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
-*flags |= env->mstatus & MSTATUS_FS;
+flags |= env->mstatus & MSTATUS_FS;
}
#endif
+*pflags = flags;
}
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
@@ -405,9 +455,4 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations
*ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-typedef CPURISCVState CPUArchState;
-typedef RISCVCPU ArchCPU;
-
-#include "exec/cpu-all.h"
-
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index debb22a480..3c28c7e407 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -76,3 +76,5 @@ DEF_HELPER_2(mret, tl, env, tl)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(tlb_flush, void, env)
#endif
+/* Vector functions */
+DEF_HELPER_3(vsetvl, tl, env, tl, tl)
diff --git a/target/ris
[PATCH v9 03/61] target/riscv: support vector extension csr
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7f64ee1174..8117e8b5a7 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -29,6 +29,14 @@
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC(FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+/* Vector Fixed-Point round model */
+#define FSR_VXRM_SHIFT 9
+#define FSR_VXRM(0x3 << FSR_VXRM_SHIFT)
+
+/* Vector Fixed-Point saturation flag */
+#define FSR_VXSAT_SHIFT 8
+#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
+
/* Control and Status Registers */
/* User Trap Setup */
@@ -48,6 +56,13 @@
#define CSR_FRM 0x002
#define CSR_FCSR0x003
+/* User Vector CSRs */
+#define CSR_VSTART 0x008
+#define CSR_VXSAT 0x009
+#define CSR_VXRM0x00a
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 383be0a955..ac01c835e1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,6 +46,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
+/* loose check condition for fcsr in vector extension */
+if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
+return 0;
+}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -1;
}
@@ -53,6 +57,14 @@ static int fs(CPURISCVState *env, int csrno)
return 0;
}
+static int vs(CPURISCVState *env, int csrno)
+{
+if (env->misa & RVV) {
+return 0;
+}
+return -1;
+}
+
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@@ -154,6 +166,10 @@ static int read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
+if (vs(env, csrno) >= 0) {
+*val |= (env->vxrm << FSR_VXRM_SHIFT)
+| (env->vxsat << FSR_VXSAT_SHIFT);
+}
return 0;
}
@@ -166,10 +182,62 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
+if (vs(env, csrno) >= 0) {
+env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
+env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
+}
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
+static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vtype;
+return 0;
+}
+
+static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vl;
+return 0;
+}
+
+static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vxrm;
+return 0;
+}
+
+static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vxrm = val;
+return 0;
+}
+
+static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vxsat;
+return 0;
+}
+
+static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vxsat = val;
+return 0;
+}
+
+static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
+{
+*val = env->vstart;
+return 0;
+}
+
+static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
+{
+env->vstart = val;
+return 0;
+}
+
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1183,7 +1251,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] = { fs, read_frm, write_frm },
[CSR_FCSR] ={ fs, read_fcsr,write_fcsr},
-
+/* Vector CSRs */
+[CSR_VSTART] = { vs, read_vstart, write_vstart },
+[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
+[CSR_VXRM] ={ vs, read_vxrm,write_vxrm},
+[CSR_VL] = { vs, read_vl },
+[CSR_VTYPE] = { vs, read_vtype
[PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 +++ target/riscv/vector_helper.c| 137 4 files changed, 294 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 608704850a..186d72a2aa 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -343,3 +343,36 @@ DEF_HELPER_6(vwadd_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwsub_wx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwsub_wx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwsub_wx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vadc_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vadc_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vadc_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vadc_vvm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsbc_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsbc_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsbc_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsbc_vvm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadc_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadc_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadc_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadc_vvm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsbc_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsbc_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsbc_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsbc_vvm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vadc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vadc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vadc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vadc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsbc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsbc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4bdbfd16fa..022c8ea18b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -70,6 +70,7 @@ @r2_nfvm ... ... vm:1 . . ... . ... %nf %rs1 %rd @r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd @r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd +@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd @r_wdvm . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd @r2_zimm . zimm:11 . ... . ... %rs1 %rd @@ -300,6 +301,16 @@ vwsubu_wv 110110 . . . 010 . 1010111 @r_vm vwsubu_wx 110110 . . . 110 . 1010111 @r_vm vwsub_wv110111 . . . 010 . 1010111 @r_vm vwsub_wx110111 . . . 110 . 1010111 @r_vm +vadc_vvm01 1 . . 000 . 1010111 @r_vm_1 +vadc_vxm01 1 . . 100 . 1010111 @r_vm_1 +vadc_vim01 1 . . 011 . 1010111 @r_vm_1 +vmadc_vvm 010001 1 . . 000 . 1010111 @r_vm_1 +vmadc_vxm 010001 1 . . 100 . 1010111 @r_vm_1 +vmadc_vim 010001 1 . . 011 . 1010111 @r_vm_1 +vsbc_vvm010010 1 . . 000 . 1010111 @r_vm_1 +vsbc_vxm010010 1 . . 100 . 1010111 @r_vm_1 +vmsbc_vvm 010011 1 . . 000 . 1010111 @r_vm_1 +vmsbc_vxm 010011 1 . . 100 . 1010111 @r_vm_1 vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 7a14b64c3d..6fe2f071e6 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1249,3 +1249,116 @@ GEN_OPIWX_WIDEN_TRANS(vwaddu_wx) GEN_OPIWX_WIDEN_TRANS(vwadd_wx) GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) GEN_OPIWX_WIDEN_TRANS(vwsub_wx) + +/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ +/* OPIVV without GVEC IR */ +#define GEN_OPIVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext
[PATCH v9 16/61] target/riscv: vector integer comparison instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c| 123 4 files changed, 246 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 0222aa863d..a1fc7cc53e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -439,3 +439,60 @@ DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsne_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsltu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmslt_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsleu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmsle_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmseq_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsne_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsltu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmslt_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsleu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsle_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgtu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 89fd2aa4e2..df6181980d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -335,6 +335,26 @@ vnsrl_vi101100 . . . 011 . 1010111 @r_vm vnsra_vv101101 . . . 000 . 1010111 @r_vm vnsra_vx101101 . . . 100 . 1010111 @r_vm vnsra_vi101101 . . . 011 . 1010111 @r_vm +vmseq_vv011000 . . . 000 . 1010111 @r_vm +vmseq_vx011000 . . . 100 . 1010111 @r_vm +vmseq_vi011000 . . . 011 . 1010111 @r_vm +vmsne_vv011001 . . . 000 . 1010111 @r_vm +vmsne_vx011001 . . . 100 . 1010111 @r_vm
[PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88 + 4 files changed, 139 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e5c3a66903..08c2544b20 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -614,3 +614,36 @@ DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmacc_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsac_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ae7cfa3e28..b49b60aea1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -385,6 +385,14 @@ vwmulsu_vv 111010 . . . 010 . 1010111 @r_vm vwmulsu_vx 111010 . . . 110 . 1010111 @r_vm vwmul_vv111011 . . . 010 . 1010111 @r_vm vwmul_vx111011 . . . 110 . 1010111 @r_vm +vmacc_vv101101 . . . 010 . 1010111 @r_vm +vmacc_vx101101 . . . 110 . 1010111 @r_vm +vnmsac_vv 10 . . . 010 . 1010111 @r_vm +vnmsac_vx 10 . . . 110 . 1010111 @r_vm +vmadd_vv101001 . . . 010 . 1010111 @r_vm +vmadd_vx101001 . . . 110 . 1010111 @r_vm +vnmsub_vv 101011 . . . 010 . 1010111 @r_vm +vnmsub_vx 101011 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index fbdd1b43d6..dc122eb2e5 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1599,3 +1599,13 @@ GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) GEN_OPIVX_WIDEN_TRANS(vwmul_vx) GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +GEN_OPIVV_TRANS(vmacc_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsac_vv, opivv_check) +GEN_OPIVV_TRANS(vmadd_vv, opivv_check) +GEN_OPIVV_TRANS(vnmsub_vv, opivv_check) +GEN_OPIVX_TRANS(vmacc_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) +GEN_OPIVX_TRANS(vmadd_vx, opivx_check) +GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 116cc9f092..e787e00b01 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1891,3 +1891,91 @@ GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq) + +/* Vector
[PATCH v9 23/61] target/riscv: vector integer merge and move instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 113
target/riscv/vector_helper.c| 88 ++
4 files changed, 225 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1a9495ceac..279b2e049f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -669,3 +669,20 @@ DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_b, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_h, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_w, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_d, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9735ac3565..adb76956c9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -71,6 +71,7 @@
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd
+@r_vm_0 .. . . . ... . ... vm=0 %rs2 %rs1 %rd
@r_wdvm . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
@r2_zimm . zimm:11 . ... . ... %rs1 %rd
@@ -400,6 +401,12 @@ vwmacc_vx 01 . . . 110 . 1010111
@r_vm
vwmaccsu_vv 10 . . . 010 . 1010111 @r_vm
vwmaccsu_vx 10 . . . 110 . 1010111 @r_vm
vwmaccus_vx 11 . . . 110 . 1010111 @r_vm
+vmv_v_v 010111 1 0 . 000 . 1010111 @r2
+vmv_v_x 010111 1 0 . 100 . 1010111 @r2
+vmv_v_i 010111 1 0 . 011 . 1010111 @r2
+vmerge_vvm 010111 0 . . 000 . 1010111 @r_vm_0
+vmerge_vxm 010111 0 . . 100 . 1010111 @r_vm_0
+vmerge_vim 010111 0 . . 011 . 1010111 @r_vm_0
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 3093191edc..d726995f84 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1618,3 +1618,116 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
+
+/* Vector Integer Merge and Move Instructions */
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs1, false)) {
+
+if (s->vl_eq_vlmax) {
+tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+} else {
+uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+static gen_helper_gvec_2_ptr * const fns[4] = {
+gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+};
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+ cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+gen_set_label(over);
+}
+return true;
+}
+return false;
+}
+
+typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
+static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false)) {
+
+TCGv s1;
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+s1 = tcg_temp_new();
+
[PATCH v9 39/61] target/riscv: vector floating-point compare instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Richard Henderson
---
target/riscv/helper.h | 37 +
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 35 +
target/riscv/vector_helper.c| 174
4 files changed, 258 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d6e7ce57be..bedd4d0114 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -953,3 +953,40 @@ DEF_HELPER_6(vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vmfeq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfeq_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfeq_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfne_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfne_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfne_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmflt_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmflt_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmflt_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfle_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfle_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfle_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmfeq_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfeq_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfeq_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfne_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfne_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfne_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmflt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmflt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmflt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfle_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfle_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfle_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfgt_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfgt_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ce2f497ed2..b0f1c54d53 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -500,6 +500,18 @@ vfsgnjn_vv 001001 . . . 001 . 1010111
@r_vm
vfsgnjn_vf 001001 . . . 101 . 1010111 @r_vm
vfsgnjx_vv 001010 . . . 001 . 1010111 @r_vm
vfsgnjx_vf 001010 . . . 101 . 1010111 @r_vm
+vmfeq_vv011000 . . . 001 . 1010111 @r_vm
+vmfeq_vf011000 . . . 101 . 1010111 @r_vm
+vmfne_vv011100 . . . 001 . 1010111 @r_vm
+vmfne_vf011100 . . . 101 . 1010111 @r_vm
+vmflt_vv011011 . . . 001 . 1010111 @r_vm
+vmflt_vf011011 . . . 101 . 1010111 @r_vm
+vmfle_vv011001 . . . 001 . 1010111 @r_vm
+vmfle_vf011001 . . . 101 . 1010111 @r_vm
+vmfgt_vf011101 . . . 101 . 1010111 @r_vm
+vmfge_vf01 . . . 101 . 1010111 @r_vm
+vmford_vv 011010 . . . 001 . 1010111 @r_vm
+vmford_vf 011010 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 6170fce05d..11473b8f72 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2146,3 +2146,38 @@ GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
+
+/* Vector Floating-Point Compare Instructions */
+static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_r
[PATCH v9 49/61] target/riscv: vector mask-register logical instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 35 ++
target/riscv/vector_helper.c| 40 +
4 files changed, 92 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6b932b444d..9bb4d8efd5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1086,3 +1086,12 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 526a964d28..a4128c26a0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -545,6 +545,14 @@ vfredmin_vs 000101 . . . 001 . 1010111
@r_vm
vfredmax_vs 000111 . . . 001 . 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
vfwredsum_vs1100-1 . . . 001 . 1010111 @r_vm
+vmand_mm011001 - . . 010 . 1010111 @r
+vmnand_mm 011101 - . . 010 . 1010111 @r
+vmandnot_mm 011000 - . . 010 . 1010111 @r
+vmxor_mm011011 - . . 010 . 1010111 @r
+vmor_mm 011010 - . . 010 . 1010111 @r
+vmnor_mm00 - . . 010 . 1010111 @r
+vmornot_mm 011100 - . . 010 . 1010111 @r
+vmxnor_mm 01 - . . 010 . 1010111 @r
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 1f1559b0bd..13e2c31421 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2354,3 +2354,38 @@ GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+
+/*
+ *** Vector Mask Operations
+ */
+
+/* Vector Mask-Register Logical Instructions */
+#define GEN_MM_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a)\
+{ \
+if (vext_check_isa_ill(s)) { \
+uint32_t data = 0; \
+gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+TCGLabel *over = gen_new_label(); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1),\
+ vreg_ofs(s, a->rs2), cpu_env, 0,\
+ s->vlen / 8, data, fn); \
+gen_set_label(over); \
+return true; \
+} \
+return false; \
+}
+
+GEN_MM_TRANS(vmand_mm)
+GEN_MM_TRANS(vmnand_mm)
+GEN_MM_TRANS(vmandnot_mm)
+GEN_MM_TRANS(vmxor_mm)
+GEN_MM_TRANS(vmor_mm)
+GEN_MM_TRANS(vmnor_mm)
+GEN_MM_TRANS(vmornot_mm)
+GEN_MM_TRANS(vmxnor_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e30f8f83d3..54c1b2e739 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4502,3 +4502,43 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void
*vs1,
*((uint64_t *)vd) = s1;
clearq(vd, 1, sizeof(uint64_t), tot);
}
+
+/*
+ *** Vector Mask Operations
+ */
+/* Vector Mask-Register Logical Instructions */
+#define GEN_VEXT_MASK_VV(NAME, OP)\
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+
[PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h | 12
target/riscv/translate.c | 3 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 80569f0d44..0018a79fa3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -59,6 +59,7 @@
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
+#define RVV RV('V')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
@@ -88,9 +89,20 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
+#define RV_VLEN_MAX 512
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
+
+/* vector coprocessor state. */
+uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
+target_ulong vxrm;
+target_ulong vxsat;
+target_ulong vl;
+target_ulong vstart;
+target_ulong vtype;
+
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 43bf7e39a6..b71b7e4bc2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc;
+static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -886,6 +886,7 @@ void riscv_translate_init(void)
}
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
+cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
--
2.23.0
[PATCH v9 05/61] target/riscv: add an internals.h header
The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/internals.h | 24 1 file changed, 24 insertions(+) create mode 100644 target/riscv/internals.h diff --git a/target/riscv/internals.h b/target/riscv/internals.h new file mode 100644 index 00..22a49af413 --- /dev/null +++ b/target/riscv/internals.h @@ -0,0 +1,24 @@ +/* + * QEMU RISC-V CPU -- internal functions and types + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef RISCV_CPU_INTERNALS_H +#define RISCV_CPU_INTERNALS_H + +#include "hw/registerfields.h" + +#endif -- 2.23.0
[PATCH v9 11/61] target/riscv: vector widening integer add and subtract
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 +++ target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 186 target/riscv/vector_helper.c| 111 ++ 4 files changed, 362 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index f791f2dbc6..608704850a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -294,3 +294,52 @@ DEF_HELPER_FLAGS_4(vec_rsubs8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vec_rsubs16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vec_rsubs32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vec_rsubs64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + +DEF_HELPER_6(vwaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwaddu_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsubu_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwaddu_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwaddu_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwaddu_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsubu_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwadd_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsub_wx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d1034a0e61..4bdbfd16fa 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -284,6 +284,22 @@ vsub_vv 10 . . . 000 . 1010111 @r_vm vsub_vx 10 . . . 100 . 1010111 @r_vm vrsub_vx11 . . . 100 . 1010111 @r_vm vrsub_vi11 . . . 011 . 1010111 @r_vm +vwaddu_vv 11 . . . 010 . 1010111 @r_vm +vwaddu_vx 11 . . . 110 . 1010111 @r_vm +vwadd_vv110001 . . . 010 . 1010111 @r_vm +vwadd_vx110001 . . . 110 . 1010111 @r_vm +vwsubu_vv 110010 . . . 010 . 1010111 @r_vm +vwsubu_vx 110010 . . . 110 . 1010111 @r_vm +vwsub_vv110011 . . . 010 . 1010111 @r_vm +vwsub_vx110011 . . . 110 . 1010111 @r_vm +vwaddu_wv 110100 . . . 010 . 1010111 @r_vm +vwaddu_wx 110100 . . . 110 . 1010111 @r_vm +vwadd_wv110101 . . . 010 . 1010111 @r_vm +vwadd_wx110101 . . . 110
[PATCH v9 17/61] target/riscv: vector integer min/max instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 71 + 4 files changed, 122 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a1fc7cc53e..32f4c76b34 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -496,3 +496,36 @@ DEF_HELPER_6(vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vminu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index df6181980d..aafbdc6be7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -355,6 +355,14 @@ vmsgtu_vx 00 . . . 100 . 1010111 @r_vm vmsgtu_vi 00 . . . 011 . 1010111 @r_vm vmsgt_vx01 . . . 100 . 1010111 @r_vm vmsgt_vi01 . . . 011 . 1010111 @r_vm +vminu_vv000100 . . . 000 . 1010111 @r_vm +vminu_vx000100 . . . 100 . 1010111 @r_vm +vmin_vv 000101 . . . 000 . 1010111 @r_vm +vmin_vx 000101 . . . 100 . 1010111 @r_vm +vmaxu_vv000110 . . . 000 . 1010111 @r_vm +vmaxu_vx000110 . . . 100 . 1010111 @r_vm +vmax_vv 000111 . . . 000 . 1010111 @r_vm +vmax_vx 000111 . . . 100 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 8fa3d5ecb0..cbcb40e682 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1561,3 +1561,13 @@ GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) + +/* Vector Integer Min/Max Instructions */ +GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) +GEN_OPIVV_GVEC_TRANS(vmin_vv, smin) +GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax) +GEN_OPIVV_GVEC_TRANS(vmax_vv, smax) +GEN_OPIVX_TRANS(vminu_vx, opivx_check) +GEN_OPIVX_TRANS(vmin_vx, opivx_check) +GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) +GEN_OPIVX_TRANS(vmax_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 07e474781c..cb41daa3ac 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -855,6 +855,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t
[PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 49 + 4 files changed, 77 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 73fc7a5a00..fa1558179a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -830,3 +830,19 @@ DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_6(vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 68e9448842..16fd938261 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -456,6 +456,11 @@ vfwsub_vv 110010 . . . 001 . 1010111 @r_vm vfwsub_vf 110010 . . . 101 . 1010111 @r_vm vfwsub_wv 110110 . . . 001 . 1010111 @r_vm vfwsub_wf 110110 . . . 101 . 1010111 @r_vm +vfmul_vv100100 . . . 001 . 1010111 @r_vm +vfmul_vf100100 . . . 101 . 1010111 @r_vm +vfdiv_vv10 . . . 001 . 1010111 @r_vm +vfdiv_vf10 . . . 101 . 1010111 @r_vm +vfrdiv_vf 11 . . . 101 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index bee4d4cb76..be60115801 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2050,3 +2050,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) + +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) +GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) +GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) +GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b65ef51116..ea807ef731 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3361,3 +3361,52 @@ RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl) GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq) + +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) +RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) +RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) +GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) +RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) +RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) +GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq) + +RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) +RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) +RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) +RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) +RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) +GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq) + +static uint16_t
[PATCH v9 25/61] target/riscv: vector single-width averaging add and subtract
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 100
4 files changed, 129 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9416ebb090..32d549ce36 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -719,3 +719,20 @@ DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c9a4050adc..e617d7bd60 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -417,6 +417,11 @@ vssubu_vv 100010 . . . 000 . 1010111
@r_vm
vssubu_vx 100010 . . . 100 . 1010111 @r_vm
vssub_vv100011 . . . 000 . 1010111 @r_vm
vssub_vx100011 . . . 100 . 1010111 @r_vm
+vaadd_vv100100 . . . 000 . 1010111 @r_vm
+vaadd_vx100100 . . . 100 . 1010111 @r_vm
+vaadd_vi100100 . . . 011 . 1010111 @r_vm
+vasub_vv100110 . . . 000 . 1010111 @r_vm
+vasub_vx100110 . . . 100 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 4d5eae8dde..ed1ee0f1b5 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1747,3 +1747,10 @@ GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
+
+/* Vector Single-Width Averaging Add and Subtract */
+GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasub_vx, opivx_check)
+GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3d4212ea4a..ada95ab1e7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2497,3 +2497,103 @@ GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Averaging Add and Subtract */
+static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
+{
+uint8_t d = extract64(v, shift, 1);
+uint8_t d1;
+uint64_t D1, D2;
+
+if (shift == 0 || shift > 64) {
+return 0;
+}
+
+d1 = extract64(v, shift - 1, 1);
+D1 = extract64(v, 0, shift);
+if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */
+return d1;
+} else if (vxrm == 1) { /* round-to-nearest-even */
+if (shift > 1) {
+D2 = extract64(v, 0, shift - 1);
+return d1 & ((D2 != 0) | d);
+} else {
+return d1 & d;
+}
+} else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */
+return !d & (D1 != 0);
+}
+return 0; /* round-down (truncate) */
+}
+
+static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t
b)
+{
+int64_t res = (int64_t)a + b;
+uint8_t round = get_round(vxrm, res, 1);
+
+return (res >> 1) + round;
+}
+
+static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t
b)
+{
+int64_t res = a + b;
+uint8_t round = get_round(vxrm, res, 1);
+int64_t over = (res ^ a) & (res ^ b) & INT64_M
[PATCH v9 31/61] target/riscv: vector widening floating-point add/subtract instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 149
target/riscv/vector_helper.c| 83 +
4 files changed, 257 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3031a941c2..73fc7a5a00 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -813,3 +813,20 @@ DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c8e3f10162..68e9448842 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -448,6 +448,14 @@ vfadd_vf00 . . . 101 . 1010111
@r_vm
vfsub_vv10 . . . 001 . 1010111 @r_vm
vfsub_vf10 . . . 101 . 1010111 @r_vm
vfrsub_vf 100111 . . . 101 . 1010111 @r_vm
+vfwadd_vv 11 . . . 001 . 1010111 @r_vm
+vfwadd_vf 11 . . . 101 . 1010111 @r_vm
+vfwadd_wv 110100 . . . 001 . 1010111 @r_vm
+vfwadd_wf 110100 . . . 101 . 1010111 @r_vm
+vfwsub_vv 110010 . . . 001 . 1010111 @r_vm
+vfwsub_vf 110010 . . . 101 . 1010111 @r_vm
+vfwsub_wv 110110 . . . 001 . 1010111 @r_vm
+vfwsub_wf 110110 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 7461e86de8..bee4d4cb76 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1901,3 +1901,152 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
GEN_OPFVF_TRANS(vfadd_vf, opfvf_check)
GEN_OPFVF_TRANS(vfsub_vf, opfvf_check)
GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Add/Subtract Instructions */
+static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+vext_check_reg(s, a->rd, true) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_reg(s, a->rs1, false) &&
+vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
+ 1 << s->lmul) &&
+(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+/* OPFVV with WIDEN */
+#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{\
+if (CHECK(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_4_ptr * const fns[2] = { \
+gen_helper_##NAME##_h, gen_helper_##NAME##_w,\
+}; \
+TCGLabel *over = gen_new_label();\
+gen_set_rm(s, 7);\
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);\
+ \
+dat
[PATCH v9 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 91 +
4 files changed, 126 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5cd1694412..edf963e787 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -900,3 +900,20 @@ DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c42bcd141c..56bfd4a919 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -479,6 +479,14 @@ vfmsub_vv 101010 . . . 001 . 1010111
@r_vm
vfmsub_vf 101010 . . . 101 . 1010111 @r_vm
vfnmsub_vv 101011 . . . 001 . 1010111 @r_vm
vfnmsub_vf 101011 . . . 101 . 1010111 @r_vm
+vfwmacc_vv 00 . . . 001 . 1010111 @r_vm
+vfwmacc_vf 00 . . . 101 . 1010111 @r_vm
+vfwnmacc_vv 01 . . . 001 . 1010111 @r_vm
+vfwnmacc_vf 01 . . . 101 . 1010111 @r_vm
+vfwmsac_vv 10 . . . 001 . 1010111 @r_vm
+vfwmsac_vf 10 . . . 101 . 1010111 @r_vm
+vfwnmsac_vv 11 . . . 001 . 1010111 @r_vm
+vfwnmsac_vf 11 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 439bfc0469..945c9424ba 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2079,3 +2079,13 @@ GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
+GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d3ad4aa8f1..7abdc2b7d8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3683,3 +3683,94 @@ RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq)
+
+/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
+static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+{
+return float32_muladd(float16_to_float32(a, true, s),
+float16_to_float32(b, true, s), d, 0, s);
+}
+
+static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
+{
+return float64_muladd(float32_to_float64(a, s),
+float32_to_float64(b, s), d, 0, s);
+}
+
+RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
+RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
+GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl)
+GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq)
+RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
+RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
+GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl)
+GEN_VEXT_VF(vfwmacc_vf_w, 4
[PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 251 4 files changed, 334 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5b3340a4af..5cd1694412 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -851,3 +851,52 @@ DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_6(vfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1d963f0b8a..c42bcd141c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -463,6 +463,22 @@ vfdiv_vf10 . . . 101 . 1010111 @r_vm vfrdiv_vf 11 . . . 101 . 1010111 @r_vm vfwmul_vv 111000 . . . 001 . 1010111 @r_vm vfwmul_vf 111000 . . . 101 . 1010111 @r_vm +vfmacc_vv 101100 . . . 001 . 1010111 @r_vm +vfnmacc_vv 101101 . . . 001 . 1010111 @r_vm +vfnmacc_vf 101101 . . . 101 . 1010111 @r_vm +vfmacc_vf 101100 . . . 101 . 1010111 @r_vm +vfmsac_vv 101110 . . . 001 . 1010111 @r_vm +vfmsac_vf 101110 . . . 101 . 1010111 @r_vm +vfnmsac_vv 10 . . . 001 . 1010111 @r_vm +vfnmsac_vf 10 . . . 101 . 1010111 @r_vm +vfmadd_vv 101000 . . . 001 . 1010111 @r_vm +vfmadd_vf 101000 . . . 101 . 1010111 @r_vm +vfnmadd_vv 101001 . . . 001 . 1010111 @r_vm +vfnmadd_vf 101001 . . . 101
[PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33 + 4 files changed, 56 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 21054cc957..05f8fb5ffc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -998,3 +998,16 @@ DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 14cb4e2e66..53562c6663 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -515,6 +515,10 @@ vmford_vf 011010 . . . 101 . 1010111 @r_vm vfclass_v 100011 . . 1 001 . 1010111 @r2_vm vfmerge_vfm 010111 0 . . 101 . 1010111 @r_vm_0 vfmv_v_f010111 1 0 . 101 . 1010111 @r2 +vfcvt_xu_f_v100010 . . 0 001 . 1010111 @r2_vm +vfcvt_x_f_v 100010 . . 1 001 . 1010111 @r2_vm +vfcvt_f_xu_v100010 . . 00010 001 . 1010111 @r2_vm +vfcvt_f_x_v 100010 . . 00011 001 . 1010111 @r2_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 51ee83255e..a2a851de87 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -,3 +,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) } return false; } + +/* Single-Width Floating-Point/Integer Type-Convert Instructions */ +GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5a0dd9304d..354d69b800 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4218,3 +4218,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl) GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq) + +/* Single-Width Floating-Point/Integer Type-Convert Instructions */ +/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ +RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16) +RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32) +RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq) + +/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */ +RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16) +RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32) +RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64) +GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq) + +/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */ +RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16) +RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32) +RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq) + +/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */ +RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16) +RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32) +RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64) +GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl
[PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 74 +
4 files changed, 133 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 82c5d1129e..93a7a303ee 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1033,3 +1033,36 @@ DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmaxu_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmaxu_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmaxu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmaxu_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmax_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredminu_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredminu_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredminu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredminu_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmin_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredand_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredand_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredand_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredand_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredor_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredor_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredor_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredor_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 57ac4de1c2..773b32f0b4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -529,6 +529,14 @@ vfncvt_x_f_v100010 . . 10001 001 . 1010111
@r2_vm
vfncvt_f_xu_v 100010 . . 10010 001 . 1010111 @r2_vm
vfncvt_f_x_v100010 . . 10011 001 . 1010111 @r2_vm
vfncvt_f_f_v100010 . . 10100 001 . 1010111 @r2_vm
+vredsum_vs 00 . . . 010 . 1010111 @r_vm
+vredand_vs 01 . . . 010 . 1010111 @r_vm
+vredor_vs 10 . . . 010 . 1010111 @r_vm
+vredxor_vs 11 . . . 010 . 1010111 @r_vm
+vredminu_vs 000100 . . . 010 . 1010111 @r_vm
+vredmin_vs 000101 . . . 010 . 1010111 @r_vm
+vredmaxu_vs 000110 . . . 010 . 1010111 @r_vm
+vredmax_vs 000111 . . . 010 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 4e4631ac6a..b3920eed23 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2324,3 +2324,21 @@ GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+
+/*
+ *** Vector Reduction Operations
+ */
+/* Vector Single-Width Integer Reduction Instructions */
+static bool reduction_check(DisasContext *s, arg_rmrr *a)
+{
+return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
+}
+
+GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
+GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
+GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
+GEN_OPIVV_TRANS(vredand_vs, reduction_check)
+GEN_OPIVV_TRANS(vredor_vs, reduction_check)
+GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
[PATCH v9 00/61] target/riscv: support vector extension v0.7.1
This patchset implements the vector extension for RISC-V on QEMU.
You can also find the patchset and all *test cases* in
my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v9).
All the test cases are in the directory qemu/tests/riscv/vector/. They are
riscv64 linux user mode programs.
You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh.
Features:
* support specification
riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/)
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* SLEN always equals VLEN.
* element width support 8bit, 16bit, 32bit, 64bit.
Changelog:
v9
* always set dynamic rounding mode for vector float insns.
* bug fix atomic implementation.
* bug fix first-only-fault.
* some small tidy up.
v8
* support different float rounding modes for vector instructions.
* use lastest released TCG GVEC DUP IR.
* set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc.
v7
* move vl == 0 check to translation time by add a global cpu_vl.
* implement vector element inline load and store function by TCG IR.
* based on vec_element_load(store), implement some permutation instructions.
* implement rsubs GVEC IR.
* fixup vsmul, vmfne, vfmerge, vslidedown.
* some other small bugs and indentation errors.
v6
* use gvec_dup Gvec IR to accellerate move and merge.
* a better way to implement fixed point instructions.
* a global check when vl == 0.
* limit some macros to only one inline function call.
* fixup sew error when use Gvec IR.
* fixup bugs for corner cases.
v5
* fixup a bug in tb flags.
v4
* no change
v3
* move check code from execution-time to translation-time
* use a continous memory block for vector register description.
* vector registers as direct fields in RISCVCPUState.
* support VLEN configure from qemu command line.
* support ELEN configure from qemu command line.
* support vector specification version configure from qemu command line.
* probe pages before real load or store access.
* use probe_page_check for no-fault operations in linux user mode.
* generation atomic exit exception when in parallel environment.
* fixup a lot of concrete bugs.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (61):
target/riscv: add vector extension field in CPURISCVState
target/riscv: implementation-defined constant parameters
target/riscv: support vector extension csr
target/riscv: add vector configure instruction
target/riscv: add an internals.h header
target/riscv: add vector stride load and store instructions
target/riscv: add vector index load and store instructions
target/riscv: add fault-only-first unit stride load
target/riscv: add vector amo operations
target/riscv: vector single-width integer add and subtract
target/riscv: vector widening integer add and subtract
target/riscv: vector integer add-with-carry / subtract-with-borrow
instructions
target/riscv: vector bitwise logical instructions
target/riscv: vector single-width bit shift instructions
target/riscv: vector narrowing integer right shift instructions
target/riscv: vector integer comparison instructions
target/riscv: vector integer min/max instructions
target/riscv: vector single-width integer multiply instructions
target/riscv: vector integer divide instructions
target/riscv: vector widening integer multiply instructions
target/riscv: vector single-width integer multiply-add instructions
target/riscv: vector widening integer multiply-add instructions
target/riscv: vector integer merge and move instructions
target/riscv: vector single-width saturating add and subtract
target/riscv: vector single-width averaging add and subtract
target/riscv: vector single-width fractional multiply with rounding
and saturation
target/riscv: vector widening saturating scaled multiply-add
target/riscv: vector single-width scaling shift instructions
target/riscv: vector narrowing fixed-point clip instructions
target/riscv: vector single-width floating-point add/subtract
instructions
target/riscv: vector widening floating-point add/subtract instructions
target/riscv: vector single-width floating-point multiply/divide
instructions
target/riscv: vector widening floating-point multiply
target/riscv: vector single-width floating-point fused multiply-add
instructions
target/riscv: vector widening floating-point fused multiply-add
instructions
target/riscv: vector floating-point square-root instruction
target/riscv: vector floating-point min/max instructions
target/riscv: vector floating-point sign-injection instructions
target/riscv: vector floating-point compare instructions
target/riscv: vector floating-point classify instructions
target/riscv: vector floating-point merge instructions
target
[PATCH v9 07/61] target/riscv: add vector index load and store instructions
Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 35 +++ target/riscv/insn32.decode | 13 +++ target/riscv/insn_trans/trans_rvv.inc.c | 129 target/riscv/vector_helper.c| 116 + 4 files changed, 293 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 87dfa90609..f9b3da60ca 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -183,3 +183,38 @@ DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ef521152c5..bc36df33b5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -241,6 +241,19 @@ vssh_v ... 010 . . . 101 . 0100111 @r_nfvm vssw_v ... 010 . . . 110 . 0100111 @r_nfvm vsse_v ... 010 . . . 111 . 0100111 @r_nfvm +vlxb_v ... 111 . . . 000 . 111 @r_nfvm +vlxh_v ... 111 . . . 101 . 111 @r_nfvm +vlxw_v ... 111 . . . 110 . 111 @r_nfvm +vlxe_v ... 011 . . . 111 . 111 @r_nfvm +vlxbu_v... 011 . . . 000 . 111 @r_nfvm +vlxhu_v... 011 . . . 101 . 111 @r_nfvm +vlxwu_v... 011 . . . 110 . 111 @r_nfvm +# Vector ordered-indexed and unordered-indexed store insns. +vsxb_v ... -11 . . . 000 . 0100111 @r_nfvm +vsxh_v ... -11 . . . 101 . 0100111 @r_nfvm +vsxw_v ... -11 . . . 110 . 0100111 @r_nfvm +vsxe_v ... -11 . . . 111 . 0100111 @r_nfvm + # *** new major opcode OP-V *** vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index f9950ad5a0..c3a79c5232 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -432,3 +432,132 @@ GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) + +/* + *** index load and store + */ +typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, + TCGv_ptr, TCGv_env, TCGv_i32); + +static bool ldst_index_trans
[PATCH v9 10/61] target/riscv: vector single-width integer add and subtract
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 25 ++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 291
target/riscv/vector_helper.c| 183 +++
4 files changed, 509 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 70a4b05f75..f791f2dbc6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -269,3 +269,28 @@ DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vrsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_FLAGS_4(vec_rsubs8, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(vec_rsubs16, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(vec_rsubs32, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+DEF_HELPER_FLAGS_4(vec_rsubs64, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1330703720..d1034a0e61 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -44,6 +44,7 @@
imm rd
shamt rs1 rd
aq rl rs2 rs1 rd
+ vm rd rs1 rs2
vm wd rd rs1 rs2
vm rd rs1 nf
vm rd rs1 rs2 nf
@@ -68,6 +69,7 @@
@r2 ... . . ... . ... %rs1 %rd
@r2_nfvm ... ... vm:1 . . ... . ... %nf %rs1 %rd
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
+@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_wdvm . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd
@r2_zimm . zimm:11 . ... . ... %rs1 %rd
@@ -275,5 +277,13 @@ vamominuw_v 11000 . . . . 110 . 010
@r_wdvm
vamomaxuw_v 11100 . . . . 110 . 010 @r_wdvm
# *** new major opcode OP-V ***
+vadd_vv 00 . . . 000 . 1010111 @r_vm
+vadd_vx 00 . . . 100 . 1010111 @r_vm
+vadd_vi 00 . . . 011 . 1010111 @r_vm
+vsub_vv 10 . . . 000 . 1010111 @r_vm
+vsub_vx 10 . . . 100 . 1010111 @r_vm
+vrsub_vx11 . . . 100 . 1010111 @r_vm
+vrsub_vi11 . . . 011 . 1010111 @r_vm
+
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index a551139207..79b6cd9b4a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -772,3 +772,294 @@ GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
#endif
+
+/*
+ *** Vector Integer Arithmetic Instructions
+ */
+#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_reg(s, a->rs1, false));
+}
+
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+uint32_t, uint32_t, uint32_t);
+
+static inline bool
+do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
+ gen_helper_gvec_4_ptr *fn)
+{
+TCGLabel *over = gen_new_la
[PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 117
4 files changed, 148 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index eb383787a2..f36f840714 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -767,3 +767,20 @@ DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssra_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssrl_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2e0e66bdfa..2ecac3d96d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -431,6 +431,12 @@ vwsmacc_vx 01 . . . 100 . 1010111
@r_vm
vwsmaccsu_vv10 . . . 000 . 1010111 @r_vm
vwsmaccsu_vx10 . . . 100 . 1010111 @r_vm
vwsmaccus_vx11 . . . 100 . 1010111 @r_vm
+vssrl_vv101010 . . . 000 . 1010111 @r_vm
+vssrl_vx101010 . . . 100 . 1010111 @r_vm
+vssrl_vi101010 . . . 011 . 1010111 @r_vm
+vssra_vv101011 . . . 000 . 1010111 @r_vm
+vssra_vx101011 . . . 100 . 1010111 @r_vm
+vssra_vi101011 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 3886b2f45a..0d9e65a194 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1767,3 +1767,11 @@ GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
+
+/* Vector Single-Width Scaling Shift Instructions */
+GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
+GEN_OPIVV_TRANS(vssra_vv, opivv_check)
+GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
+GEN_OPIVX_TRANS(vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d653ec5e2b..c33e845a90 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2909,3 +2909,120 @@ RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4,
vwsmaccus32)
GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
+
+/* Vector Single-Width Scaling Shift Instructions */
+static inline uint8_t
+vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
+{
+uint8_t round, shift = b & 0x7;
+uint8_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint16_t
+vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b)
+{
+uint8_t round, shift = b & 0xf;
+uint16_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint32_t
+vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b)
+{
+uint8_t round, shift = b & 0x1f;
+uint32_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+static inline uint64_t
+vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b)
+{
+uint8_t round, shift = b & 0x3f;
+uint64_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+return res;
+}
+RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
+RVVCALL(OPIVV2_RM, vssrl_vv_h,
[PATCH v9 20/61] target/riscv: vector widening integer multiply instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51 + 4 files changed, 84 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5fd718771c..e5c3a66903 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -595,3 +595,22 @@ DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7fb8f8fad8..ae7cfa3e28 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -379,6 +379,12 @@ vremu_vv100010 . . . 010 . 1010111 @r_vm vremu_vx100010 . . . 110 . 1010111 @r_vm vrem_vv 100011 . . . 010 . 1010111 @r_vm vrem_vx 100011 . . . 110 . 1010111 @r_vm +vwmulu_vv 111000 . . . 010 . 1010111 @r_vm +vwmulu_vx 111000 . . . 110 . 1010111 @r_vm +vwmulsu_vv 111010 . . . 010 . 1010111 @r_vm +vwmulsu_vx 111010 . . . 110 . 1010111 @r_vm +vwmul_vv111011 . . . 010 . 1010111 @r_vm +vwmul_vx111011 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 4b4312fa99..fbdd1b43d6 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1591,3 +1591,11 @@ GEN_OPIVX_TRANS(vdivu_vx, opivx_check) GEN_OPIVX_TRANS(vdiv_vx, opivx_check) GEN_OPIVX_TRANS(vremu_vx, opivx_check) GEN_OPIVX_TRANS(vrem_vx, opivx_check) + +/* Vector Widening Integer Multiply Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aee107a82e..116cc9f092 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -863,6 +863,18 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t +#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t +#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t +#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t +#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t +#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t +#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t +#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t +#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t +#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); @@ -1840,3 +1852,42 @@ GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb) GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh
[PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 205
4 files changed, 243 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e6cae1b59c..eb383787a2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -745,3 +745,25 @@ DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 633f782fbf..2e0e66bdfa 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -424,6 +424,13 @@ vasub_vv100110 . . . 000 . 1010111
@r_vm
vasub_vx100110 . . . 100 . 1010111 @r_vm
vsmul_vv100111 . . . 000 . 1010111 @r_vm
vsmul_vx100111 . . . 100 . 1010111 @r_vm
+vwsmaccu_vv 00 . . . 000 . 1010111 @r_vm
+vwsmaccu_vx 00 . . . 100 . 1010111 @r_vm
+vwsmacc_vv 01 . . . 000 . 1010111 @r_vm
+vwsmacc_vx 01 . . . 100 . 1010111 @r_vm
+vwsmaccsu_vv10 . . . 000 . 1010111 @r_vm
+vwsmaccsu_vx10 . . . 100 . 1010111 @r_vm
+vwsmaccus_vx11 . . . 100 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 23714793df..3886b2f45a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1758,3 +1758,12 @@ GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
+
+/* Vector Widening Saturating Scaled Multiply-Add */
+GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index dd3fc39016..d653ec5e2b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2704,3 +2704,208 @@ GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
+
+/* Vector Widening Saturating Scaled Multiply-Add */
+static inline uint16_t
+vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
+ uint16_t c)
+{
+uint8_t round;
+uint16_t res = (uint16_t)a * b;
+
+round = get_round(vxrm, res, 4);
+res = (res >> 4) + round;
+return saddu16(env, vxrm, c, res);
+}
+
+static inline uint32_t
+vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
+ uint32_t c)
+{
+uint8_t round;
+uint32_t res = (uint32_t)a * b;
+
+round = get_round(vxrm, res, 8);
+res = (res >> 8) + round;
+return saddu32(env, vxrm, c, res);
+}
+
+static inline uint64_t
[PATCH v9 22/61] target/riscv: vector widening integer multiply-add instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c| 45 + 4 files changed, 83 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 08c2544b20..1a9495ceac 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -647,3 +647,25 @@ DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vwmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b49b60aea1..9735ac3565 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -393,6 +393,13 @@ vmadd_vv101001 . . . 010 . 1010111 @r_vm vmadd_vx101001 . . . 110 . 1010111 @r_vm vnmsub_vv 101011 . . . 010 . 1010111 @r_vm vnmsub_vx 101011 . . . 110 . 1010111 @r_vm +vwmaccu_vv 00 . . . 010 . 1010111 @r_vm +vwmaccu_vx 00 . . . 110 . 1010111 @r_vm +vwmacc_vv 01 . . . 010 . 1010111 @r_vm +vwmacc_vx 01 . . . 110 . 1010111 @r_vm +vwmaccsu_vv 10 . . . 010 . 1010111 @r_vm +vwmaccsu_vx 10 . . . 110 . 1010111 @r_vm +vwmaccus_vx 11 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index dc122eb2e5..3093191edc 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1609,3 +1609,12 @@ GEN_OPIVX_TRANS(vmacc_vx, opivx_check) GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) GEN_OPIVX_TRANS(vmadd_vx, opivx_check) GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) + +/* Vector Widening Integer Multiply-Add Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e787e00b01..c966ad8470 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1979,3 +1979,48 @@ GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq) + +/* Vector Widening Integer Multiply-Add Instructions */ +RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) +GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmaccu_vv_w, 4, 8
[PATCH v9 36/61] target/riscv: vector floating-point square-root instruction
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 43 +
target/riscv/vector_helper.c| 43 +
4 files changed, 93 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index edf963e787..db4de7135b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -917,3 +917,7 @@ DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 56bfd4a919..4ea71eaf39 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -45,6 +45,7 @@
shamt rs1 rd
aq rl rs2 rs1 rd
vm rd rs1 rs2
+ vm rd rs2
vm wd rd rs1 rs2
vm rd rs1 nf
vm rd rs1 rs2 nf
@@ -68,6 +69,7 @@
@r2_rm ... . . ... . ... %rs1 %rm %rd
@r2 ... . . ... . ... %rs1 %rd
@r2_nfvm ... ... vm:1 . . ... . ... %nf %rs1 %rd
+@r2_vm .. vm:1 . . ... . ... %rs2 %rd
@r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd
@r_vm.. vm:1 . . ... . ... %rs2 %rs1 %rd
@r_vm_1 .. . . . ... . ... vm=1 %rs2 %rs1 %rd
@@ -487,6 +489,7 @@ vfwmsac_vv 10 . . . 001 . 1010111 @r_vm
vfwmsac_vf 10 . . . 101 . 1010111 @r_vm
vfwnmsac_vv 11 . . . 001 . 1010111 @r_vm
vfwnmsac_vf 11 . . . 101 . 1010111 @r_vm
+vfsqrt_v100011 . . 0 001 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 945c9424ba..35db704bbc 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2089,3 +2089,46 @@ GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
+
+/* Vector Floating-Point Square-Root Instruction */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_check(DisasContext *s, arg_rmr *a)
+{
+ return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+(s->sew != 0));
+}
+
+#define GEN_OPFV_TRANS(NAME, CHECK)\
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+if (CHECK(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_3_ptr * const fns[3] = {\
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+gen_helper_##NAME##_d, \
+}; \
+TCGLabel *over = gen_new_label(); \
+gen_set_rm(s, 7); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0,\
+ s->vlen / 8, data, fns[s->sew - 1]);\
+gen_set_label(over); \
+return true; \
+} \
+return false; \
+}
+
+GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7abdc2b7d
[PATCH v9 41/61] target/riscv: vector floating-point merge instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 38 +
target/riscv/vector_helper.c| 24
4 files changed, 68 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 23b268df90..21054cc957 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -994,3 +994,7 @@ DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 23e80fe954..14cb4e2e66 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -513,6 +513,8 @@ vmfge_vf01 . . . 101 . 1010111 @r_vm
vmford_vv 011010 . . . 001 . 1010111 @r_vm
vmford_vf 011010 . . . 101 . 1010111 @r_vm
vfclass_v 100011 . . 1 001 . 1010111 @r2_vm
+vfmerge_vfm 010111 0 . . 101 . 1010111 @r_vm_0
+vfmv_v_f010111 1 0 . 101 . 1010111 @r2
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 80058669f0..51ee83255e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2184,3 +2184,41 @@ GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
+
+/* Vector Floating-Point Merge Instruction */
+GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
+
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+(s->sew != 0)) {
+
+if (s->vl_eq_vlmax) {
+tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+} else {
+TCGv_ptr dest;
+TCGv_i32 desc;
+uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+static gen_helper_vmv_vx * const fns[3] = {
+gen_helper_vmv_v_x_h,
+gen_helper_vmv_v_x_w,
+gen_helper_vmv_v_x_d,
+};
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+dest = tcg_temp_new_ptr();
+desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+tcg_temp_free_ptr(dest);
+tcg_temp_free_i32(desc);
+gen_set_label(over);
+}
+return true;
+}
+return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b0ccb32de0..5a0dd9304d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4194,3 +4194,27 @@ RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
+
+/* Vector Floating-Point Merge Instruction */
+#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+uint32_t mlen = vext_mlen(desc); \
+uint32_t vm = vext_vm(desc); \
+uint32_t vl = env->vl;\
+uint32_t esz = sizeof(ETYPE); \
+uint32_t vlmax = vext_maxsz(desc) / esz; \
+uint32_t i; \
+ \
+for (i = 0; i < vl; i++) {\
+ETYPE s2 = *((ETYPE *)vs2 + H(i));\
+*((ETYPE *)vd + H(i)) \
+ = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
+} \
+CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
+}
+
+GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
+GEN_VFMERGE_VF(vf
[PATCH v9 09/61] target/riscv: add vector amo operations
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 29 + target/riscv/insn32-64.decode | 11 ++ target/riscv/insn32.decode | 13 +++ target/riscv/insn_trans/trans_rvv.inc.c | 138 ++ target/riscv/internals.h| 1 + target/riscv/vector_helper.c| 147 6 files changed, 339 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 72ba4d9bdb..70a4b05f75 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -240,3 +240,32 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) +#ifdef TARGET_RISCV64 +DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) +#endif +DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 380bf791bc..86153d93fa 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -57,6 +57,17 @@ amomax_d 10100 . . . . 011 . 010 @atom_st amominu_d 11000 . . . . 011 . 010 @atom_st amomaxu_d 11100 . . . . 011 . 010 @atom_st +#*** Vector AMO operations (in addition to Zvamo) *** +vamoswapd_v 1 . . . . 111 . 010 @r_wdvm +vamoaddd_v 0 . . . . 111 . 010 @r_wdvm +vamoxord_v 00100 . . . . 111 . 010 @r_wdvm +vamoandd_v 01100 . . . . 111 . 010 @r_wdvm +vamoord_v 01000 . . . . 111 . 010 @r_wdvm +vamomind_v 1 . . . . 111 . 010 @r_wdvm +vamomaxd_v 10100 . . . . 111 . 010 @r_wdvm +vamominud_v 11000 . . . . 111 . 010 @r_wdvm +vamomaxud_v 11100 . . . . 111 . 010 @r_wdvm + # *** RV64F Standard Extension (in addition to RV32F) *** fcvt_l_s 110 00010 . ... . 1010011 @r2_rm fcvt_lu_s 110 00011 . ... . 1010011 @r2_rm diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b76c09c8c0..1330703720 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -44,6 +44,7 @@ imm rd shamt rs1 rd aq rl rs2 rs1 rd + vm wd rd rs1 rs2 vm rd rs1 nf vm rd rs1 rs2 nf @@ -67,6 +68,7 @@ @r2 ... . . ... . ... %rs1 %rd @r2_nfvm ... ... vm:1 . . ... . ... %nf %rs1 %rd @r_nfvm ... ... vm:1 . . ... . ... %nf %rs2 %rs1 %rd +@r_wdvm . wd:1 vm:1 . . ... . ... %rs2 %rs1 %rd @r2_zimm . zimm:11 . ... . ... %rs1 %rd @hfence_gvma ... . . ... . ... %rs2 %rs1 @@ -261,6 +263,17 @@ vsxh_v ... -11 . . . 101 . 0100111 @r_nfvm vsxw_v ... -11 . . . 110 . 0100111 @r_nfvm vsxe_v ... -11 . . . 111 . 0100111 @r_nfvm
[PATCH v9 14/61] target/riscv: vector single-width bit shift instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 52
target/riscv/vector_helper.c| 79 +
4 files changed, 165 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ea4a4a6054..f96079bee5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -401,3 +401,28 @@ DEF_HELPER_6(vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsrl_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsra_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsll_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsrl_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ad6724632..f6d0f5aec5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -320,6 +320,15 @@ vor_vi 001010 . . . 011 . 1010111
@r_vm
vxor_vv 001011 . . . 000 . 1010111 @r_vm
vxor_vx 001011 . . . 100 . 1010111 @r_vm
vxor_vi 001011 . . . 011 . 1010111 @r_vm
+vsll_vv 100101 . . . 000 . 1010111 @r_vm
+vsll_vx 100101 . . . 100 . 1010111 @r_vm
+vsll_vi 100101 . . . 011 . 1010111 @r_vm
+vsrl_vv 101000 . . . 000 . 1010111 @r_vm
+vsrl_vx 101000 . . . 100 . 1010111 @r_vm
+vsrl_vi 101000 . . . 011 . 1010111 @r_vm
+vsra_vv 101001 . . . 000 . 1010111 @r_vm
+vsra_vx 101001 . . . 100 . 1010111 @r_vm
+vsra_vi 101001 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 35c92986a6..8ea7c437ee 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1373,3 +1373,55 @@ GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
+
+/* Vector Single-Width Bit Shift Instructions */
+GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
+GEN_OPIVV_GVEC_TRANS(vsrl_vv, shrv)
+GEN_OPIVV_GVEC_TRANS(vsra_vv, sarv)
+
+typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
+ uint32_t, uint32_t);
+
+static inline bool
+do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
+gen_helper_opivx *fn)
+{
+if (!opivx_check(s, a)) {
+return false;
+}
+
+if (a->vm && s->vl_eq_vlmax) {
+TCGv_i32 src1 = tcg_temp_new_i32();
+TCGv tmp = tcg_temp_new();
+
+gen_get_gpr(tmp, a->rs1);
+tcg_gen_trunc_tl_i32(src1, tmp);
+tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
+gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+src1, MAXSZ(s), MAXSZ(s));
+
+tcg_temp_free_i32(src1);
+tcg_temp_free(tmp);
+return true;
+}
+return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
+}
+
+#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
+static bo
[PATCH v9 19/61] target/riscv: vector integer divide instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74 + 4 files changed, 125 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 08c1c02e13..5fd718771c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -562,3 +562,36 @@ DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vdivu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdivu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdivu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdivu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdiv_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vremu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vremu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vremu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vremu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrem_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrem_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrem_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrem_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vdivu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdivu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdivu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdivu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdiv_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdiv_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdiv_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vdiv_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vremu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vremu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vremu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vremu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index abfed469bc..7fb8f8fad8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -371,6 +371,14 @@ vmulhu_vv 100100 . . . 010 . 1010111 @r_vm vmulhu_vx 100100 . . . 110 . 1010111 @r_vm vmulhsu_vv 100110 . . . 010 . 1010111 @r_vm vmulhsu_vx 100110 . . . 110 . 1010111 @r_vm +vdivu_vv10 . . . 010 . 1010111 @r_vm +vdivu_vx10 . . . 110 . 1010111 @r_vm +vdiv_vv 11 . . . 010 . 1010111 @r_vm +vdiv_vx 11 . . . 110 . 1010111 @r_vm +vremu_vv100010 . . . 010 . 1010111 @r_vm +vremu_vx100010 . . . 110 . 1010111 @r_vm +vrem_vv 100011 . . . 010 . 1010111 @r_vm +vrem_vx 100011 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index de5b8b7df6..4b4312fa99 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1581,3 +1581,13 @@ GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) GEN_OPIVX_TRANS(vmulh_vx, opivx_check) GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) + +/* Vector Integer Divide Instructions */ +GEN_OPIVV_TRANS(vdivu_vv, opivv_check) +GEN_OPIVV_TRANS(vdiv_vv, opivv_check) +GEN_OPIVV_TRANS(vremu_vv, opivv_check) +GEN_OPIVV_TRANS(vrem_vv, opivv_check) +GEN_OPIVX_TRANS(vdivu_vx, opivx_check) +GEN_OPIVX_TRANS(vdiv_vx, opivx_check) +GEN_OPIVX_TRANS(vremu_vx, opivx_check) +GEN_OPIVX_TRANS(vrem_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3319370ae2..aee107a82e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1766,3 +1766,77 @@ GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb) GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh) GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl) GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq) + +/* Vector Integer Divide Instructions */ +#define DO_DIVU(N
[PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 +
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 141
4 files changed, 168 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f36f840714..7f7fdcb451 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -784,3 +784,16 @@ DEF_HELPER_6(vssra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2ecac3d96d..8b898f9bad 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -437,6 +437,12 @@ vssrl_vi101010 . . . 011 . 1010111
@r_vm
vssra_vv101011 . . . 000 . 1010111 @r_vm
vssra_vx101011 . . . 100 . 1010111 @r_vm
vssra_vi101011 . . . 011 . 1010111 @r_vm
+vnclipu_vv 101110 . . . 000 . 1010111 @r_vm
+vnclipu_vx 101110 . . . 100 . 1010111 @r_vm
+vnclipu_vi 101110 . . . 011 . 1010111 @r_vm
+vnclip_vv 10 . . . 000 . 1010111 @r_vm
+vnclip_vx 10 . . . 100 . 1010111 @r_vm
+vnclip_vi 10 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 0d9e65a194..96fcf02a8c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1775,3 +1775,11 @@ GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+
+/* Vector Narrowing Fixed-Point Clip Instructions */
+GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
+GEN_OPIVV_NARROW_TRANS(vnclip_vv)
+GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
+GEN_OPIVX_NARROW_TRANS(vnclip_vx)
+GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
+GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c33e845a90..1c375f437a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -875,6 +875,12 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w,
clearl)
#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
+#define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
+#define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
+#define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
+#define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t
+#define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
+#define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
/* operation of two vector elements */
typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
@@ -3009,6 +3015,7 @@ vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t
b)
res = (a >> shift) + round;
return res;
}
+
RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
@@ -3026,3 +3033,137 @@ GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq)
+
+/* Vector Narrowing Fixed-Point Clip Instructions */
+static inline int8_t
+vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b)
+{
+uint8_t round, shift = b & 0xf;
+int16_t res;
+
+round = get_round(vxrm, a, shift);
+res = (a >> shift) + round;
+if (res > INT8_MAX) {
+
[PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 107
4 files changed, 122 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 32d549ce36..e6cae1b59c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -736,3 +736,12 @@ DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e617d7bd60..633f782fbf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -422,6 +422,8 @@ vaadd_vx100100 . . . 100 . 1010111 @r_vm
vaadd_vi100100 . . . 011 . 1010111 @r_vm
vasub_vv100110 . . . 000 . 1010111 @r_vm
vasub_vx100110 . . . 100 . 1010111 @r_vm
+vsmul_vv100111 . . . 000 . 1010111 @r_vm
+vsmul_vx100111 . . . 100 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index ed1ee0f1b5..23714793df 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1754,3 +1754,7 @@ GEN_OPIVV_TRANS(vasub_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
+GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ada95ab1e7..dd3fc39016 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2597,3 +2597,110 @@ GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
+static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
+{
+uint8_t round;
+int16_t res;
+
+res = (int16_t)a * (int16_t)b;
+round = get_round(vxrm, res, 7);
+res = (res >> 7) + round;
+
+if (res > INT8_MAX) {
+env->vxsat = 0x1;
+return INT8_MAX;
+} else if (res < INT8_MIN) {
+env->vxsat = 0x1;
+return INT8_MIN;
+} else {
+return res;
+}
+}
+
+static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b)
+{
+uint8_t round;
+int32_t res;
+
+res = (int32_t)a * (int32_t)b;
+round = get_round(vxrm, res, 15);
+res = (res >> 15) + round;
+
+if (res > INT16_MAX) {
+env->vxsat = 0x1;
+return INT16_MAX;
+} else if (res < INT16_MIN) {
+env->vxsat = 0x1;
+return INT16_MIN;
+} else {
+return res;
+}
+}
+
+static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
+{
+uint8_t round;
+int64_t res;
+
+res = (int64_t)a * (int64_t)b;
+round = get_round(vxrm, res, 31);
+res = (res >> 31) + round;
+
+if (res > INT32_MAX) {
+env->vxsat = 0x1;
+return INT32_MAX;
+} else if (res < INT32_MIN) {
+env->vxsat = 0x1;
+return INT32_MIN;
+} else {
+return res;
+}
+}
+
+static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
+{
+uint8_t round;
+uint64_t hi_64, lo_64;
+int64_t res;
+
+if (a == INT64_MIN && b == INT64_MIN) {
+env->vxsat = 1;
+return INT64_MAX;
+}
+
+muls64(_64, _64, a, b);
+round = get_round(vxrm, lo_64, 63);
+/*
+ * Cannot overflow, as there are always
+ * 2 sign bits after multiply.
+ */
+res = (hi_64 << 1) | (lo_64 >> 63);
+if (round) {
+if (res == INT64_MAX) {
+env->vxsat = 1;
+} else {
+res += 1;
+}
+
[PATCH v9 37/61] target/riscv: vector floating-point min/max instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c| 27 + 4 files changed, 50 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index db4de7135b..12d959ba0d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -921,3 +921,16 @@ DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4ea71eaf39..5ec5595e2c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -490,6 +490,10 @@ vfwmsac_vf 10 . . . 101 . 1010111 @r_vm vfwnmsac_vv 11 . . . 001 . 1010111 @r_vm vfwnmsac_vf 11 . . . 101 . 1010111 @r_vm vfsqrt_v100011 . . 0 001 . 1010111 @r2_vm +vfmin_vv000100 . . . 001 . 1010111 @r_vm +vfmin_vf000100 . . . 101 . 1010111 @r_vm +vfmax_vv000110 . . . 001 . 1010111 @r_vm +vfmax_vf000110 . . . 101 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 35db704bbc..0c1e45123d 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2132,3 +2132,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check) + +/* Vector Floating-Point MIN/MAX Instructions */ +GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) +GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) +GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) +GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7f527c95e0..82e570da4e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3817,3 +3817,30 @@ RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) + +/* Vector Floating-Point MIN/MAX Instructions */ +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) +GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) +GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) + +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) +GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) +GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) +GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) +GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) +GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq) -- 2.23.0
[PATCH v9 40/61] target/riscv: vector floating-point classify instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 33 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 +
target/riscv/internals.h| 5 ++
target/riscv/vector_helper.c| 91 +
6 files changed, 107 insertions(+), 30 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 0b79562a69..4379756dc4 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -22,6 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
+#include "internals.h"
target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
@@ -230,21 +231,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
target_ulong helper_fclass_s(uint64_t frs1)
{
-float32 f = frs1;
-bool sign = float32_is_neg(f);
-
-if (float32_is_infinity(f)) {
-return sign ? 1 << 0 : 1 << 7;
-} else if (float32_is_zero(f)) {
-return sign ? 1 << 3 : 1 << 4;
-} else if (float32_is_zero_or_denormal(f)) {
-return sign ? 1 << 2 : 1 << 5;
-} else if (float32_is_any_nan(f)) {
-float_status s = { }; /* for snan_bit_is_one */
-return float32_is_quiet_nan(f, ) ? 1 << 9 : 1 << 8;
-} else {
-return sign ? 1 << 1 : 1 << 6;
-}
+return fclass_s(frs1);
}
uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
@@ -353,19 +340,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
target_ulong helper_fclass_d(uint64_t frs1)
{
-float64 f = frs1;
-bool sign = float64_is_neg(f);
-
-if (float64_is_infinity(f)) {
-return sign ? 1 << 0 : 1 << 7;
-} else if (float64_is_zero(f)) {
-return sign ? 1 << 3 : 1 << 4;
-} else if (float64_is_zero_or_denormal(f)) {
-return sign ? 1 << 2 : 1 << 5;
-} else if (float64_is_any_nan(f)) {
-float_status s = { }; /* for snan_bit_is_one */
-return float64_is_quiet_nan(f, ) ? 1 << 9 : 1 << 8;
-} else {
-return sign ? 1 << 1 : 1 << 6;
-}
+return fclass_d(frs1);
}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index bedd4d0114..23b268df90 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -990,3 +990,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env,
i32)
DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b0f1c54d53..23e80fe954 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -512,6 +512,7 @@ vmfgt_vf011101 . . . 101 . 1010111 @r_vm
vmfge_vf01 . . . 101 . 1010111 @r_vm
vmford_vv 011010 . . . 001 . 1010111 @r_vm
vmford_vf 011010 . . . 101 . 1010111 @r_vm
+vfclass_v 100011 . . 1 001 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 11473b8f72..80058669f0 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2181,3 +2181,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
+
+/* Vector Floating-Point Classify Instruction */
+GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index e59e8b30ad..f3cea478f7 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,4 +27,9 @@ FIELD(VDATA, VM, 8, 1)
FIELD(VDATA, LMUL, 9, 2)
FIELD(VDATA, NF, 11, 4)
FIELD(VDATA, WD, 11, 1)
+
+/* float point classify helpers */
+target_ulong fclass_h(uint64_t frs1);
+target_ulong fclass_s(uint64_t frs1);
+target_ulong fclass_d(uint64_t frs1);
#endif
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f4264c51b5..b0ccb32de0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4103,3 +4103,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8,
!float64_unordered_quiet)
GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
GEN_VEXT_CMP_VF(vmford_vf_w
[PATCH v9 43/61] target/riscv: widening floating-point/integer type-convert instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 48 +
target/riscv/vector_helper.c| 42 ++
4 files changed, 106 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 05f8fb5ffc..e59dcc5a7c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1011,3 +1011,14 @@ DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 53562c6663..e0efc63ec2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -519,6 +519,11 @@ vfcvt_xu_f_v100010 . . 0 001 . 1010111
@r2_vm
vfcvt_x_f_v 100010 . . 1 001 . 1010111 @r2_vm
vfcvt_f_xu_v100010 . . 00010 001 . 1010111 @r2_vm
vfcvt_f_x_v 100010 . . 00011 001 . 1010111 @r2_vm
+vfwcvt_xu_f_v 100010 . . 01000 001 . 1010111 @r2_vm
+vfwcvt_x_f_v100010 . . 01001 001 . 1010111 @r2_vm
+vfwcvt_f_xu_v 100010 . . 01010 001 . 1010111 @r2_vm
+vfwcvt_f_x_v100010 . . 01011 001 . 1010111 @r2_vm
+vfwcvt_f_f_v100010 . . 01100 001 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index a2a851de87..dd4182c327 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2228,3 +2228,51 @@ GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
+
+/* Widening Floating-Point/Integer Type-Convert Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+vext_check_reg(s, a->rd, true) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
+ 1 << s->lmul) &&
+(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+#define GEN_OPFV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+if (opfv_widen_check(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_3_ptr * const fns[2] = {\
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+}; \
+TCGLabel *over = gen_new_label(); \
+gen_set_rm(s, 7); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0,\
+ s->vlen / 8, data, fns[s->sew - 1]);\
+gen_set_label(over); \
+return true;
[PATCH v9 47/61] target/riscv: vector single-width floating-point reduction instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 5
target/riscv/vector_helper.c| 39 +
4 files changed, 58 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ce31577ea9..17fd02c323 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1073,3 +1073,13 @@ DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b69d804fda..0592075167 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -539,6 +539,10 @@ vredmaxu_vs 000110 . . . 010 . 1010111
@r_vm
vredmax_vs 000111 . . . 010 . 1010111 @r_vm
vwredsumu_vs11 . . . 000 . 1010111 @r_vm
vwredsum_vs 110001 . . . 000 . 1010111 @r_vm
+# Vector ordered and unordered reduction sum
+vfredsum_vs -1 . . . 001 . 1010111 @r_vm
+vfredmin_vs 000101 . . . 001 . 1010111 @r_vm
+vfredmax_vs 000111 . . . 001 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 06842c424e..7e9d0ded37 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2346,3 +2346,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */
GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
+
+/* Vector Single-Width Floating-Point Reduction Instructions */
+GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
+GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fdeedad64f..ba961230f6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4417,3 +4417,42 @@ GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4,
DO_ADD, clearq)
GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
+
+/* Vector Single-Width Floating-Point Reduction Instructions */
+#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+uint32_t mlen = vext_mlen(desc); \
+uint32_t vm = vext_vm(desc); \
+uint32_t vl = env->vl; \
+uint32_t i;\
+uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
+TD s1 = *((TD *)vs1 + HD(0)); \
+ \
+for (i = 0; i < vl; i++) { \
+TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+continue; \
+} \
+s1 = OP(s1, (TD)s2, >fp_status); \
+} \
+*((TD *)vd + HD(0)) = s1; \
+CLEAR_FN(vd, 1, sizeof(TD), tot); \
+}
+
+/* Unordered sum */
+GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh)
+GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl)
+GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq)
+
+/* Maximum val
[PATCH v9 06/61] target/riscv: add vector stride load and store instructions
Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 105 ++ target/riscv/insn32.decode | 32 ++ target/riscv/insn_trans/trans_rvv.inc.c | 355 target/riscv/internals.h| 5 + target/riscv/translate.c| 7 + target/riscv/vector_helper.c| 410 6 files changed, 914 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3c28c7e407..87dfa90609 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -78,3 +78,108 @@ DEF_HELPER_1(tlb_flush, void, env) #endif /* Vector functions */ DEF_HELPER_3(vsetvl, tl, env, tl, tl) +DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5
[PATCH v9 08/61] target/riscv: add fault-only-first unit stride load
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 73
target/riscv/vector_helper.c| 110
4 files changed, 212 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f9b3da60ca..72ba4d9bdb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -218,3 +218,25 @@ DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bc36df33b5..b76c09c8c0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -224,6 +224,13 @@ vle_v ... 000 . 0 . 111 . 111 @r2_nfvm
vlbu_v ... 000 . 0 . 000 . 111 @r2_nfvm
vlhu_v ... 000 . 0 . 101 . 111 @r2_nfvm
vlwu_v ... 000 . 0 . 110 . 111 @r2_nfvm
+vlbff_v... 100 . 1 . 000 . 111 @r2_nfvm
+vlhff_v... 100 . 1 . 101 . 111 @r2_nfvm
+vlwff_v... 100 . 1 . 110 . 111 @r2_nfvm
+vleff_v... 000 . 1 . 111 . 111 @r2_nfvm
+vlbuff_v ... 000 . 1 . 000 . 111 @r2_nfvm
+vlhuff_v ... 000 . 1 . 101 . 111 @r2_nfvm
+vlwuff_v ... 000 . 1 . 110 . 111 @r2_nfvm
vsb_v ... 000 . 0 . 000 . 0100111 @r2_nfvm
vsh_v ... 000 . 0 . 101 . 0100111 @r2_nfvm
vsw_v ... 000 . 0 . 110 . 0100111 @r2_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index c3a79c5232..299b479ec1 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -561,3 +561,76 @@ GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op,
st_index_check)
GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+
+/*
+ *** unit stride fault-only-first load
+ */
+static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
+ gen_helper_ldst_us *fn, DisasContext *s)
+{
+TCGv_ptr dest, mask;
+TCGv base;
+TCGv_i32 desc;
+
+TCGLabel *over = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+dest = tcg_temp_new_ptr();
+mask = tcg_temp_new_ptr();
+base = tcg_temp_new();
+desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+gen_get_gpr(base, rs1);
+tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
+
+fn(dest, mask, base, cpu_env, desc);
+
+tcg_temp_free_ptr(dest);
+tcg_temp_free_ptr(mask);
+tcg_temp_free(base);
+tcg_temp_free_i32(desc);
+gen_set_label(over);
+return true;
+}
+
+static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+uint32_t data = 0;
+gen_helper_ldst_us *fn;
+static gen_helper_ldst_us * const fns[7][4] = {
+{ gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
+ gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
+{ NULL, gen_helper_vlhff_v_h,
+ gen_helper_vlhff_
[PATCH v9 15/61] target/riscv: vector narrowing integer right shift instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 90 +
target/riscv/vector_helper.c| 14
4 files changed, 123 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f96079bee5..0222aa863d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -426,3 +426,16 @@ DEF_HELPER_6(vsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f6d0f5aec5..89fd2aa4e2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -329,6 +329,12 @@ vsrl_vi 101000 . . . 011 . 1010111
@r_vm
vsra_vv 101001 . . . 000 . 1010111 @r_vm
vsra_vx 101001 . . . 100 . 1010111 @r_vm
vsra_vi 101001 . . . 011 . 1010111 @r_vm
+vnsrl_vv101100 . . . 000 . 1010111 @r_vm
+vnsrl_vx101100 . . . 100 . 1010111 @r_vm
+vnsrl_vi101100 . . . 011 . 1010111 @r_vm
+vnsra_vv101101 . . . 000 . 1010111 @r_vm
+vnsra_vx101101 . . . 100 . 1010111 @r_vm
+vnsra_vi101101 . . . 011 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 8ea7c437ee..87f9ee7f6c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1425,3 +1425,93 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+
+/* Vector Narrowing Integer Right Shift Instructions */
+static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, true) &&
+vext_check_reg(s, a->rs1, false) &&
+vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+2 << s->lmul) &&
+(s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+/* OPIVV with NARROW */
+#define GEN_OPIVV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+if (opivv_narrow_check(s, a)) {\
+uint32_t data = 0; \
+static gen_helper_gvec_4_ptr * const fns[3] = {\
+gen_helper_##NAME##_b, \
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+}; \
+TCGLabel *over = gen_new_label(); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1),\
+ vreg_ofs(s, a->rs2), cpu_env, 0,\
+ s->v
[PATCH v9 13/61] target/riscv: vector bitwise logical instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c| 51 + 4 files changed, 96 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 186d72a2aa..ea4a4a6054 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -376,3 +376,28 @@ DEF_HELPER_6(vmsbc_vxm_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vand_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vxor_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vand_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vand_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vor_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 022c8ea18b..3ad6724632 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -311,6 +311,15 @@ vsbc_vvm010010 1 . . 000 . 1010111 @r_vm_1 vsbc_vxm010010 1 . . 100 . 1010111 @r_vm_1 vmsbc_vvm 010011 1 . . 000 . 1010111 @r_vm_1 vmsbc_vxm 010011 1 . . 100 . 1010111 @r_vm_1 +vand_vv 001001 . . . 000 . 1010111 @r_vm +vand_vx 001001 . . . 100 . 1010111 @r_vm +vand_vi 001001 . . . 011 . 1010111 @r_vm +vor_vv 001010 . . . 000 . 1010111 @r_vm +vor_vx 001010 . . . 100 . 1010111 @r_vm +vor_vi 001010 . . . 011 . 1010111 @r_vm +vxor_vv 001011 . . . 000 . 1010111 @r_vm +vxor_vx 001011 . . . 100 . 1010111 @r_vm +vxor_vi 001011 . . . 011 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 6fe2f071e6..35c92986a6 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1362,3 +1362,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) + +/* Vector Bitwise Logical Instructions */ +GEN_OPIVV_GVEC_TRANS(vand_vv, and) +GEN_OPIVV_GVEC_TRANS(vor_vv, or) +GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) +GEN_OPIVX_GVEC_TRANS(vand_vx, ands) +GEN_OPIVX_GVEC_TRANS(vor_vx, ors) +GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) +GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ad746175bd..6c53dc5796 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1265,3 +1265,54 @@ GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC) GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC) + +/* Vector Bitwise Logical Instructions */ +RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND) +RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND) +RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND) +RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND) +RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR) +RVVCALL(OPIVV2, vor_vv_h
[PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 + target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 163 4 files changed, 214 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 32f4c76b34..08c1c02e13 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -529,3 +529,36 @@ DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulh_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulh_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aafbdc6be7..abfed469bc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -363,6 +363,14 @@ vmaxu_vv000110 . . . 000 . 1010111 @r_vm vmaxu_vx000110 . . . 100 . 1010111 @r_vm vmax_vv 000111 . . . 000 . 1010111 @r_vm vmax_vx 000111 . . . 100 . 1010111 @r_vm +vmul_vv 100101 . . . 010 . 1010111 @r_vm +vmul_vx 100101 . . . 110 . 1010111 @r_vm +vmulh_vv100111 . . . 010 . 1010111 @r_vm +vmulh_vx100111 . . . 110 . 1010111 @r_vm +vmulhu_vv 100100 . . . 010 . 1010111 @r_vm +vmulhu_vx 100100 . . . 110 . 1010111 @r_vm +vmulhsu_vv 100110 . . . 010 . 1010111 @r_vm +vmulhsu_vx 100110 . . . 110 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index cbcb40e682..de5b8b7df6 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1571,3 +1571,13 @@ GEN_OPIVX_TRANS(vminu_vx, opivx_check) GEN_OPIVX_TRANS(vmin_vx, opivx_check) GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) GEN_OPIVX_TRANS(vmax_vx, opivx_check) + +/* Vector Single-Width Integer Multiply Instructions */ +GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) +GEN_OPIVV_TRANS(vmulh_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) +GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) +GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) +GEN_OPIVX_TRANS(vmulh_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) +GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cb41daa3ac..3319370ae2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -859,6 +859,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
[PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 118
target/riscv/vector_helper.c| 111 ++
4 files changed, 250 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7f7fdcb451..3031a941c2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -797,3 +797,19 @@ DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env,
i32)
DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8b898f9bad..c8e3f10162 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -443,6 +443,11 @@ vnclipu_vi 101110 . . . 011 . 1010111
@r_vm
vnclip_vv 10 . . . 000 . 1010111 @r_vm
vnclip_vx 10 . . . 100 . 1010111 @r_vm
vnclip_vi 10 . . . 011 . 1010111 @r_vm
+vfadd_vv00 . . . 001 . 1010111 @r_vm
+vfadd_vf00 . . . 101 . 1010111 @r_vm
+vfsub_vv10 . . . 001 . 1010111 @r_vm
+vfsub_vf10 . . . 101 . 1010111 @r_vm
+vfrsub_vf 100111 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 96fcf02a8c..7461e86de8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1783,3 +1783,121 @@ GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
GEN_OPIVX_NARROW_TRANS(vnclip_vx)
GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+
+/*
+ *** Vector Float Point Arithmetic Instructions
+ */
+/* Vector Single-Width Floating-Point Add/Subtract Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised.
+ */
+static bool opfvv_check(DisasContext *s, arg_rmrr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, false) &&
+vext_check_reg(s, a->rs1, false) &&
+(s->sew != 0));
+}
+
+/* OPFVV without GVEC IR */
+#define GEN_OPFVV_TRANS(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+if (CHECK(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_4_ptr * const fns[3] = {\
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+gen_helper_##NAME##_d, \
+}; \
+TCGLabel *over = gen_new_label(); \
+gen_set_rm(s, 7); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd)
[PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385 4 files changed, 444 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 279b2e049f..9416ebb090 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -686,3 +686,36 @@ DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32) DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32) + +DEF_HELPER_6(vsaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vssub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index adb76956c9..c9a4050adc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -407,6 +407,16 @@ vmv_v_i 010111 1 0 . 011 . 1010111 @r2 vmerge_vvm 010111 0 . . 000 . 1010111 @r_vm_0 vmerge_vxm 010111 0 . . 100 . 1010111 @r_vm_0 vmerge_vim 010111 0 . . 011 . 1010111 @r_vm_0 +vsaddu_vv 10 . . . 000 . 1010111 @r_vm +vsaddu_vx 10 . . . 100 . 1010111 @r_vm +vsaddu_vi 10 . . . 011 . 1010111 @r_vm +vsadd_vv11 . . . 000 . 1010111 @r_vm +vsadd_vx11 . . . 100 . 1010111 @r_vm +vsadd_vi11 . . . 011 . 1010111 @r_vm +vssubu_vv 100010 . . . 000 . 1010111 @r_vm +vssubu_vx 100010 . . . 100 . 1010111 @r_vm +vssub_vv100011 . . . 000 . 1010111 @r_vm +vssub_vx100011 . . . 100 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index d726995f84..4d5eae8dde 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1731,3 +1731,19 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) + +/* + *** Vector Fixed-Point Arithmetic Instructions + */ + +/* Vector Single-Width Saturating Add and Subtract */ +GEN_OPIVV_TRANS(vsaddu_vv, opivv_check) +GEN_OPIVV_TRANS(vsadd_vv, opivv_check) +GEN_OPIVV_TRANS(vssubu_vv, opivv_check) +GEN_OPIVV_TRANS(vssub_vv, opivv_check) +GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) +GEN_OPIVX_TRANS(vsadd_vx, opivx_check) +GEN_OPIVX_TRANS(vssubu_vx, opivx_check) +GEN_OPIVX_TRANS(vssub_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index
[PATCH v9 33/61] target/riscv: vector widening floating-point multiply
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index fa1558179a..5b3340a4af 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -846,3 +846,8 @@ DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 16fd938261..1d963f0b8a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -461,6 +461,8 @@ vfmul_vf100100 . . . 101 . 1010111 @r_vm
vfdiv_vv10 . . . 001 . 1010111 @r_vm
vfdiv_vf10 . . . 101 . 1010111 @r_vm
vfrdiv_vf 11 . . . 101 . 1010111 @r_vm
+vfwmul_vv 111000 . . . 001 . 1010111 @r_vm
+vfwmul_vf 111000 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index be60115801..7ff3af0c61 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2057,3 +2057,7 @@ GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Multiply */
+GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ea807ef731..0dd94348e8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3410,3 +3410,25 @@ RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8,
float64_rdiv)
GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq)
+
+/* Vector Widening Floating-Point Multiply */
+static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
+{
+return float32_mul(float16_to_float32(a, true, s),
+float16_to_float32(b, true, s), s);
+}
+
+static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
+{
+return float64_mul(float32_to_float64(a, s),
+float32_to_float64(b, s), s);
+
+}
+RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
+RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
+GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl)
+GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq)
+RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
+RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
+GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
+GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)
--
2.23.0
[PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 85 +
4 files changed, 118 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 12d959ba0d..d6e7ce57be 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -934,3 +934,22 @@ DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfsgnj_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5ec5595e2c..ce2f497ed2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -494,6 +494,12 @@ vfmin_vv000100 . . . 001 . 1010111
@r_vm
vfmin_vf000100 . . . 101 . 1010111 @r_vm
vfmax_vv000110 . . . 001 . 1010111 @r_vm
vfmax_vf000110 . . . 101 . 1010111 @r_vm
+vfsgnj_vv 001000 . . . 001 . 1010111 @r_vm
+vfsgnj_vf 001000 . . . 101 . 1010111 @r_vm
+vfsgnjn_vv 001001 . . . 001 . 1010111 @r_vm
+vfsgnjn_vf 001001 . . . 101 . 1010111 @r_vm
+vfsgnjx_vv 001010 . . . 001 . 1010111 @r_vm
+vfsgnjx_vf 001010 . . . 101 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 0c1e45123d..6170fce05d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2138,3 +2138,11 @@ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 82e570da4e..7a1c5311bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3844,3 +3844,88 @@ RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8,
float64_maxnum)
GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
+{
+return deposit64(b, 0, 15, a);
+}
+
+static uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s)
+{
+return deposit64(b, 0, 31, a);
+}
+
+static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
+{
+return deposit64(b, 0, 63, a);
+}
+
+RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
+RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
+RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
+GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq)
+RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
+RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
+RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
+GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh)
+GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl)
+GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq)
+
+static uint16_t fsgnjn16(uint16_t
[PATCH v9 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 48 +
target/riscv/vector_helper.c| 39
4 files changed, 103 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e59dcc5a7c..82c5d1129e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1022,3 +1022,14 @@ DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e0efc63ec2..57ac4de1c2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -524,6 +524,11 @@ vfwcvt_x_f_v100010 . . 01001 001 . 1010111
@r2_vm
vfwcvt_f_xu_v 100010 . . 01010 001 . 1010111 @r2_vm
vfwcvt_f_x_v100010 . . 01011 001 . 1010111 @r2_vm
vfwcvt_f_f_v100010 . . 01100 001 . 1010111 @r2_vm
+vfncvt_xu_f_v 100010 . . 1 001 . 1010111 @r2_vm
+vfncvt_x_f_v100010 . . 10001 001 . 1010111 @r2_vm
+vfncvt_f_xu_v 100010 . . 10010 001 . 1010111 @r2_vm
+vfncvt_f_x_v100010 . . 10011 001 . 1010111 @r2_vm
+vfncvt_f_f_v100010 . . 10100 001 . 1010111 @r2_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index dd4182c327..4e4631ac6a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2276,3 +2276,51 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
+
+/* Narrowing Floating-Point/Integer Type-Convert Instructions */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+return (vext_check_isa_ill(s) &&
+vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs2, true) &&
+vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+(s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+}
+
+#define GEN_OPFV_NARROW_TRANS(NAME)\
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+if (opfv_narrow_check(s, a)) { \
+uint32_t data = 0; \
+static gen_helper_gvec_3_ptr * const fns[2] = {\
+gen_helper_##NAME##_h, \
+gen_helper_##NAME##_w, \
+}; \
+TCGLabel *over = gen_new_label(); \
+gen_set_rm(s, 7); \
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+data = FIELD_DP32(data, VDATA, VM, a->vm); \
+data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0,\
+ s->vlen / 8, data, fns[s->sew - 1]);\
+gen_set_label(over); \
+return true; \
+}
[PATCH v9 46/61] target/riscv: vector wideing integer reduction instructions
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 93a7a303ee..ce31577ea9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1066,3 +1066,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 773b32f0b4..b69d804fda 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -537,6 +537,8 @@ vredminu_vs 000100 . . . 010 . 1010111 @r_vm vredmin_vs 000101 . . . 010 . 1010111 @r_vm vredmaxu_vs 000110 . . . 010 . 1010111 @r_vm vredmax_vs 000111 . . . 010 . 1010111 @r_vm +vwredsumu_vs11 . . . 000 . 1010111 @r_vm +vwredsum_vs 110001 . . . 000 . 1010111 @r_vm vsetvli 0 ... . 111 . 1010111 @r2_zimm vsetvl 100 . . 111 . 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index b3920eed23..06842c424e 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2342,3 +2342,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check) GEN_OPIVV_TRANS(vredand_vs, reduction_check) GEN_OPIVV_TRANS(vredor_vs, reduction_check) GEN_OPIVV_TRANS(vredxor_vs, reduction_check) + +/* Vector Widening Integer Reduction Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5c357b688f..fdeedad64f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4406,3 +4406,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) + +/* Vector Widening Integer Reduction Instructions */ +/* signed sum reduction into double-width accumulator */ +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) + +/* Unsigned sum reduction into double-width accumulator */ +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) -- 2.23.0
[PATCH v9 48/61] target/riscv: vector widening floating-point reduction instructions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 46 +
4 files changed, 54 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 17fd02c323..6b932b444d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1083,3 +1083,6 @@ DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0592075167..526a964d28 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -543,6 +543,8 @@ vwredsum_vs 110001 . . . 000 . 1010111 @r_vm
vfredsum_vs -1 . . . 001 . 1010111 @r_vm
vfredmin_vs 000101 . . . 001 . 1010111 @r_vm
vfredmax_vs 000111 . . . 001 . 1010111 @r_vm
+# Vector widening ordered and unordered float reduction sum
+vfwredsum_vs1100-1 . . . 001 . 1010111 @r_vm
vsetvli 0 ... . 111 . 1010111 @r2_zimm
vsetvl 100 . . 111 . 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 7e9d0ded37..1f1559b0bd 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2351,3 +2351,6 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
+
+/* Vector Widening Floating-Point Reduction Instructions */
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ba961230f6..e30f8f83d3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4456,3 +4456,49 @@ GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8,
float64_maxnum, clearq)
GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum,
clearh)
GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum,
clearl)
GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum,
clearq)
+
+/* Vector Widening Floating-Point Reduction Instructions */
+/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
+void *vs2, CPURISCVState *env, uint32_t desc)
+{
+uint32_t mlen = vext_mlen(desc);
+uint32_t vm = vext_vm(desc);
+uint32_t vl = env->vl;
+uint32_t i;
+uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+
+for (i = 0; i < vl; i++) {
+uint16_t s2 = *((uint16_t *)vs2 + H2(i));
+if (!vm && !vext_elem_mask(v0, mlen, i)) {
+continue;
+}
+s1 = float32_add(s1, float16_to_float32(s2, true, >fp_status),
+ >fp_status);
+}
+*((uint32_t *)vd + H4(0)) = s1;
+clearl(vd, 1, sizeof(uint32_t), tot);
+}
+
+void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
+void *vs2, CPURISCVState *env, uint32_t desc)
+{
+uint32_t mlen = vext_mlen(desc);
+uint32_t vm = vext_vm(desc);
+uint32_t vl = env->vl;
+uint32_t i;
+uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+uint64_t s1 = *((uint64_t *)vs1);
+
+for (i = 0; i < vl; i++) {
+uint32_t s2 = *((uint32_t *)vs2 + H4(i));
+if (!vm && !vext_elem_mask(v0, mlen, i)) {
+continue;
+}
+s1 = float64_add(s1, float32_to_float64(s2, >fp_status),
+ >fp_status);
+}
+*((uint64_t *)vd) = s1;
+clearq(vd, 1, sizeof(uint64_t), tot);
+}
--
2.23.0
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
On 2020/6/3 1:54, Alistair Francis wrote:
On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote:
Hi Alistair,
There are still some questions I don't understand.
1. Is the baud rate or fifo a necessary feature to simulate?
As you can see, qemu_chr_fe_write will send the byte as soon as possible.
When you want to transmit a byte through WDATA, you can call
qemu_chr_fe_write directly.
So qemu_chr_fe_write() will send the data straight away. This doesn't
match what teh hardware does though. So by modelling a FIFO and a
delay in sending we can better match the hardware.
I see many UARTs have similar features. Does the software really care about
these features? Usually I just want to print something to the terminal
through UART.
Most simulation in QEMU is for running software, not exactly the details
of hardware.
For example, we will not simulate the 16x oversamples in this UART.
There is no error here. Personally I think it is necessary to simulate
the FIFO and baud rate,
maybe for supporting some backends.
Can someone give a reasonable answer for this question?
2. The baud rate calculation method is not strictly right.
I think when a byte write to FIFO, char_tx_time * 8 is the correct time
to send the byte instead of
char_tx_time * 4.
Do you mind explaining why 8 is correct instead of 4?
Usually write a byte to WDATA will trigger a uart_write_tx_fifo.
Translate a bit will take
char_tx_time. So it will take char_tx_time * 8 to transmit a byte.
3. Why add a watch here?
This is based on the Cadence UART implementation in QEMU (which does
the same thing). This will trigger a callback when we can write more
data or when the backend has hung up.
Many other serials do the same thing, like virtio-console and serial. So
it may be a common
interface here. I will try to understand it(Not yet).
Zhiwei
Alistair
+s->uart_status |= UART_STATUS_TXEMPTY;
+s->uart_intr_state |= INTR_STATE_TX_EMPTY;
+s->uart_intr_state &= ~INTR_STATE_TX_WATERMARK;
+ibex_uart_update_irqs(s);
+return FALSE;
+}
+
+ret = qemu_chr_fe_write(>chr, s->tx_fifo, s->tx_level);
+
+if (ret >= 0) {
+s->tx_level -= ret;
+memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
+}
+
+if (s->tx_level) {
+guint r = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP,
+ibex_uart_xmit, s);
+if (!r) {
+s->tx_level = 0;
+return FALSE;
+}
+}
+
Zhiwei
Re: hw/char: a question about watch callback function in serial
On 2020/6/5 10:19, LIU Zhiwei wrote: On 2020/6/4 21:32, Peter Maydell wrote: On Thu, 4 Jun 2020 at 13:15, LIU Zhiwei wrote: I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s->watch_tag = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, serial_watch_cb, s); In hw/candence_uart.c, it is cadence_uart_xmit, setting by the following code, guint r = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, cadence_uart_xmit, s); I tried to call it with booting a Linux, but the interface will never be called. Can someone give a reasonable answer why needs this interface, or a way to call it. This code is here to handle the case where the UART wants to pass data to the chardev which is acting as the backend to the UART (which might be host stdio, a TCP port, etc), but the backend cannot accept data. Older UART code (eg hw/char/pl011.c) calls qemu_chr_fe_write_all() to write data, but this is a blocking call and these calls are usually marked with an XXX/TODO comment, because if the chardev backend can't currently accept the data then execution of the guest will be blocked until the backend does start to accept data again. The solution to this bug was the introduction of the non-blocking qemu_chr_fe_write() call. But to use the non-blocking call, the UART emulation code now needs to handle the case where qemu_chr_fe_write() says "I couldn't write all the data you asked me to". In that case, it must use qemu_chr_fe_add_watch() to request a callback when the chardev is able to accept new data, so that it can try again. (It also needs to emulate telling the guest that the transmit FIFO is not yet empty via whatever status registers the UART has for that, because in the meantime guest execution will continue with some of the data still not sent to the chardev, but sitting in the emulated FIFO; and it needs to correctly emulate "guest tried to write more data to a full FIFO". Older UART emulations that use the blocking write_all function don't need to bother with these details because there the tx FIFO is always empty -- from the guest's perspective data written to the tx FIFO drains instantaneously.) The common case execution path is "the chardev can accept the data faster than the guest can feed it to the UART", in which case qemu_chr_fe_write() will return 'wrote all the data' and the UART never needs to call qemu_chr_fe_add_watch(). To exercise the add-watch codepath you need to connect the UART to a chardev that can be made to stop accepting data (for instance a pipe or a unix domain socket where there's nothing on the other end reading data.) Hi Peter, Thanks, it's really a reasonable answer. However I still have one question. When I tried to verify the code-path, the callback is not triggered. The serial I used is hw/serial.c, back ended with a named pipe. The first step is make named pipe by mkfifo xpipe Then run a RISC-V Linux by the command gdb --args qemu-system-riscv64 -M virt -kernel fw_jump.elf -device loader,file=Image,addr=0x8020 \ -append "rootwait root=/dev/vda ro" -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 -serial pipe:xpipe -smp 1 Set a breakpoint on serial_watch_cb before run the Linux b serial_watch_cb Then run the Linux. The breakpoint will never matched. I think "there is nothing on the other end reading data". Then I tried another way to verify. Read the pipe a little later after booting(There are some data in the FIFO already) by cat xpipe Now I can read some data out from the pipe. But it still can't match the breakpoint. I think the reading will set the G_IO_OUT condition, but it doesn't. Is there something wrong? Or could you show me a case./ / Hi folks, I find it's the pipe buffer size is big enough to contain all the output of Linux booting. So it will not call the qemu_chr_fe_add_watch. If I output more characters more than 64KB, it will call the qemu_chr_fe_add_watch and serial_watch_cb. By this way, I verify the code-path. Thanks Peter. It's really a right answer. Zhiwei/ / / /Best Regards, Zhiwei/ / thanks -- PMM
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
On 2020/6/5 11:30, Richard Henderson wrote:
On 6/4/20 7:50 PM, LIU Zhiwei wrote:
So no scalar insns will require changes within a translation block.
Not true -- scalar insns can encode rm into the instruction.
I think there is a error in gen_set_rm
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
if (ctx->frm == rm) {
return;
}
ctx->frm = rm;
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
}
I don't know why updating ctx->frm in this function.
This is a cache of the current rm, as most recently stored in
env->fp_status.rounding_mode.
So if we have
fadd.s ft0, ft0, ft0, rtz
fadd.s ft0, ft0, ft0, rtz
fadd.s ft0, ft0, ft0, rtz
we will only switch to round_to_zero once.
Get it, thanks.
Maybe I should only gen_set_rm(ctx, 7) for each vector float insn.
And the csr write method for frm or fcsr will not change.
So I will remove this patch in the next patch set.
Zhiwei
r~
fpu/softfloat: a question on BFloat 16 support on QEMU
Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What's your opinion about it? Should I expand the fpu/softfloat? Best Regards, Zhiwei
Re: fpu/softfloat: a question on BFloat 16 support on QEMU
On 2020/6/9 17:42, Alex Bennée wrote: LIU Zhiwei writes: On 2020/6/8 23:50, Alex Bennée wrote: LIU Zhiwei writes: Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What do you mean by re-use the float32 interface? Once I think bfloat16 can been converted to float32 by deposit32(0, 16, 16, bf16) Then do a bfloat16 op by float32 op. No I don't think you want to be munging things like that - best to decompose it into FloatParts and let the common code deal with the actual calculation. We've learnt the hard way that having lots of slightly different functions each dealing with edge cases and rounding ends up in mistakes creeping in. The common code path is well tested and a lot easier to understand. Get it. Thanks. If I am ready, I will upstream the bfloat16 code. Best Regards, Zhiwei At last, get the bfloat16 result by right shift the float32 result 16 bits. Again the common round and packing code should be agnostic to the underlying precision. Isn't bfloat16 going to be pretty much the same as float16 but with some slightly different float parameters for the different encoding? Agree. Like the float16 code it won't have to deal with any of the hardfloat wrappers so it should look pretty similar. Good idea. I will list the float16 interfaces, and try to emulate the bfloat16 one by one. I list float16 interfaces in softfloat.c alone. It counts 67 interfaces. What's your opinion about it? Should I expand the fpu/softfloat? bfloat16 is certainly going to become more common that we should have common softfloat code to handle it. It would be nice is TestFloat could exercise it as well. Thanks. I will try to use make check-softfloat to test bfloat16 interfaces. Best Regards, Zhiwei Best Regards, Zhiwei
Re: [PATCH v8 58/62] target/riscv: floating-point scalar move instructions
On 2020/6/5 5:32, Richard Henderson wrote:
On 5/21/20 2:44 AM, LIU Zhiwei wrote:
+static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
+{
+if (!s->vill && has_ext(s, RVF) &&
+(s->mstatus_fs != 0) && (s->sew != 0)) {
+unsigned int ofs = (8 << s->sew);
+unsigned int len = 64 - ofs;
+TCGv_i64 t_nan;
+
+vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
+/* NaN-box f[rd] as necessary for SEW */
+if (len) {
+t_nan = tcg_const_i64(UINT64_MAX);
+tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+t_nan, ofs, len);
+tcg_temp_free_i64(t_nan);
+}
I guess this is correct, but it looks odd.
I would have done
unsigned int len = 8 << s->sew;
if (len < 64) {
tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
MAKE_64BIT_MASK(len, 64 - len));
}
and to match, I might use
MAKE_64BIT_MASK(32, 32)
in trans_vfmv_s_f.
Thanks. It's much clear this way.
Zhiwei
Otherwise,
Reviewed-by: Richard Henderson
r~
Re: hw/char: a question about watch callback function in serial
On 2020/6/4 21:32, Peter Maydell wrote: On Thu, 4 Jun 2020 at 13:15, LIU Zhiwei wrote: I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s->watch_tag = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, serial_watch_cb, s); In hw/candence_uart.c, it is cadence_uart_xmit, setting by the following code, guint r = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, cadence_uart_xmit, s); I tried to call it with booting a Linux, but the interface will never be called. Can someone give a reasonable answer why needs this interface, or a way to call it. This code is here to handle the case where the UART wants to pass data to the chardev which is acting as the backend to the UART (which might be host stdio, a TCP port, etc), but the backend cannot accept data. Older UART code (eg hw/char/pl011.c) calls qemu_chr_fe_write_all() to write data, but this is a blocking call and these calls are usually marked with an XXX/TODO comment, because if the chardev backend can't currently accept the data then execution of the guest will be blocked until the backend does start to accept data again. The solution to this bug was the introduction of the non-blocking qemu_chr_fe_write() call. But to use the non-blocking call, the UART emulation code now needs to handle the case where qemu_chr_fe_write() says "I couldn't write all the data you asked me to". In that case, it must use qemu_chr_fe_add_watch() to request a callback when the chardev is able to accept new data, so that it can try again. (It also needs to emulate telling the guest that the transmit FIFO is not yet empty via whatever status registers the UART has for that, because in the meantime guest execution will continue with some of the data still not sent to the chardev, but sitting in the emulated FIFO; and it needs to correctly emulate "guest tried to write more data to a full FIFO". Older UART emulations that use the blocking write_all function don't need to bother with these details because there the tx FIFO is always empty -- from the guest's perspective data written to the tx FIFO drains instantaneously.) The common case execution path is "the chardev can accept the data faster than the guest can feed it to the UART", in which case qemu_chr_fe_write() will return 'wrote all the data' and the UART never needs to call qemu_chr_fe_add_watch(). To exercise the add-watch codepath you need to connect the UART to a chardev that can be made to stop accepting data (for instance a pipe or a unix domain socket where there's nothing on the other end reading data.) Hi Peter, Thanks, it's really a reasonable answer. However I still have one question. When I tried to verify the code-path, the callback is not triggered. The serial I used is hw/serial.c, back ended with a named pipe. The first step is make named pipe by mkfifo xpipe Then run a RISC-V Linux by the command gdb --args qemu-system-riscv64 -M virt -kernel fw_jump.elf -device loader,file=Image,addr=0x8020 \ -append "rootwait root=/dev/vda ro" -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 -serial pipe:xpipe -smp 1 Set a breakpoint on serial_watch_cb before run the Linux b serial_watch_cb Then run the Linux. The breakpoint will never matched. I think "there is nothing on the other end reading data". Then I tried another way to verify. Read the pipe a little later after booting(There are some data in the FIFO already) by cat xpipe Now I can read some data out from the pipe. But it still can't match the breakpoint. I think the reading will set the G_IO_OUT condition, but it doesn't. Is there something wrong? Or could you show me a case./ /Best Regards, Zhiwei/ / thanks -- PMM
Re: [PATCH v8 40/62] target/riscv: vector floating-point compare instructions
On 2020/6/5 4:51, Richard Henderson wrote:
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
+static uint8_t float16_eq_quiet(uint16_t a, uint16_t b, float_status *s)
Return bool, better than uint8_t.
Yes.
+{
+int compare = float16_compare_quiet(a, b, s);
New since your last revision is that compare should be type FloatRelation.
And similarly for the other 13 comparison helpers.
OK. I will use the FloatRelation in next patch set.
+vext_set_elem_mask(vd, mlen, i, DO_OP(s2, (ETYPE)s1,\
+ >fp_status)); \
Indentation is off. env->fp_status should align with DO_OP.
Yes. Thanks.
Zhiwei
With that,
Reviewed-by: Richard Henderson
r~
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
On 2020/6/5 4:15, Richard Henderson wrote:
On 6/2/20 10:46 PM, LIU Zhiwei wrote:
I think you are right. Maybe I should transmit frm to ctx->frm, and check
ctx->frm in vector fp ops.
We can set ctx->frm = env->frm instead of ctx->frm = -1 in
riscv_tr_init_disas_context.
And remove the sentence ctx->frm = rm; from gen_set_rm.
Is it right?
If we record frm in tb_flags, then we also have to reset
env->fp_status.rounding_mode for scalar fp insns which encode a rm != 7.
Depending on the exact mix of fp insns, that could result in more changes to
rounding_mode than we do presently. This is something that you'd want to look
at closely to make sure you're not making scalar code worse.
Hi Richard,
I don't think so. It will occupy three bits in tb_flags.
Another reason is the scalar float codes have fixed rounding mode. The
frm field in tb_flags is useless without vector extension.
If we really have to put it in the tb_flags, one bit INVALID_FRM is
enough. The scalar code will still be the same.
The vector code will check the INVALID_FRM.
I think the easiest solution in the short term is to have the translation of
any fp vector insn call gen_set_rm(ctx, 7), so that we are certain to install
frm as rounding_mode. This will happen at most once per translation block,
assuming no scalar insns that would also require changes to rounding_mode.
Yes. Only some csr insns can change the rounding mode. And they will
exit the tb immediately.
So no scalar insns will require changes within a translation block.
I think there is a error in gen_set_rm
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
if (ctx->frm == rm) {
return;
}
ctx->frm = rm;
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
}
I don't know why updating ctx->frm in this function.
You can work with the risc-v folk to examine frm handling more generally
separate from this vector work.
OK. I will send a separate RFC patch to handle frm. Then merge it to the
vector patch set.
Best Regards,
Zhiwei
r~
Re: [PATCH v9 39/61] target/riscv: vector floating-point compare instructions
On 2020/6/11 1:33, Richard Henderson wrote: On 6/10/20 4:37 AM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Richard Henderson --- Missed the actual "Reviewed-by:" :-) I tried to make a reasonable explanation, but failed:-). "Reviewed-by: " is really what I mean here. Zhiwei r~
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
On 2020/6/4 12:35, Alistair Francis wrote: On Wed, Jun 3, 2020 at 6:59 PM LIU Zhiwei wrote: On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi Alistair, There are still some questions I don't understand. 1. Is the baud rate or fifo a necessary feature to simulate? As you can see, qemu_chr_fe_write will send the byte as soon as possible. When you want to transmit a byte through WDATA, you can call qemu_chr_fe_write directly. So qemu_chr_fe_write() will send the data straight away. This doesn't match what teh hardware does though. So by modelling a FIFO and a delay in sending we can better match the hardware. I see many UARTs have similar features. Does the software really care about these features? Usually I just want to print something to the terminal through UART. In this case Tock (which is the OS used for OpenTitan) does car about these features as it relies on interrupts generated by the HW to complete the serial send task. It also just makes the QEMU model more accurate. Fair enough. I see the "tx_watermark" interrupt, which needs the FIFO. At least, it can verify the ISP. Exactly :) Most simulation in QEMU is for running software, not exactly the details of hardware. For example, we will not simulate the 16x oversamples in this UART. Agreed. Lots of UARTs don't bother modelling the delay from the hardware as generally it doesn't matter. In this case it does make a difference for the software and it makes the QEMU model more accurate, which is always a good thing. There is no error here. Personally I think it is necessary to simulate the FIFO and baud rate, maybe for supporting some backends. So baud rate doesn't need to be modelled as we aren't actually sending UART data, just pretending and then printing it. Can someone give a reasonable answer for this question? Which question? I see the UART can work with many different backends, such as pty , file, socket and so on. I wonder if this a backend, which has some requirements on the baud The backend should be independent so it doesn't matter what baud rate we choose here. rate. You can ignore it, as it doesn't matter. 2. The baud rate calculation method is not strictly right. I think when a byte write to FIFO, char_tx_time * 8 is the correct time to send the byte instead of char_tx_time * 4. Do you mind explaining why 8 is correct instead of 4? Usually write a byte to WDATA will trigger a uart_write_tx_fifo. Translate a bit will take char_tx_time. So it will take char_tx_time * 8 to transmit a byte. I see your point. I just used the 4 as that is what the Cadence one does. I don't think it matters too much as it's just the delay for a timer (that isn't used as an accurate timer). Got it. Just a way to send the bytes at sometime later. 3. Why add a watch here? This is based on the Cadence UART implementation in QEMU (which does the same thing). This will trigger a callback when we can write more data or when the backend has hung up. Many other serials do the same thing, like virtio-console and serial. So it may be a common interface here. I will try to understand it(Not yet). Yep, it's just a more complete model of that the HW does. I try to boot a RISC-V Linux, and set a breakpoint to a watch callback function. The breakpoint did't match. I just wonder if there is a case really need the callback function. AFAIK Linux doesn't support the Ibex UART (or Ibex at all) so it shouldn't be triggered. I tried with the UART in the virt board. It also registers the watch callback on G_IO_HUP and G_IO_OUT. However I will through the question alone in another mail. After the two points addressed, Reviewed-by: LIU Zhiwei Zhiwei Alistair Zhiwei Alistair
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
On 2020/6/4 12:35, Alistair Francis wrote: On Wed, Jun 3, 2020 at 6:59 PM LIU Zhiwei wrote: On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi Alistair, There are still some questions I don't understand. 1. Is the baud rate or fifo a necessary feature to simulate? As you can see, qemu_chr_fe_write will send the byte as soon as possible. When you want to transmit a byte through WDATA, you can call qemu_chr_fe_write directly. So qemu_chr_fe_write() will send the data straight away. This doesn't match what teh hardware does though. So by modelling a FIFO and a delay in sending we can better match the hardware. I see many UARTs have similar features. Does the software really care about these features? Usually I just want to print something to the terminal through UART. In this case Tock (which is the OS used for OpenTitan) does car about these features as it relies on interrupts generated by the HW to complete the serial send task. It also just makes the QEMU model more accurate. Fair enough. I see the "tx_watermark" interrupt, which needs the FIFO. At least, it can verify the ISP. Exactly :) Most simulation in QEMU is for running software, not exactly the details of hardware. For example, we will not simulate the 16x oversamples in this UART. Agreed. Lots of UARTs don't bother modelling the delay from the hardware as generally it doesn't matter. In this case it does make a difference for the software and it makes the QEMU model more accurate, which is always a good thing. There is no error here. Personally I think it is necessary to simulate the FIFO and baud rate, maybe for supporting some backends. So baud rate doesn't need to be modelled as we aren't actually sending UART data, just pretending and then printing it. Can someone give a reasonable answer for this question? Which question? I see the UART can work with many different backends, such as pty , file, socket and so on. I wonder if this a backend, which has some requirements on the baud The backend should be independent so it doesn't matter what baud rate we choose here. rate. You can ignore it, as it doesn't matter. 2. The baud rate calculation method is not strictly right. I think when a byte write to FIFO, char_tx_time * 8 is the correct time to send the byte instead of char_tx_time * 4. Do you mind explaining why 8 is correct instead of 4? Usually write a byte to WDATA will trigger a uart_write_tx_fifo. Translate a bit will take char_tx_time. So it will take char_tx_time * 8 to transmit a byte. I see your point. I just used the 4 as that is what the Cadence one does. I don't think it matters too much as it's just the delay for a timer (that isn't used as an accurate timer). Got it. Just a way to send the bytes at sometime later. 3. Why add a watch here? This is based on the Cadence UART implementation in QEMU (which does the same thing). This will trigger a callback when we can write more data or when the backend has hung up. Many other serials do the same thing, like virtio-console and serial. So it may be a common interface here. I will try to understand it(Not yet). Yep, it's just a more complete model of that the HW does. I try to boot a RISC-V Linux, and set a breakpoint to a watch callback function. The breakpoint did't match. I just wonder if there is a case really need the callback function. AFAIK Linux doesn't support the Ibex UART (or Ibex at all) so it shouldn't be triggered. I tried with the UART in the virt board. It also registers the watch callback on G_IO_HUP and G_IO_OUT. However I will throw the question alone in another thread. After the two comments pointed at another email addressed, Reviewed-by: LIU Zhiwei Zhiwei Alistair Zhiwei Alistair
Re: [PATCH v5 07/11] hw/char: Initial commit of Ibex UART
On 2020/6/3 23:56, Alistair Francis wrote: On Wed, Jun 3, 2020 at 3:33 AM LIU Zhiwei wrote: On 2020/6/3 1:54, Alistair Francis wrote: On Tue, Jun 2, 2020 at 5:28 AM LIU Zhiwei wrote: Hi Alistair, There are still some questions I don't understand. 1. Is the baud rate or fifo a necessary feature to simulate? As you can see, qemu_chr_fe_write will send the byte as soon as possible. When you want to transmit a byte through WDATA, you can call qemu_chr_fe_write directly. So qemu_chr_fe_write() will send the data straight away. This doesn't match what teh hardware does though. So by modelling a FIFO and a delay in sending we can better match the hardware. I see many UARTs have similar features. Does the software really care about these features? Usually I just want to print something to the terminal through UART. In this case Tock (which is the OS used for OpenTitan) does car about these features as it relies on interrupts generated by the HW to complete the serial send task. It also just makes the QEMU model more accurate. Fair enough. I see the "tx_watermark" interrupt, which needs the FIFO. At least, it can verify the ISP. Most simulation in QEMU is for running software, not exactly the details of hardware. For example, we will not simulate the 16x oversamples in this UART. Agreed. Lots of UARTs don't bother modelling the delay from the hardware as generally it doesn't matter. In this case it does make a difference for the software and it makes the QEMU model more accurate, which is always a good thing. There is no error here. Personally I think it is necessary to simulate the FIFO and baud rate, maybe for supporting some backends. So baud rate doesn't need to be modelled as we aren't actually sending UART data, just pretending and then printing it. Can someone give a reasonable answer for this question? Which question? I see the UART can work with many different backends, such as pty , file, socket and so on. I wonder if this a backend, which has some requirements on the baud rate. You can ignore it, as it doesn't matter. 2. The baud rate calculation method is not strictly right. I think when a byte write to FIFO, char_tx_time * 8 is the correct time to send the byte instead of char_tx_time * 4. Do you mind explaining why 8 is correct instead of 4? Usually write a byte to WDATA will trigger a uart_write_tx_fifo. Translate a bit will take char_tx_time. So it will take char_tx_time * 8 to transmit a byte. I see your point. I just used the 4 as that is what the Cadence one does. I don't think it matters too much as it's just the delay for a timer (that isn't used as an accurate timer). Got it. Just a way to send the bytes at sometime later. 3. Why add a watch here? This is based on the Cadence UART implementation in QEMU (which does the same thing). This will trigger a callback when we can write more data or when the backend has hung up. Many other serials do the same thing, like virtio-console and serial. So it may be a common interface here. I will try to understand it(Not yet). Yep, it's just a more complete model of that the HW does. I try to boot a RISC-V Linux, and set a breakpoint to a watch callback function. The breakpoint did't match. I just wonder if there is a case really need the callback function. Zhiwei Alistair
hw/char: a question about watch callback function in serial
Hi folks, I see many UART implementations have a G_IO_OUT | G_IO_HUP callback function. In hw/serial.c, it is serial_watch_cb, setting by the following code, s->watch_tag = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, serial_watch_cb, s); In hw/candence_uart.c, it is cadence_uart_xmit, setting by the following code, guint r = qemu_chr_fe_add_watch(>chr, G_IO_OUT | G_IO_HUP, cadence_uart_xmit, s); I tried to call it with booting a Linux, but the interface will never be called. Can someone give a reasonable answer why needs this interface, or a way to call it. Best Regards, Zhiwei
Re: [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes
On 2020/6/3 12:27, Richard Henderson wrote:
On 5/21/20 2:43 AM, LIU Zhiwei wrote:
@@ -174,6 +175,9 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
+if (!riscv_cpu_set_rounding_mode(env, env->frm)) {
+return -1;
+}
This will raise an exception immediately in helper_csrrw().
According to Section 8.2, the no exception should occur until the next fp
operation that uses the invalid frm.
You're doing this just fine in helper_set_rounding_mode(), which is sufficient
for scalar fp ops. Without looking forward to later patches, I suppose we'll
need to do something else for vector fp ops.
Hi Richard,
I think you are right. Maybe I should transmit frm to ctx->frm, and
check ctx->frm in vector fp ops.
We can set ctx->frm = env->frm instead of ctx->frm = -1 in
riscv_tr_init_disas_context.
And remove the sentence ctx->frm = rm; from gen_set_rm.
Is it right?
Zhiwei
r~
Re: fpu/softfloat: a question on BFloat 16 support on QEMU
On 2020/6/8 23:50, Alex Bennée wrote: LIU Zhiwei writes: Hi Richard, I am doing bfloat16 support on QEMU. Once I tried to reuse float32 interface, but I couldn't properly process rounding in some insns like fadd. What do you mean by re-use the float32 interface? Once I think bfloat16 can been converted to float32 by deposit32(0, 16, 16, bf16) Then do a bfloat16 op by float32 op. At last, get the bfloat16 result by right shift the float32 result 16 bits. Isn't bfloat16 going to be pretty much the same as float16 but with some slightly different float parameters for the different encoding? Agree. Like the float16 code it won't have to deal with any of the hardfloat wrappers so it should look pretty similar. Good idea. I will list the float16 interfaces, and try to emulate the bfloat16 one by one. I list float16 interfaces in softfloat.c alone. It counts 67 interfaces. What's your opinion about it? Should I expand the fpu/softfloat? bfloat16 is certainly going to become more common that we should have common softfloat code to handle it. It would be nice is TestFloat could exercise it as well. Thanks. I will try to use make check-softfloat to test bfloat16 interfaces. Best Regards, Zhiwei Best Regards, Zhiwei
Re: fpu/softfloat: a question on BFloat 16 support on QEMU
On 2020/6/9 3:34, Richard Henderson wrote:
On 6/8/20 5:53 AM, LIU Zhiwei wrote:
Hi Richard,
I am doing bfloat16 support on QEMU.
Once I tried to reuse float32 interface, but I couldn't properly process
rounding in some insns like fadd.
What's your opinion about it? Should I expand the fpu/softfloat?
Yes, we need to expand fpu/softfloat.
You'll want something like
static const FloatFmt bfloat16_params = {
FLOAT_PARAMS(8, 7)
};
(This would be the Arm and x86 definition, anyway; hopefully risc-v is the
same.)
Yes. It's the same for me.
And then add all of the other interface functions that you need to use that
parameter.
FWIW, it appears that Arm only requires:
float32_to_bfloat16
bfloat16_mul
bfloat16_add
and I could even get away with only float32_to_bfloat16, since technically
Arm's BFAdd and BFMul psuedo-code are implemented in terms of single-precision
arithmetic, followed by a round-to-odd into BFloat16.
Some different here.
It's directly implemented in half-precision unit. So I'm afraid I have
to implement as many as interfaces like float16.
Best Regards,
Zhiwei
r~
[PATCH 1/2] target/riscv: Quiet Coverity complains about vamo*
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index c0b7375927..7b4752b911 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -733,6 +733,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t
seq)
g_assert_not_reached();
#endif
} else {
+assert(seq < ARRAY_SIZE(fnsw));
fn = fnsw[seq];
}
}
--
2.23.0
[PATCH 2/2] target/riscv: fix vector index load/store constraints
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.inc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 7b4752b911..887c6b8883 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,
uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
+/*
+ * For vector indexed segment loads, the destination vector register
+ * groups cannot overlap the source vector register group (specified by
+ * `vs2`), else an illegal instruction exception is raised.
+ */
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
-vext_check_nf(s, a->nf));
+vext_check_nf(s, a->nf) &&
+((a->nf == 1) ||
+ vext_check_overlap_group(a->rd, a->nf << s->lmul,
+ a->rs2, 1 << s->lmul)));
}
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
--
2.23.0
Re: [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c
On 2020/7/24 8:28, Richard Henderson wrote: Make sure that all results from inline single-precision scalar operations are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index c7057482e8..264d3139f1 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], 0, 31); } +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); tcg_temp_free_i64(t0); } +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); tcg_temp_free_i64(t0); } +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); Reviewed-by: LIU Zhiwei Zhiwei
Re: [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
On 2020/7/24 8:28, Richard Henderson wrote:
Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.
Signed-off-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvf.inc.c | 16 +---
target/riscv/translate.c| 11 +++
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 3bfd8881e7..c7057482e8 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -23,20 +23,6 @@
return false; \
} while (0)
-/*
- * RISC-V requires NaN-boxing of narrower width floating
- * point values. This applies when a 32-bit value is
- * assigned to a 64-bit FP register. Thus this does not
- * apply when the RVD extension is not present.
- */
-static void gen_nanbox_fpr(DisasContext *ctx, int regno)
-{
-if (has_ext(ctx, RVD)) {
-tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno],
-MAKE_64BIT_MASK(32, 32));
-}
-}
-
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv t0 = tcg_temp_new();
@@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
-gen_nanbox_fpr(ctx, a->rd);
+gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
tcg_temp_free(t0);
mark_fs_dirty(ctx);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..12a746da97 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+/*
+ * RISC-V requires NaN-boxing of narrower width floating point values.
+ * This applies when a 32-bit value is assigned to a 64-bit FP register.
+ * For consistency and simplicity, we nanbox results even when the RVD
+ * extension is not present.
+ */
+static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
+{
+tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
+}
+
If possible,
+static void gen_nanbox(TCGv_i64 out, TCGv_i64 in, uint32_t flen)
+{
+tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(flen, 64 - flen));
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
Re: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers
On 2020/7/24 8:28, Richard Henderson wrote:
If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson
---
target/riscv/internals.h | 11 +++
target/riscv/fpu_helper.c | 64 ---
2 files changed, 57 insertions(+), 18 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 9f4ba7d617..f1a546dba6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -43,4 +43,15 @@ static inline uint64_t nanbox_s(float32 f)
return f | MAKE_64BIT_MASK(32, 32);
}
+static inline float32 check_nanbox_s(uint64_t f)
+{
+uint64_t mask = MAKE_64BIT_MASK(32, 32);
+
+if (likely((f & mask) == mask)) {
+return (uint32_t)f;
+} else {
+return 0x7fc0u; /* default qnan */
+}
+}
+
If possible,
+static inline float32 check_nanbox(uint64_t f, uint32_t flen)
+{
+uint64_t mask = MAKE_64BIT_MASK(flen, 64 - flen);
+
+if (likely((f & mask) == mask)) {
+return (uint32_t)f;
+} else {
+return (flen == 32) ? 0x7fc0u : 0x7e00u; /* default qnan */
+}
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
#endif
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 72541958a7..bb346a8249 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,9 +81,12 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
set_float_rounding_mode(softrm, >fp_status);
}
-static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
- uint64_t frs3, int flags)
+static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
+ uint64_t rs3, int flags)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
+float32 frs3 = check_nanbox_s(rs3);
return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, >fp_status));
}
@@ -139,74 +142,97 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
float_muladd_negate_product, >fp_status);
}
-uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_add(frs1, frs2, >fp_status));
}
-uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_sub(frs1, frs2, >fp_status));
}
-uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_mul(frs1, frs2, >fp_status));
}
-uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_div(frs1, frs2, >fp_status));
}
-uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_minnum(frs1, frs2, >fp_status));
}
-uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return nanbox_s(float32_maxnum(frs1, frs2, >fp_status));
}
-uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
+uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
{
+float32 frs1 = check_nanbox_s(rs1);
return nanbox_s(float32_sqrt(frs1, >fp_status));
}
-target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return float32_le(frs1, frs2, >fp_status);
}
-target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
+float32 frs1 = check_nanbox_s(rs1);
+float32 frs2 = check_nanbox_s(rs2);
return float32_lt(frs1, frs2, >fp_status);
}
-target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2
Re: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison
On 2020/7/24 8:28, Richard Henderson wrote:
This is my take on Liu Zhiwei's patch set:
https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_...@c-sky.com
This differs from Zhiwei's v1 in:
* If a helper is involved, the helper does the boxing and unboxing.
* Which leaves only LDW and FSGN*.S as the only instructions that
are expanded inline which need to handle nanboxing.
* All mention of RVD is dropped vs boxing. This means that an
RVF-only cpu will still generate and check nanboxes into the
64-bit cpu_fpu slots. There should be no way an RVF-only cpu
can generate an unboxed cpu_fpu value.
This choice is made to speed up the common case: RVF+RVD, so
that we do not have to check whether RVD is enabled.
* The translate.c primitives take TCGv values rather than fpu
regno, which will make it possible to use them with RVV,
since v0.9 does proper nanboxing.
Agree.
And I think this patch set should be applied if possible, because it is
bug fix.
* I have adjusted the current naming to be float32 specific ("*_s"),
to avoid confusion with the float16 data type supported by RVV.
It's OK.
A more general function with flen is better in my opinion. So that it
can be used
everywhere, both in scalar and vector instructions, even the future fp16 or
bf16 instructions.
Zhiwei
r~
LIU Zhiwei (2):
target/riscv: Clean up fmv.w.x
target/riscv: check before allocating TCG temps
Richard Henderson (5):
target/riscv: Generate nanboxed results from fp helpers
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
target/riscv: Generate nanboxed results from trans_rvf.inc.c
target/riscv: Check nanboxed inputs to fp helpers
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
target/riscv/internals.h| 16
target/riscv/fpu_helper.c | 102
target/riscv/insn_trans/trans_rvd.inc.c | 8 +-
target/riscv/insn_trans/trans_rvf.inc.c | 99 ++-
target/riscv/translate.c| 29 +++
5 files changed, 178 insertions(+), 76 deletions(-)
Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
On 2020/7/24 11:55, Richard Henderson wrote:
On 7/23/20 7:35 PM, LIU Zhiwei wrote:
On 2020/7/24 8:28, Richard Henderson wrote:
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson
---
target/riscv/internals.h | 5 +
target/riscv/fpu_helper.c | 42 +--
2 files changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 37d33820ad..9f4ba7d617 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+static inline uint64_t nanbox_s(float32 f)
+{
+ return f | MAKE_64BIT_MASK(32, 32);
+}
+
If define it here, we can also define a more general function with flen.
+static inline uint64_t nanbox_s(float32 f, uint32_t flen)
+{
+ return f | MAKE_64BIT_MASK(flen, 64 - flen);
+}
+
So we can reuse it in fp16 or bf16 scalar instruction and in vector
instructions.
While we could do that, we will not encounter all possible lengths. In the
cover letter, I mentioned defining a second function,
static inline uint64_t nanbox_h(float16 f)
{
return f | MAKE_64BIT_MASK(16, 48);
}
Having two separate functions will, I believe, be easier to use in practice.
Get it. Thanks.
Zhiwei
r~
Re: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+tcg_temp_free_i64(t_max);
+tcg_temp_free_i64(t_nan);
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
On 2020/7/24 8:28, Richard Henderson wrote:
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson
---
target/riscv/internals.h | 5 +
target/riscv/fpu_helper.c | 42 +--
2 files changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 37d33820ad..9f4ba7d617 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+static inline uint64_t nanbox_s(float32 f)
+{
+return f | MAKE_64BIT_MASK(32, 32);
+}
+
If define it here, we can also define a more general function with flen.
+static inline uint64_t nanbox_s(float32 f, uint32_t flen)
+{
+return f | MAKE_64BIT_MASK(flen, 64 - flen);
+}
+
So we can reuse it in fp16 or bf16 scalar instruction and in vector
instructions.
Reviewed-by: LIU Zhiwei
Zhiwei
#endif
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 4379756dc4..72541958a7 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,10 +81,16 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
set_float_rounding_mode(softrm, >fp_status);
}
+static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+ uint64_t frs3, int flags)
+{
+return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, >fp_status));
+}
+
uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
-return float32_muladd(frs1, frs2, frs3, 0, >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, 0);
}
uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -96,8 +102,7 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1,
uint64_t frs2,
uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c,
- >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c);
}
uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -110,8 +115,7 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1,
uint64_t frs2,
uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product,
- >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product);
}
uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -124,8 +128,8 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1,
uint64_t frs2,
uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
-return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c |
- float_muladd_negate_product, >fp_status);
+return do_fmadd_s(env, frs1, frs2, frs3,
+ float_muladd_negate_c | float_muladd_negate_product);
}
uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
@@ -137,37 +141,37 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t
frs1, uint64_t frs2,
uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_add(frs1, frs2, >fp_status);
+return nanbox_s(float32_add(frs1, frs2, >fp_status));
}
uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_sub(frs1, frs2, >fp_status);
+return nanbox_s(float32_sub(frs1, frs2, >fp_status));
}
uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_mul(frs1, frs2, >fp_status);
+return nanbox_s(float32_mul(frs1, frs2, >fp_status));
}
uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_div(frs1, frs2, >fp_status);
+return nanbox_s(float32_div(frs1, frs2, >fp_status));
}
uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_minnum(frs1, frs2, >fp_status);
+return nanbox_s(float32_minnum(frs1, frs2, >fp_status));
}
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
{
-return float32_maxnum(frs1, frs2, >fp_status);
+return nanbox_s(float32_maxnum(frs1, frs2, >fp_status));
}
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
{
-return float32_sqrt(frs1, >fp_status);
+return nanbox_s(float32_sqrt(frs1, >fp_status));
}
target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
@
Re: [PULL v2 12/64] target/riscv: add vector amo operations
On 2020/7/7 7:36, Alistair Francis wrote:
On Sun, Jul 5, 2020 at 11:20 AM Peter Maydell wrote:
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
From: LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Hi; Coverity thinks (probably wrongly) that there might be an array
overflow here:
+static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+{
+uint32_t data = 0;
+gen_helper_amo *fn;
+static gen_helper_amo *const fnsw[9] = {
This is a 9-element array...
+/* no atomic operation */
+gen_helper_vamoswapw_v_w,
+gen_helper_vamoaddw_v_w,
+gen_helper_vamoxorw_v_w,
+gen_helper_vamoandw_v_w,
+gen_helper_vamoorw_v_w,
+gen_helper_vamominw_v_w,
+gen_helper_vamomaxw_v_w,
+gen_helper_vamominuw_v_w,
+gen_helper_vamomaxuw_v_w
+};
+if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+gen_helper_exit_atomic(cpu_env);
+s->base.is_jmp = DISAS_NORETURN;
+return true;
+} else {
+if (s->sew == 3) {
+#ifdef TARGET_RISCV64
+fn = fnsd[seq];
+#else
+/* Check done in amo_check(). */
+g_assert_not_reached();
+#endif
+} else {
+fn = fnsw[seq];
...which we here index via 'seq'...
+#ifdef TARGET_RISCV64
+GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
+GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+#endif
...which in the calls that these macros expand out to can
be 9 or greater.
If it's in fact impossible to get into that code path
with a value of seq that's larger than the array, it
would help Coverity if we asserted so, maybe
assert(seq < ARRAY_SIZE(fnsw));
This is CID 1430177, 1430178, 1430179, 1430180, 1430181,
1430182, 1430183, 1430184, 1430185, 14305186.
@ LIU Zhiwei can you please look into this and send a patch with a fix?
Sure.
I will think about Richard's comments before I send a patch to fix it.
I applied for a Coverity account just a moment ago, so that I can see
what the CID details.
Best Regards,
Zhiwei
Alistair
thanks
-- PMM
[PATCH 4/4] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
>From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds
of layouts according to HCR_EL2.E2H.
When HCR_EL2.E2H is 1, fp_exception_el should refer to
HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN.
Reviewed-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
target/arm/helper.c | 55 +
1 file changed, 46 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 38cd35c049..6cc9f2bb50 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6147,11 +6147,30 @@ int sve_exception_el(CPUARMState *env, int el)
* they will be zero when EL2 is not present.
*/
if (el <= 2 && !arm_is_secure_below_el3(env)) {
-if (env->cp15.cptr_el[2] & CPTR_TZ) {
-return 2;
-}
-if (env->cp15.cptr_el[2] & CPTR_TFP) {
-return 0;
+/* Since we exclude secure first, we may read HCR_EL2 directly. */
+if (env->cp15.hcr_el2 & HCR_E2H) {
+int zen = extract32(env->cp15.cptr_el[2], 16, 2);
+switch (zen) {
+case 0:
+case 2:
+return 2;
+case 1:
+if (env->cp15.hcr_el2 & HCR_TGE) {
+if (el == 0) {
+return 2;
+}
+}
+break;
+case 3:
+break;
+}
+} else {
+if (env->cp15.cptr_el[2] & CPTR_TZ) {
+return 2;
+}
+if (env->cp15.cptr_el[2] & CPTR_TFP) {
+return 0;
+}
}
}
@@ -12635,12 +12654,30 @@ int fp_exception_el(CPUARMState *env, int cur_el)
*/
/* CPTR_EL2 : present in v7VE or v8 */
-if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
-&& !arm_is_secure_below_el3(env)) {
+if ((cur_el <= 2) && !arm_is_secure_below_el3(env)) {
/* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
-return 2;
+if ((arm_hcr_el2_eff(env) & HCR_E2H) == HCR_E2H) {
+int fpen = extract32(env->cp15.cptr_el[2], 20, 2);
+switch (fpen) {
+case 0:
+case 2:
+return 2;
+case 1:
+if ((arm_hcr_el2_eff(env) & HCR_TGE) == HCR_TGE) {
+if (cur_el == 0) {
+return 2;
+}
+}
+break;
+case 3:
+break;
+}
+} else {
+if (extract32(env->cp15.cptr_el[2], 10, 1)) {
+return 2;
+}
+}
}
-
/* CPTR_EL3 : present in v8 */
if (extract32(env->cp15.cptr_el[3], 10, 1)) {
/* Trap all FP ops to EL3 */
--
2.23.0
[PATCH 0/4] target/arm bug fix
I found some bugs in target/arm. The first one is about SVE first-fault or no-fault load/store. The second is SIMD fcmla(by element). The third is about CPTR_EL2. I am not sure I really understand this code. Please confirm the patch set and let me know if I am wrong. LIU Zhiwei (4): target/arm: Fixup special cross page case for sve continuous load/store target/arm: Fixup contiguous first-fault and no-fault loads target/arm: Fixup SIMD fcmla(by element) in 4H arrangement target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H target/arm/helper.c | 55 ++--- target/arm/sve_helper.c | 42 --- target/arm/vec_helper.c | 8 ++ 3 files changed, 82 insertions(+), 23 deletions(-) -- 2.23.0
