[SeaBIOS] [PATCH 2/5] pci: activate two-pass pci initialization code
This patch actually enables the two-pass pci initialization and
deactivates the old pci initialization bits.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
src/pciinit.c | 38 ++
1 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index 9314698..a26eb77 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -123,6 +123,8 @@ static void pci_set_io_region_addr(u16 bdf, int region_num,
u32 addr)
*/
static int pci_bios_allocate_region(u16 bdf, int region_num)
{
+return 0;
+
struct pci_region *r;
u32 ofs = pci_bar(bdf, region_num);
@@ -184,6 +186,8 @@ static int pci_bios_allocate_region(u16 bdf, int region_num)
static void pci_bios_allocate_regions(struct pci_device *pci, void *arg)
{
+return;
+
int i;
for (i = 0; i PCI_NUM_REGIONS; i++) {
int is_64bit = pci_bios_allocate_region(pci-bdf, i);
@@ -239,6 +243,7 @@ static const struct pci_device_id pci_isa_bridge_tbl[] = {
#define PCI_PREF_MEMORY_ALIGN (1UL 20)
#define PCI_PREF_MEMORY_SHIFT 16
+#if 0
static void pci_bios_init_device_bridge(struct pci_device *pci, void *arg)
{
u16 bdf = pci-bdf;
@@ -323,6 +328,7 @@ static void pci_bios_init_device_bridge(struct pci_device
*pci, void *arg)
pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
}
+#endif
static void storage_ide_init(struct pci_device *pci, void *arg)
{
@@ -374,9 +380,11 @@ static const struct pci_device_id pci_class_tbl[] = {
PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
+#if 0
/* PCI bridge */
PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
pci_bios_init_device_bridge),
+#endif
/* default */
PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
@@ -607,6 +615,7 @@ static void pci_bios_check_device(struct pci_bus *bus,
struct pci_device *dev)
static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
{
+u16 bdf = dev-bdf;
int type, i;
if (dev-class == PCI_CLASS_BRIDGE_PCI) {
@@ -614,13 +623,32 @@ static void pci_bios_map_device(struct pci_bus *bus,
struct pci_device *dev)
return;
}
struct pci_bus *s = busses + dev-secondary_bus;
+u32 base, limit;
for (type = 0; type PCI_REGION_TYPE_COUNT; type++) {
s-r[type].base = pci_bios_bus_get_addr(bus, type,
s-r[type].size);
}
dprintf(1, PCI: init bases bus %d (secondary)\n, dev-secondary_bus);
pci_bios_init_bus_bases(s);
-/* TODO: commit assignments */
+
+base = s-r[PCI_REGION_TYPE_IO].base;
+limit = base + s-r[PCI_REGION_TYPE_IO].size - 1;
+pci_config_writeb(bdf, PCI_IO_BASE, base PCI_IO_SHIFT);
+pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
+pci_config_writeb(bdf, PCI_IO_LIMIT, limit PCI_IO_SHIFT);
+pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
+
+base = s-r[PCI_REGION_TYPE_MEM].base;
+limit = base + s-r[PCI_REGION_TYPE_MEM].size - 1;
+pci_config_writew(bdf, PCI_MEMORY_BASE, base PCI_MEMORY_SHIFT);
+pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit PCI_MEMORY_SHIFT);
+
+base = s-r[PCI_REGION_TYPE_PREFMEM].base;
+limit = base + s-r[PCI_REGION_TYPE_PREFMEM].size - 1;
+pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base
PCI_PREF_MEMORY_SHIFT);
+pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit
PCI_PREF_MEMORY_SHIFT);
+pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
+pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
pci_bios_map_device_in_bus(dev-secondary_bus);
return;
@@ -637,7 +665,7 @@ static void pci_bios_map_device(struct pci_bus *bus, struct
pci_device *dev)
dprintf(1, bar %d, addr %x, size %x [%s]\n,
i, addr, dev-bars[i].size,
dev-bars[i].addr PCI_BASE_ADDRESS_SPACE_IO ? io : mem);
-/* TODO: commit assignments */
+pci_set_io_region_addr(bdf, i, addr);
if (dev-bars[i].is64) {
i++;
@@ -758,8 +786,7 @@ pci_setup(void)
memset(busses, 0, sizeof(*busses) * busses_count);
pci_bios_check_device_in_bus(0 /* host bus */);
if (pci_bios_init_root_regions(start, end) != 0) {
-dprintf(1, PCI: out of address space\n);
-/* Hmm, what do now? */
+panic(PCI: out of address space\n);
}
dprintf(1, === PCI new allocation pass #2 ===\n);
@@ -767,11 +794,14 @@ pci_setup(void)
pci_bios_init_bus_bases(busses[0]);
pci_bios_map_device_in_bus(0 /* host bus */);
+#if 0
dprintf(1, === PCI old allocation pass ===\n);
struct pci_device *pci;
foreachpci(pci) {
pci_init_device(pci_isa_bridge_tbl, pci, NULL);
}
+#endif
+
pci_bios_init_device_in_bus(0 /* host bus */);
[SeaBIOS] [PATCH 5/5] pci: set BUILD_PCIMEM_START to 0xe0000000
... and make it match with the declarations in acpi-dsdt.dsl. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 687cac6..f2fce89 100644 --- a/src/config.h +++ b/src/config.h @@ -40,7 +40,7 @@ #define BUILD_BIOS_TMP_ADDR 0x3 #define BUILD_MAX_HIGHMEM 0xe000 -#define BUILD_PCIMEM_START0xf000 +#define BUILD_PCIMEM_START0xe000 #define BUILD_PCIMEM_SIZE (BUILD_PCIMEM_END - BUILD_PCIMEM_START) #define BUILD_PCIMEM_END 0xfec0/* IOAPIC is mapped at */ -- 1.7.1 ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 0/5] pci: two-pass initialization
Hi, Next (and hopefully final) version of the two-pass pci initialization patches. Addressed review comments, fixed some bugs, especially the io range setup for bridges. cheers, Gerd Gerd Hoffmann (5): pci: add two-pass pci initialization code pci: activate two-pass pci initialization code pci: remove old pci initilaization code pci: cleanup config.h pci: set BUILD_PCIMEM_START to 0xe000 Makefile |2 +- src/config.h | 16 +-- src/pci.h|8 + src/pci_region.c | 77 src/pciinit.c| 509 ++ src/util.h | 29 --- 6 files changed, 335 insertions(+), 306 deletions(-) delete mode 100644 src/pci_region.c ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
[SeaBIOS] [PATCH 3/5] pci: remove old pci initilaization code
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
Makefile |2 +-
src/pci_region.c | 77 -
src/pciinit.c| 197 --
src/util.h | 29
4 files changed, 1 insertions(+), 304 deletions(-)
delete mode 100644 src/pci_region.c
diff --git a/Makefile b/Makefile
index 2786c9e..47828e5 100644
--- a/Makefile
+++ b/Makefile
@@ -20,7 +20,7 @@ SRC16=$(SRCBOTH) system.c disk.c font.c
SRC32FLAT=$(SRCBOTH) post.c shadow.c memmap.c coreboot.c boot.c \
acpi.c smm.c mptable.c smbios.c pciinit.c optionroms.c mtrr.c \
lzmadecode.c bootsplash.c jpeg.c usb-hub.c paravirt.c \
- pci_region.c biostables.c xen.c bmp.c
+ biostables.c xen.c bmp.c
SRC32SEG=util.c output.c pci.c pcibios.c apm.c stacks.c
cc-option = $(shell if test -z `$(1) $(2) -S -o /dev/null -xc \
diff --git a/src/pci_region.c b/src/pci_region.c
deleted file mode 100644
index 1d9de71..000
--- a/src/pci_region.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// helper functions to manage pci io/memory/prefetch memory region
-//
-// Copyright (C) 2009 Isaku Yamahata yamahata at valinux co jp
-//
-// This file may be distributed under the terms of the GNU LGPLv3 license.
-//
-//
-
-#include util.h
-
-#define PCI_REGION_DISABLED (-1)
-
-void pci_region_init(struct pci_region *r, u32 first, u32 last)
-{
-r-first = first;
-r-last = last;
-
-r-cur_first = r-first;
-}
-
-// PCI_REGION_DISABLED represents that the region is in special state.
-// its value is chosen such that cur_first can't be PCI_REGION_DISABLED
-// normally.
-// NOTE: the area right below 4G is used for LAPIC, so such area can't
-// be used for PCI memory.
-u32 pci_region_disable(struct pci_region *r)
-{
-return r-cur_first = PCI_REGION_DISABLED;
-}
-
-static int pci_region_disabled(const struct pci_region *r)
-{
-return r-cur_first == PCI_REGION_DISABLED;
-}
-
-static u32 pci_region_alloc_align(struct pci_region *r, u32 size, u32 align)
-{
-if (pci_region_disabled(r)) {
-return 0;
-}
-
-u32 s = ALIGN(r-cur_first, align);
-if (s r-last || s r-cur_first) {
-return 0;
-}
-u32 e = s + size;
-if (e s || e - 1 r-last) {
-return 0;
-}
-r-cur_first = e;
-return s;
-}
-
-u32 pci_region_alloc(struct pci_region *r, u32 size)
-{
-return pci_region_alloc_align(r, size, size);
-}
-
-u32 pci_region_align(struct pci_region *r, u32 align)
-{
-return pci_region_alloc_align(r, 0, align);
-}
-
-void pci_region_revert(struct pci_region *r, u32 addr)
-{
-r-cur_first = addr;
-}
-
-u32 pci_region_addr(const struct pci_region *r)
-{
-return r-cur_first;
-}
-
-u32 pci_region_size(const struct pci_region *r)
-{
-return r-last - r-first + 1;
-}
diff --git a/src/pciinit.c b/src/pciinit.c
index a26eb77..a0e932b 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -18,10 +18,6 @@
#define PCI_BRIDGE_IO_MIN 0x1000
#define PCI_BRIDGE_MEM_MIN 0x10
-static struct pci_region pci_bios_io_region;
-static struct pci_region pci_bios_mem_region;
-static struct pci_region pci_bios_prefmem_region;
-
enum pci_region_type {
PCI_REGION_TYPE_IO,
PCI_REGION_TYPE_MEM,
@@ -113,88 +109,6 @@ static void pci_set_io_region_addr(u16 bdf, int
region_num, u32 addr)
ofs = pci_bar(bdf, region_num);
pci_config_writel(bdf, ofs, addr);
-dprintf(1, region %d: 0x%08x\n, region_num, addr);
-}
-
-/*
- * return value
- * 0: 32bit BAR
- * non 0: 64bit BAR
- */
-static int pci_bios_allocate_region(u16 bdf, int region_num)
-{
-return 0;
-
-struct pci_region *r;
-u32 ofs = pci_bar(bdf, region_num);
-
-u32 old = pci_config_readl(bdf, ofs);
-u32 mask;
-if (region_num == PCI_ROM_SLOT) {
-mask = PCI_ROM_ADDRESS_MASK;
-pci_config_writel(bdf, ofs, mask);
-} else {
-if (old PCI_BASE_ADDRESS_SPACE_IO)
-mask = PCI_BASE_ADDRESS_IO_MASK;
-else
-mask = PCI_BASE_ADDRESS_MEM_MASK;
-pci_config_writel(bdf, ofs, ~0);
-}
-u32 val = pci_config_readl(bdf, ofs);
-pci_config_writel(bdf, ofs, old);
-
-u32 size = (~(val mask)) + 1;
-if (val != 0) {
-const char *type;
-const char *msg;
-if (val PCI_BASE_ADDRESS_SPACE_IO) {
-r = pci_bios_io_region;
-type = io;
-msg = ;
-} else if ((val PCI_BASE_ADDRESS_MEM_PREFETCH)
- /* keep behaviour on bus = 0 */
- pci_bdf_to_bus(bdf) != 0
- /* If pci_bios_prefmem_addr == 0, keep old behaviour */
- pci_region_addr(pci_bios_prefmem_region) != 0) {
-r = pci_bios_prefmem_region;
-type = prefmem;
-msg = decrease BUILD_PCIMEM_SIZE and recompile. size %x;
-} else {
-r = pci_bios_mem_region;
-type = mem;
-msg = increase BUILD_PCIMEM_SIZE and
[SeaBIOS] [PATCH 4/5] pci: cleanup config.h
Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h | 14 -- src/pciinit.c |2 +- 2 files changed, 1 insertions(+), 15 deletions(-) diff --git a/src/config.h b/src/config.h index e6e07c9..687cac6 100644 --- a/src/config.h +++ b/src/config.h @@ -40,23 +40,9 @@ #define BUILD_BIOS_TMP_ADDR 0x3 #define BUILD_MAX_HIGHMEM 0xe000 -// Support old pci mem assignment behaviour -//#define CONFIG_OLD_PCIMEM_ASSIGNMENT1 -#if CONFIG_OLD_PCIMEM_ASSIGNMENT #define BUILD_PCIMEM_START0xf000 #define BUILD_PCIMEM_SIZE (BUILD_PCIMEM_END - BUILD_PCIMEM_START) #define BUILD_PCIMEM_END 0xfec0/* IOAPIC is mapped at */ -#define BUILD_PCIPREFMEM_START0 -#define BUILD_PCIPREFMEM_SIZE 0 -#define BUILD_PCIPREFMEM_END 0 -#else -#define BUILD_PCIMEM_START0xf000 -#define BUILD_PCIMEM_SIZE 0x0800/* half- of pci window */ -#define BUILD_PCIMEM_END (BUILD_PCIMEM_START + BUILD_PCIMEM_SIZE) -#define BUILD_PCIPREFMEM_STARTBUILD_PCIMEM_END -#define BUILD_PCIPREFMEM_SIZE (BUILD_PCIPREFMEM_END - BUILD_PCIPREFMEM_START) -#define BUILD_PCIPREFMEM_END 0xfec0/* IOAPIC is mapped at */ -#endif #define BUILD_APIC_ADDR 0xfee0 #define BUILD_IOAPIC_ADDR 0xfec0 diff --git a/src/pciinit.c b/src/pciinit.c index a0e932b..6331fdf 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -584,7 +584,7 @@ pci_setup(void) dprintf(3, pci setup\n); u32 start = BUILD_PCIMEM_START; -u32 end = BUILD_IOAPIC_ADDR; +u32 end = BUILD_PCIMEM_END; dprintf(1, === PCI bus bridge init ===\n); pci_bios_init_bus(); -- 1.7.1 ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [PATCH 5/5] pci: set BUILD_PCIMEM_START to 0xe0000000
On Mon, Jul 11, 2011 at 09:20:32AM +0200, Gerd Hoffmann wrote: ... and make it match with the declarations in acpi-dsdt.dsl. Signed-off-by: Gerd Hoffmann kra...@redhat.com --- src/config.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 687cac6..f2fce89 100644 --- a/src/config.h +++ b/src/config.h @@ -40,7 +40,7 @@ #define BUILD_BIOS_TMP_ADDR 0x3 #define BUILD_MAX_HIGHMEM 0xe000 -#define BUILD_PCIMEM_START0xf000 +#define BUILD_PCIMEM_START0xe000 I thought there was some dependency on 0xe000 in the VGA BIOS. Has that been cleared up now? The patch series looks good to me. -Kevin ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] [PATCH 5/5] pci: set BUILD_PCIMEM_START to 0xe0000000
Hi, -#define BUILD_PCIMEM_START0xf000 +#define BUILD_PCIMEM_START0xe000 I thought there was some dependency on 0xe000 in the VGA BIOS. Has that been cleared up now? Yes, the magic bochs vga lfb @ 0xe000 is gone in recent qemu (version 0.14 + newer). The vgabios looks up the framebuffer bar address in pci config space instead of depending on the hardcoded address. And even when combining this with old qemu this is quite unlikely to actually cause trouble as the code tries to move the pci bars as high as possible. On a typical qemu configuration the lowest address used is 0xfc00. cheers, Gerd ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
Re: [SeaBIOS] SeaBIOS error with Juniper FreeBSD kernel
Are all versions based on FreeBSD 4.11? Are newer versions still affected? Newer versions should be based on 6.1 but there are a lot of changes. I haven't had a chance to test with something newer yet. -Brandon ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios
