Re: [SeaBIOS] Failure to detect high-capacity SD card
On Sat, Oct 28, 2017 at 10:26 AM, Kevin O'Connor wrote: > Okay. One more thing to try is a slightly different voltage range. > > -Kevin > > > --- a/src/hw/sdcard.c > +++ b/src/hw/sdcard.c > @@ -123,6 +123,17 @@ struct sdhci_s { > #define SRF_DATA 0x04 > > // SDHCI result flags > +#define SR_OCR_VDD_165_195 (1<<7) > +#define SR_OCR_VDD_27_28 (1<<15) > +#define SR_OCR_VDD_28_29 (1<<16) > +#define SR_OCR_VDD_29_30 (1<<17) > +#define SR_OCR_VDD_30_31 (1<<18) > +#define SR_OCR_VDD_31_32 (1<<19) > +#define SR_OCR_VDD_32_33 (1<<20) > +#define SR_OCR_VDD_33_34 (1<<21) > +#define SR_OCR_VDD_34_35 (1<<22) > +#define SR_OCR_VDD_35_36 (1<<23) > +#define SR_OCR_S18R(1<<24) > #define SR_OCR_CCS (1<<30) > #define SR_OCR_NOTBUSY (1<<31) > > @@ -181,7 +192,7 @@ static int > sdcard_pio(struct sdhci_s *regs, int cmd, u32 *param) > { > u32 state = readl(®s->present_state); > -dprintf(9, "sdcard_pio cmd %x %x %x\n", cmd, *param, state); > +dprintf(1, "sdcard_pio cmd %x %x %x\n", cmd, *param, state); > if ((state & SP_CMD_INHIBIT) > || ((cmd & 0x03) == 0x03 && state & SP_DAT_INHIBIT)) { > dprintf(1, "sdcard_pio not ready %x\n", state); > @@ -203,7 +214,7 @@ sdcard_pio(struct sdhci_s *regs, int cmd, u32 *param) > writew(®s->irq_status, SI_CMD_COMPLETE); > // Read response > memcpy(param, regs->response, sizeof(regs->response)); > -dprintf(9, "sdcard cmd %x response %x %x %x %x\n" > +dprintf(1, "sdcard cmd %x response %x %x %x %x\n" > , cmd, param[0], param[1], param[2], param[3]); > return 0; > } > @@ -302,13 +313,13 @@ sdcard_set_power(struct sdhci_s *regs) > u32 cap = readl(®s->cap_lo); > u32 volt, vbits; > if (cap & SD_CAPLO_V33) { > -volt = 1<<20; > +volt = SR_OCR_VDD_32_33 | SR_OCR_VDD_33_34; > vbits = SPC_V33; > } else if (cap & SD_CAPLO_V30) { > -volt = 1<<18; > +volt = SR_OCR_VDD_29_30 | SR_OCR_VDD_30_31; > vbits = SPC_V30; > } else if (cap & SD_CAPLO_V18) { > -volt = 1<<7; > +volt = SR_OCR_VDD_165_195; > vbits = SPC_V18; > } else { > dprintf(1, "SD controller unsupported volt range (%x)\n", cap); > @@ -399,11 +410,11 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, > int prio) > if (ret) > return ret; > // Let card know SDHC/SDXC is supported and confirm voltage > -u32 hcs = 0, vrange = (volt >= (1<<15) ? 0x100 : 0x200) | 0xaa; > +u32 hcs = 0, vrange = (volt >= SR_OCR_VDD_27_28 ? 0x100 : 0x200) | > 0xaa; > param[0] = vrange; > ret = sdcard_pio(regs, SC_SEND_IF_COND, param); > if (!ret && param[0] == vrange) > -hcs = (1<<30); > +hcs = SR_OCR_CCS | (1<<28); > // Verify SD card (instead of MMC or SDIO) > param[0] = 0x00; > ret = sdcard_pio_app(regs, SC_APP_SEND_OP_COND, param); > @@ -414,8 +425,12 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, > int prio) > if (ret) > return ret; > drive->card_type |= SF_MMC; > -hcs = (1<<30); > +hcs = SR_OCR_CCS; > } > +// XXX > +if (volt == (SR_OCR_VDD_32_33 | SR_OCR_VDD_33_34) > +&& hcs && readl(®s->cap_lo) & SD_CAPLO_V18) > +hcs |= SR_OCR_S18R; > // Init card > u32 end = timer_calc(SDHCI_POWERUP_TIMEOUT); > for (;;) { > @@ -434,6 +449,10 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, > int prio) > } > msleep(5); // Avoid flooding log when debugging > } > +if (param[0] & SR_OCR_S18R) { > +dprintf(1, "Card requests 1.8 volt\n"); > +return -1; > +} > drive->card_type |= (param[0] & SR_OCR_CCS) ? SF_HIGHCAPACITY : 0; > // Select card (get cid, set rca, get csd, select card) > param[0] = 0x00; > no luck, log attached SeaBIOS (version rel-1.10.0-82-g6ebb3b1-MrChromebox-2017.10.28) BUILD: gcc: (Ubuntu 7.2.0-8ubuntu3) 7.2.0 binutils: (GNU Binutils for Ubuntu) 2.29.1 Found coreboot cbmem console @ 7acde000 Found mainboard Google Cave malloc preinit Relocating init from 0x000ed580 to 0x7aa03900 (size 30304) malloc init Found CBFS header at 0xffbfffdc Add romfile: payload (size=81080) Add romfile: pci8086,0406.rom (size=65536) Add romfile: bootorder (size=32) Add romfile: links (size=144) Add romfile: etc/boot-menu-wait (size=8) Add romfile: (size=1949784) Copying data 144@0xffa23e38 to 144@0x7aa032f0 Add romfile: pci8086,1906.rom (size=65536) Add romfile: pci8086,1916.rom (size=65536) Add romfile: pci8086,191e.rom (size=65536) init ivt init bda Copying data 32@0xffa23db8 to 32@0x7aa03360 boot order: 1: /pci@i0cf8/*@1f,2/drive@0/disk@0 init bios32 init PMM init PNPBIOS table init keyboard init pic math cp init PCI probe Found 19 PCI devices (max PCI bus is 01) Relocating coreboot bios tables Copying SMBIOS entry point from 0x7aa4b000 to 0x000f4bc0 Copying ACPI RSDP from 0x7ab5c000 to 0x000f4b90 CPU Mhz=914 init timer Scan fo
Re: [SeaBIOS] Failure to detect high-capacity SD card
On Fri, Oct 27, 2017 at 08:26:35PM -0500, Matt DeVillier wrote: > On Fri, Oct 27, 2017 at 7:08 PM, Kevin O'Connor wrote: > > > Can you try the two patches below? (Go back to master, apply the > > first, gather the log, go back to master, apply the second, gather the > > log.) > > > > -Kevin > > > > w/patch 1 only: https://paste.ubuntu.com/25833503/ > > w/patch 2 only: https://paste.ubuntu.com/25833542/ Okay. One more thing to try is a slightly different voltage range. -Kevin --- a/src/hw/sdcard.c +++ b/src/hw/sdcard.c @@ -123,6 +123,17 @@ struct sdhci_s { #define SRF_DATA 0x04 // SDHCI result flags +#define SR_OCR_VDD_165_195 (1<<7) +#define SR_OCR_VDD_27_28 (1<<15) +#define SR_OCR_VDD_28_29 (1<<16) +#define SR_OCR_VDD_29_30 (1<<17) +#define SR_OCR_VDD_30_31 (1<<18) +#define SR_OCR_VDD_31_32 (1<<19) +#define SR_OCR_VDD_32_33 (1<<20) +#define SR_OCR_VDD_33_34 (1<<21) +#define SR_OCR_VDD_34_35 (1<<22) +#define SR_OCR_VDD_35_36 (1<<23) +#define SR_OCR_S18R(1<<24) #define SR_OCR_CCS (1<<30) #define SR_OCR_NOTBUSY (1<<31) @@ -181,7 +192,7 @@ static int sdcard_pio(struct sdhci_s *regs, int cmd, u32 *param) { u32 state = readl(®s->present_state); -dprintf(9, "sdcard_pio cmd %x %x %x\n", cmd, *param, state); +dprintf(1, "sdcard_pio cmd %x %x %x\n", cmd, *param, state); if ((state & SP_CMD_INHIBIT) || ((cmd & 0x03) == 0x03 && state & SP_DAT_INHIBIT)) { dprintf(1, "sdcard_pio not ready %x\n", state); @@ -203,7 +214,7 @@ sdcard_pio(struct sdhci_s *regs, int cmd, u32 *param) writew(®s->irq_status, SI_CMD_COMPLETE); // Read response memcpy(param, regs->response, sizeof(regs->response)); -dprintf(9, "sdcard cmd %x response %x %x %x %x\n" +dprintf(1, "sdcard cmd %x response %x %x %x %x\n" , cmd, param[0], param[1], param[2], param[3]); return 0; } @@ -302,13 +313,13 @@ sdcard_set_power(struct sdhci_s *regs) u32 cap = readl(®s->cap_lo); u32 volt, vbits; if (cap & SD_CAPLO_V33) { -volt = 1<<20; +volt = SR_OCR_VDD_32_33 | SR_OCR_VDD_33_34; vbits = SPC_V33; } else if (cap & SD_CAPLO_V30) { -volt = 1<<18; +volt = SR_OCR_VDD_29_30 | SR_OCR_VDD_30_31; vbits = SPC_V30; } else if (cap & SD_CAPLO_V18) { -volt = 1<<7; +volt = SR_OCR_VDD_165_195; vbits = SPC_V18; } else { dprintf(1, "SD controller unsupported volt range (%x)\n", cap); @@ -399,11 +410,11 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, int prio) if (ret) return ret; // Let card know SDHC/SDXC is supported and confirm voltage -u32 hcs = 0, vrange = (volt >= (1<<15) ? 0x100 : 0x200) | 0xaa; +u32 hcs = 0, vrange = (volt >= SR_OCR_VDD_27_28 ? 0x100 : 0x200) | 0xaa; param[0] = vrange; ret = sdcard_pio(regs, SC_SEND_IF_COND, param); if (!ret && param[0] == vrange) -hcs = (1<<30); +hcs = SR_OCR_CCS | (1<<28); // Verify SD card (instead of MMC or SDIO) param[0] = 0x00; ret = sdcard_pio_app(regs, SC_APP_SEND_OP_COND, param); @@ -414,8 +425,12 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, int prio) if (ret) return ret; drive->card_type |= SF_MMC; -hcs = (1<<30); +hcs = SR_OCR_CCS; } +// XXX +if (volt == (SR_OCR_VDD_32_33 | SR_OCR_VDD_33_34) +&& hcs && readl(®s->cap_lo) & SD_CAPLO_V18) +hcs |= SR_OCR_S18R; // Init card u32 end = timer_calc(SDHCI_POWERUP_TIMEOUT); for (;;) { @@ -434,6 +449,10 @@ sdcard_card_setup(struct sddrive_s *drive, int volt, int prio) } msleep(5); // Avoid flooding log when debugging } +if (param[0] & SR_OCR_S18R) { +dprintf(1, "Card requests 1.8 volt\n"); +return -1; +} drive->card_type |= (param[0] & SR_OCR_CCS) ? SF_HIGHCAPACITY : 0; // Select card (get cid, set rca, get csd, select card) param[0] = 0x00; ___ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios