Re: [SeaBIOS] [PATCH] Add config option to disable MTRRinitialization.

2011-03-17 Thread Sebastian Herbszt 

Kevin O'Connor wrote:

On Tue, Mar 15, 2011 at 11:29:21PM +0100, Sebastian Herbszt wrote:

I was now able to reproduce it:

[...]

It happens because your Bochs 2.4.5 version was compiled without
x86-64 support and --enable-long-phy-address and only supports
32-bit phys_bits. You can recompile it or upgrade to 2.4.6 to fix
this.


It sounds like SeaBIOS should be able to detect this at runtime and
apply the right mask.  The mtrr code in seabios came from Bochs BIOS -
which I think was just for kvm.  So, maybe just some tweaks are needed
here.

-Kevin


A Bochs CPU level 6 processor should support 36 bits. SeaBIOS assumes
this and sets phys_bits to 36. If CPUID leaf 0x8008 is available this 
assumption
is modified and the supplied value is used. The Bochs CPU code suggests this 
leaf is
only available on 64-bit CPUs.
If you compile Bochs 2.4.5 without --enable-long-phy-address the valid 36 bit
assumption is violated and you get a family 6 CPU with only 32 bits.
I don't think trying to fix the detection is worth it, because the problem 
disappears with
Bochs version 2.4.6 or --enable-long-phy-address on older versions.

Sebastian


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Re: [SeaBIOS] [PATCH] Add config option to disable MTRRinitialization.

2011-03-16 Thread Kevin O'Connor 
On Tue, Mar 15, 2011 at 11:29:21PM +0100, Sebastian Herbszt wrote:
 I was now able to reproduce it:
[...]
 It happens because your Bochs 2.4.5 version was compiled without
 x86-64 support and --enable-long-phy-address and only supports
 32-bit phys_bits. You can recompile it or upgrade to 2.4.6 to fix
 this.

It sounds like SeaBIOS should be able to detect this at runtime and
apply the right mask.  The mtrr code in seabios came from Bochs BIOS -
which I think was just for kvm.  So, maybe just some tweaks are needed
here.

-Kevin

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Re: [SeaBIOS] [PATCH] Add config option to disable MTRRinitialization.

2011-03-15 Thread Sebastian Herbszt 

Sebastian Herbszt wrote:

Kevin O'Connor wrote:

On Thu, Mar 10, 2011 at 10:50:30PM +0100, Sebastian Herbszt wrote:

Kevin O'Connor wrote:
On Mon, Mar 07, 2011 at 09:37:59PM +0100, Sebastian Herbszt wrote:
Kevin O'Connor wrote:
Some versions of Bochs don't like the MTRR initialization, so add
I ran into it with the version fc14 has - Bochs v2.4.5.  I get:

00034041578i[CPU0 ] 0x01fe28e9 wrmsr  : 0F30
00034041578e[CPU0 ] exception(): 3rd (13) exception with no resolution, 
shutdown status is 00h, resetting
00034041578i[SYS  ] bx_pc_system_c::Reset(HARDWARE) called
00034041578i[CPU0 ] cpu hardware reset

and then the boot restarts.  The issue goes away if I disable the MTRR
init.
Can you please post your cpuid lines from your bochsrc file and
the CPU configuration related lines from the top of the bochsout.txt
file?


I don't have a bochsrc - I just run:

bochs -q 'floppya: 1_44=odin1440.img, status=inserted' 'romimage: 
file=../seabios/out/bios.bin'

and then select option '6'.  Below is the system config output:

000i[ ] Bochs x86 Emulator 2.4.5.cvs
000i[ ]   Build from CVS snapshot, after release 2.4.5
000i[ ] System configuration
000i[ ]   processors: 1 (cores=1, HT threads=1)
000i[ ]   A20 line support: yes
000i[ ] CPU configuration
000i[ ]   level: 6
000i[ ]   SMP support: no
000i[ ]   APIC support: yes
000i[ ]   FPU support: yes
000i[ ]   MMX support: yes
000i[ ]   3dnow! support: yes
000i[ ]   SEP support: yes
000i[ ]   SSE support: sse2
000i[ ]   XSAVE support: no
000i[ ]   AES support: no
000i[ ]   MOVBE support: no
000i[ ]   x86-64 support: no
000i[ ]   MWAIT support: no
000i[ ]   VMX support: no

-Kevin


Stanislav, you happen to know why WRMSR is not recognized here?


I was now able to reproduce it:

0449408i[BIOS ] init mtrr
00023940129e[CPU0 ] WRMSR[0x0201]: attempt to write invalid phy addr to 
variable range MTRR 000f:e800
00023940129e[CPU0 ] interrupt(): vector must be within IDT table limits, 
IDT.limit = 0x0
00023940129e[CPU0 ] interrupt(): vector must be within IDT table limits, 
IDT.limit = 0x0
00023940129i[CPU0 ] CPU is in protected mode (active)
00023940129i[CPU0 ] CS.d_b = 32 bit
00023940129i[CPU0 ] SS.d_b = 32 bit
00023940129i[CPU0 ] | EAX=e800  EBX=0201  ECX=0201  EDX=000f
00023940129i[CPU0 ] | ESP=6eec  EBP=0008  ESI=000f  EDI=0210
00023940129i[CPU0 ] | IOPL=0 id vip vif ac vm RF nt of df if tf sf zf af pf cf
00023940129i[CPU0 ] | SEG selector baselimit G D
00023940129i[CPU0 ] | SEG sltr(index|ti|rpl) baselimit G D
00023940129i[CPU0 ] |  CS:0008( 0001| 0|  0)   1 1
00023940129i[CPU0 ] |  DS:0010( 0002| 0|  0)   1 1
00023940129i[CPU0 ] |  SS:0010( 0002| 0|  0)   1 1
00023940129i[CPU0 ] |  ES:0010( 0002| 0|  0)   1 1
00023940129i[CPU0 ] |  FS:0010( 0002| 0|  0)   1 1
00023940129i[CPU0 ] |  GS:0010( 0002| 0|  0)   1 1
00023940129i[CPU0 ] | EIP=01fe1bd2 (01fe1bd2)
00023940129i[CPU0 ] | CR0=0x0011 CR2=0x
00023940129i[CPU0 ] | CR3=0x CR4=0x
00023940129i[CPU0 ] 0x01fe1bd2 wrmsr  : 0F30
00023940129e[CPU0 ] exception(): 3rd (13) exception with no resolution, 
shutdown status is 00h, resetting

It happens because your Bochs 2.4.5 version was compiled without x86-64 support 
and --enable-long-phy-address
and only supports 32-bit phys_bits. You can recompile it or upgrade to 2.4.6 to 
fix this.

Sebastian


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Re: [SeaBIOS] [PATCH] Add config option to disable MTRRinitialization.

2011-03-14 Thread Scott Duplichan 
Sebastian Herbszt wrote:

] 00034041578i[CPU0 ] 0x01fe28e9 wrmsr  : 0F30
] 00034041578e[CPU0 ] exception(): 3rd (13) exception with no resolution, 
shutdown status is 00h,
]
]Stanislav, you happen to know why WRMSR is not recognized here?
]
]Sebastian

If it works like real hardware, it is exception 6 that would tell you the
instruction is not supporteed, not exception 13. Exception 13h during MTRR
initialization is most often because of too many mask bits set when writing
the mask part of a variable MTRR pair (ecx=201,203,...20Fh). Software
should call cpuid function 8008h to find out how many bits can safely be
set in the variable MTRR mask. Setting reserved bits in the fixed MTRRs
might also be able to cause a GP fault.

Thanks,
Scott


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