Re: [SeaBIOS] [RFC v2 2/3] pci_device: Add pci domain support
Marcel Apfelbaum 于2018年8月25日周六 下午7:53写道：
>
>
>
> On 08/09/2018 08:43 AM, Zihan Yang wrote:
> > Most part of seabios assume only PCI domain 0. This patch adds support
> > for multiple domain in pci devices, which involves some API changes.
> >
> > For compatibility, interfaces such as pci_config_read[b|w|l] still exist
> > so that existing domain 0 devices needs no modification, but whenever a
> > device wants to reside in different domain, it should add *_dom suffix to
> > above functions, e.g, pci_config_readl_dom(..., domain_nr) to read from
> > specific host bridge other than q35 host bridge.
>
> It is not related only to q35. Is about PCI hosts bridges others
> that the main one.
I see, I will correct it.
> > Also, the user should
> > check the device domain when using foreachpci() macro to fileter undesired
> > devices that reside in a different domain.
> >
> > Signed-off-by: Zihan Yang
> > ---
> > src/fw/coreboot.c | 2 +-
> > src/fw/csm.c | 2 +-
> > src/fw/paravirt.c | 2 +-
> > src/fw/pciinit.c | 261
> > ++---
> > src/hw/pci.c | 69 +++---
> > src/hw/pci.h | 42 ++---
> > src/hw/pci_ids.h | 7 +-
> > src/hw/pcidevice.c | 8 +-
> > src/hw/pcidevice.h | 4 +-
> > 9 files changed, 227 insertions(+), 170 deletions(-)
> >
> > diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c
> > index 7c0954b..c955dfd 100644
> > --- a/src/fw/coreboot.c
> > +++ b/src/fw/coreboot.c
> > @@ -254,7 +254,7 @@ coreboot_platform_setup(void)
> > {
> > if (!CONFIG_COREBOOT)
> > return;
> > -pci_probe_devices();
> > +pci_probe_devices(0);
> >
> > struct cb_memory *cbm = CBMemTable;
> > if (!cbm)
> > diff --git a/src/fw/csm.c b/src/fw/csm.c
> > index 03b4bb8..e94f614 100644
> > --- a/src/fw/csm.c
> > +++ b/src/fw/csm.c
> > @@ -63,7 +63,7 @@ static void
> > csm_maininit(struct bregs *regs)
> > {
> > interface_init();
> > -pci_probe_devices();
> > +pci_probe_devices(0);
> >
> > csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS;
> > csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset();
> > diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c
> > index 6b14542..ef4d487 100644
> > --- a/src/fw/paravirt.c
> > +++ b/src/fw/paravirt.c
> > @@ -155,7 +155,7 @@ qemu_platform_setup(void)
> > return;
> >
> > if (runningOnXen()) {
> > -pci_probe_devices();
> > +pci_probe_devices(0);
> > xen_hypercall_setup();
> > xen_biostable_setup();
> > return;
> > diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
> > index 6e6a434..fcdcd38 100644
> > --- a/src/fw/pciinit.c
> > +++ b/src/fw/pciinit.c
> > @@ -51,6 +51,7 @@ u64 pcimem_end = BUILD_PCIMEM_END;
> > u64 pcimem64_start = BUILD_PCIMEM64_START;
> > u64 pcimem64_end = BUILD_PCIMEM64_END;
> > u64 pci_io_low_end = 0xa000;
> > +u64 pxb_mcfg_size = 0;
> >
> > struct pci_region_entry {
> > struct pci_device *dev;
> > @@ -88,9 +89,9 @@ static void
> > pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int
> > is64)
> > {
> > u32 ofs = pci_bar(pci, bar);
> > -pci_config_writel(pci->bdf, ofs, addr);
> > +pci_config_writel_dom(pci->bdf, ofs, addr, pci->domain_nr);
> > if (is64)
> > -pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
> > +pci_config_writel_dom(pci->bdf, ofs + 4, addr >> 32,
> > pci->domain_nr);
> > }
> >
> >
> > @@ -405,25 +406,29 @@ static void pci_bios_init_device(struct pci_device
> > *pci)
> >
> > /* map the interrupt */
> > u16 bdf = pci->bdf;
> > -int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
> > +int pin = pci_config_readb_dom(bdf, PCI_INTERRUPT_PIN, pci->domain_nr);
> > if (pin != 0)
> > -pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci,
> > pin));
> > +pci_config_writeb_dom(bdf, PCI_INTERRUPT_LINE,
> > pci_slot_get_irq(pci, pin),
> > + pci->domain_nr);
> >
> > pci_init_device(pci_device_tbl, pci, NULL);
> >
> > /* enable memory mappings */
> > -pci_config_maskw(bdf, PCI_COMMAND, 0,
> > - PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> > PCI_COMMAND_SERR);
> > +pci_config_maskw_dom(bdf, PCI_COMMAND, 0,
> > + PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> > PCI_COMMAND_SERR,
> > + pci->domain_nr);
> > /* enable SERR# for forwarding */
> > if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
> > -pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
> > - PCI_BRIDGE_CTL_SERR);
> > +pci_config_maskw_dom(bdf, PCI_BRIDGE_CONTROL, 0,
> > + PCI_BRIDGE_CTL_SERR, pci->domain_nr);
> > }
> >
> > -static void pci_bios_init_devices(void)
> > +static void pci_bios_init_devices(int domain_nr)
> > {
> > struct pci_device *pci;
> >
Re: [SeaBIOS] [RFC v2 2/3] pci_device: Add pci domain support
On 08/09/2018 08:43 AM, Zihan Yang wrote:
Most part of seabios assume only PCI domain 0. This patch adds support
for multiple domain in pci devices, which involves some API changes.
For compatibility, interfaces such as pci_config_read[b|w|l] still exist
so that existing domain 0 devices needs no modification, but whenever a
device wants to reside in different domain, it should add *_dom suffix to
above functions, e.g, pci_config_readl_dom(..., domain_nr) to read from
specific host bridge other than q35 host bridge.
It is not related only to q35. Is about PCI hosts bridges others
that the main one.
Also, the user should
check the device domain when using foreachpci() macro to fileter undesired
devices that reside in a different domain.
Signed-off-by: Zihan Yang
---
src/fw/coreboot.c | 2 +-
src/fw/csm.c | 2 +-
src/fw/paravirt.c | 2 +-
src/fw/pciinit.c | 261 ++---
src/hw/pci.c | 69 +++---
src/hw/pci.h | 42 ++---
src/hw/pci_ids.h | 7 +-
src/hw/pcidevice.c | 8 +-
src/hw/pcidevice.h | 4 +-
9 files changed, 227 insertions(+), 170 deletions(-)
diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c
index 7c0954b..c955dfd 100644
--- a/src/fw/coreboot.c
+++ b/src/fw/coreboot.c
@@ -254,7 +254,7 @@ coreboot_platform_setup(void)
{
if (!CONFIG_COREBOOT)
return;
-pci_probe_devices();
+pci_probe_devices(0);
struct cb_memory *cbm = CBMemTable;
if (!cbm)
diff --git a/src/fw/csm.c b/src/fw/csm.c
index 03b4bb8..e94f614 100644
--- a/src/fw/csm.c
+++ b/src/fw/csm.c
@@ -63,7 +63,7 @@ static void
csm_maininit(struct bregs *regs)
{
interface_init();
-pci_probe_devices();
+pci_probe_devices(0);
csm_compat_table.PnPInstallationCheckSegment = SEG_BIOS;
csm_compat_table.PnPInstallationCheckOffset = get_pnp_offset();
diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c
index 6b14542..ef4d487 100644
--- a/src/fw/paravirt.c
+++ b/src/fw/paravirt.c
@@ -155,7 +155,7 @@ qemu_platform_setup(void)
return;
if (runningOnXen()) {
-pci_probe_devices();
+pci_probe_devices(0);
xen_hypercall_setup();
xen_biostable_setup();
return;
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 6e6a434..fcdcd38 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -51,6 +51,7 @@ u64 pcimem_end = BUILD_PCIMEM_END;
u64 pcimem64_start = BUILD_PCIMEM64_START;
u64 pcimem64_end = BUILD_PCIMEM64_END;
u64 pci_io_low_end = 0xa000;
+u64 pxb_mcfg_size = 0;
struct pci_region_entry {
struct pci_device *dev;
@@ -88,9 +89,9 @@ static void
pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
{
u32 ofs = pci_bar(pci, bar);
-pci_config_writel(pci->bdf, ofs, addr);
+pci_config_writel_dom(pci->bdf, ofs, addr, pci->domain_nr);
if (is64)
-pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
+pci_config_writel_dom(pci->bdf, ofs + 4, addr >> 32, pci->domain_nr);
}
@@ -405,25 +406,29 @@ static void pci_bios_init_device(struct pci_device *pci)
/* map the interrupt */
u16 bdf = pci->bdf;
-int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
+int pin = pci_config_readb_dom(bdf, PCI_INTERRUPT_PIN, pci->domain_nr);
if (pin != 0)
-pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
+pci_config_writeb_dom(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci,
pin),
+ pci->domain_nr);
pci_init_device(pci_device_tbl, pci, NULL);
/* enable memory mappings */
-pci_config_maskw(bdf, PCI_COMMAND, 0,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
+pci_config_maskw_dom(bdf, PCI_COMMAND, 0,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR,
+ pci->domain_nr);
/* enable SERR# for forwarding */
if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
-pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
- PCI_BRIDGE_CTL_SERR);
+pci_config_maskw_dom(bdf, PCI_BRIDGE_CONTROL, 0,
+ PCI_BRIDGE_CTL_SERR, pci->domain_nr);
}
-static void pci_bios_init_devices(void)
+static void pci_bios_init_devices(int domain_nr)
{
struct pci_device *pci;
foreachpci(pci) {
+if (pci->domain_nr != domain_nr)
+continue;
pci_bios_init_device(pci);
}
}
@@ -520,6 +525,10 @@ static void pxb_mem_addr_setup(struct pci_device *dev,
void *arg)
It seems is a new function, but I can't find the definition.
Can you please point me to it?
* read mcfg_base and mcfg_size from it just now. Instead, we directly add
* this item to e820 */
e820_add(mcfg_base.val, mcfg_size, E820_RESERVED);
+
+/* Add PXBHosts so that we can can initialize them later */
+
