On Tue, Jun 27, 2006 at 05:05:43PM +1000, David Hart wrote:
> AMD has taken out some very interesting patents whereby certain process
> scheduling operations are moved from the OS into silicon
>From reading that patent and a related paper [1] it seems that the
speculative execution on another processor (or processor thread) is
kicked off on a particular instruction and speculatively executes
instructions from the current thread; the particular patent deals with
getting things out the other end in the right order.
It seems this is very effective for loop based code, where the
compiler can find a lot of other things to do. But have a look at the
figures for IPC on less helpful code; it doesn't seem there is enough
work being found to make it effective. The authors argue that it is
simpler hardware, so you could increase clock rate.
You're essentially turning two superscalar processors into one with
speculative execution (Itanium anyone?). We know that even finding
enough instructions to keep the units on a standard superscalar busy
is almost impossible, so, unless you make the compiler much smarter
there is still a bottle neck of finding enough to do (Itanium
anyone?).
Personally, I think we're all going to have to bite the bullet and
learn to write parallelisable code. For a good discussion on this,
see "The problem with threads" from May's IEEE Computer [2].
> http://1url.org/go/1USP6574725
A great site I have found is www.pat2pdf.org which puts these in a
little more readable form.
[1] http://citeseer.ist.psu.edu/krishnan99chipmultiprocessor.html
[2]
http://www.computer.org/portal/site/computer/index.jsp?pageID=computer_level1_article&TheCat=1005&path=computer/homepage/0506&file=cover.xml&xsl=article.xsl
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