CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Tue May 28 06:57:03 UTC 2024
Modified Files:
src/sys/arch/riscv/include: netbsd32_machdep.h
Log Message:
Change MIPS to RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/netbsd32_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/netbsd32_machdep.h
diff -u src/sys/arch/riscv/include/netbsd32_machdep.h:1.1 src/sys/arch/riscv/include/netbsd32_machdep.h:1.2
--- src/sys/arch/riscv/include/netbsd32_machdep.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/netbsd32_machdep.h Tue May 28 06:57:03 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: netbsd32_machdep.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: netbsd32_machdep.h,v 1.2 2024/05/28 06:57:03 skrll Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include
/*
- * On MIPS, pointers are signed.
+ * On RISC-V, pointers are signed.
*/
#define NETBSD32_POINTER_TYPE int32_t
typedef struct { NETBSD32_POINTER_TYPE i32; } netbsd32_pointer_t;
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue May 28 06:57:03 UTC 2024 Modified Files: src/sys/arch/riscv/include: netbsd32_machdep.h Log Message: Change MIPS to RISC-V. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/netbsd32_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:17:57 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.
These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).
I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.32 src/sys/arch/riscv/include/sysreg.h:1.33
--- src/sys/arch/riscv/include/sysreg.h:1.32 Tue May 14 15:16:51 2024
+++ src/sys/arch/riscv/include/sysreg.h Tue May 14 15:17:57 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.32 2024/05/14 15:16:51 riastradh Exp $ */
+/* $NetBSD: sysreg.h,v 1.33 2024/05/14 15:17:57 riastradh Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@ static inline uint32_t
fcsr_read(void)
{
uint32_t __fcsr;
- asm volatile("frcsr %0" : "=r"(__fcsr) :: "memory");
+ asm("frcsr %0" : "=r"(__fcsr) :: "memory");
return __fcsr;
}
@@ -73,7 +73,7 @@ static inline uint32_t
fcsr_fflags_read(void)
{
uint32_t __old;
- asm volatile("frflags %0" : "=r"(__old) :: "memory");
+ asm("frflags %0" : "=r"(__old) :: "memory");
return __old;
}
@@ -89,7 +89,7 @@ static inline uint32_t
fcsr_frm_read(void)
{
uint32_t __old;
- asm volatile("frrm\t%0" : "=r"(__old) :: "memory");
+ asm("frrm\t%0" : "=r"(__old) :: "memory");
return __old;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue May 14 15:17:57 UTC 2024 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: riscv: No volatile needed on asm to _read_ rounding mode, exceptions. These instructions can be omitted if the return values are unused. In contrast, _writes_ to the rounding mode or exceptions must not be omitted (even if we ignore the return value, which is the old value of the field). I think "memory" is the wrong clobber on these asm blocks too; they can't be reordered around _floating-point_ instructions, while reordering around loads and stores is fine. But I don't know how to spell the right thing in gcclish. To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:16:51 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: Fix reading and writing frm and fflags.
The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.31 src/sys/arch/riscv/include/sysreg.h:1.32
--- src/sys/arch/riscv/include/sysreg.h:1.31 Mon Feb 5 21:46:05 2024
+++ src/sys/arch/riscv/include/sysreg.h Tue May 14 15:16:51 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.31 2024/02/05 21:46:05 andvar Exp $ */
+/* $NetBSD: sysreg.h,v 1.32 2024/05/14 15:16:51 riastradh Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -61,7 +61,6 @@ fcsr_read(void)
return __fcsr;
}
-
static inline uint32_t
fcsr_write(uint32_t __new)
{
@@ -75,16 +74,15 @@ fcsr_fflags_read(void)
{
uint32_t __old;
asm volatile("frflags %0" : "=r"(__old) :: "memory");
- return __SHIFTOUT(__old, FCSR_FFLAGS);
+ return __old;
}
static inline uint32_t
fcsr_fflags_write(uint32_t __new)
{
uint32_t __old;
- __new = __SHIFTIN(__new, FCSR_FFLAGS);
asm volatile("fsflags %0, %1" : "=r"(__old) : "r"(__new) : "memory");
- return __SHIFTOUT(__old, FCSR_FFLAGS);
+ return __old;
}
static inline uint32_t
@@ -92,19 +90,17 @@ fcsr_frm_read(void)
{
uint32_t __old;
asm volatile("frrm\t%0" : "=r"(__old) :: "memory");
- return __SHIFTOUT(__old, FCSR_FRM);
+ return __old;
}
static inline uint32_t
fcsr_frm_write(uint32_t __new)
{
uint32_t __old;
- __new = __SHIFTIN(__new, FCSR_FRM);
asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new) : "memory");
- return __SHIFTOUT(__old, FCSR_FRM);
+ return __old;
}
-
#define RISCVREG_READ_INLINE(regname) \
static inline uintptr_t \
csr_##regname##_read(void) \
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue May 14 15:16:51 UTC 2024 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: riscv: Fix reading and writing frm and fflags. The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and shifting needed -- __SHIFTIN/__SHIFTOUT is wrong. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Sun May 12 20:04:12 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: riscv fenv.h: Make sure FE_* exception constants have type int. This may not be formally required by the standard, but the values must be representable by int since that's the type that functions like fetestexcept and feclearexcept traffic in. And this is less work than changing all the printf %d users in tree. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Sun May 12 20:04:12 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: riscv fenv.h: Make sure FE_* exception constants have type int. This may not be formally required by the standard, but the values must be representable by int since that's the type that functions like fetestexcept and feclearexcept traffic in. And this is less work than changing all the printf %d users in tree. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/fenv.h diff -u src/sys/arch/riscv/include/fenv.h:1.4 src/sys/arch/riscv/include/fenv.h:1.5 --- src/sys/arch/riscv/include/fenv.h:1.4 Fri May 10 08:20:37 2024 +++ src/sys/arch/riscv/include/fenv.h Sun May 12 20:04:12 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: fenv.h,v 1.4 2024/05/10 08:20:37 skrll Exp $ */ +/* $NetBSD: fenv.h,v 1.5 2024/05/12 20:04:12 riastradh Exp $ */ /* * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 @@ -11,11 +11,11 @@ typedef int fenv_t; /* FPSCR */ typedef int fexcept_t; -#define FE_INEXACT __BIT(0) /* Result inexact */ -#define FE_UNDERFLOW __BIT(1) /* Result underflowed */ -#define FE_OVERFLOW __BIT(2) /* Result overflowed */ -#define FE_DIVBYZERO __BIT(3) /* divide-by-zero */ -#define FE_INVALID __BIT(4) /* Result invalid */ +#define FE_INEXACT ((int)__BIT(0)) /* Result inexact */ +#define FE_UNDERFLOW ((int)__BIT(1)) /* Result underflowed */ +#define FE_OVERFLOW ((int)__BIT(2)) /* Result overflowed */ +#define FE_DIVBYZERO ((int)__BIT(3)) /* divide-by-zero */ +#define FE_INVALID ((int)__BIT(4)) /* Result invalid */ #define FE_ALL_EXCEPT \ (FE_INEXACT | FE_UNDERFLOW | FE_OVERFLOW | FE_DIVBYZERO | FE_INVALID)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 10 08:20:37 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: Use __BIT and fix FE_INEXACT To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/fenv.h diff -u src/sys/arch/riscv/include/fenv.h:1.3 src/sys/arch/riscv/include/fenv.h:1.4 --- src/sys/arch/riscv/include/fenv.h:1.3 Sat Mar 14 16:12:16 2020 +++ src/sys/arch/riscv/include/fenv.h Fri May 10 08:20:37 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: fenv.h,v 1.3 2020/03/14 16:12:16 skrll Exp $ */ +/* $NetBSD: fenv.h,v 1.4 2024/05/10 08:20:37 skrll Exp $ */ /* * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 @@ -11,13 +11,14 @@ typedef int fenv_t; /* FPSCR */ typedef int fexcept_t; -#define FE_INEXACT 0x00 /* Result inexact */ -#define FE_UNDERFLOW 0x02 /* Result underflowed */ -#define FE_OVERFLOW 0x04 /* Result overflowed */ -#define FE_DIVBYZERO 0x08 /* divide-by-zero */ -#define FE_INVALID 0x10 /* Result invalid */ +#define FE_INEXACT __BIT(0) /* Result inexact */ +#define FE_UNDERFLOW __BIT(1) /* Result underflowed */ +#define FE_OVERFLOW __BIT(2) /* Result overflowed */ +#define FE_DIVBYZERO __BIT(3) /* divide-by-zero */ +#define FE_INVALID __BIT(4) /* Result invalid */ -#define FE_ALL_EXCEPT 0x1f +#define FE_ALL_EXCEPT \ +(FE_INEXACT | FE_UNDERFLOW | FE_OVERFLOW | FE_DIVBYZERO | FE_INVALID) #define FE_TONEAREST 0 /* round to nearest representable number */ #define FE_TOWARDZERO 1 /* round to zero (truncate) */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 10 08:20:37 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: Use __BIT and fix FE_INEXACT To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat May 4 12:42:09 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix the __greg_t typedef for riscv32
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/mcontext.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/mcontext.h
diff -u src/sys/arch/riscv/include/mcontext.h:1.7 src/sys/arch/riscv/include/mcontext.h:1.8
--- src/sys/arch/riscv/include/mcontext.h:1.7 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/mcontext.h Sat May 4 12:42:09 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.7 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: mcontext.h,v 1.8 2024/05/04 12:42:09 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -48,7 +48,7 @@ union __fpreg {
#define _BSD_FPREG_T_ union __fpreg
#endif
-typedef __uint64_t __greg_t;
+typedef long __greg_t;
typedef __greg_t __gregset_t[_NGREG];
typedef __uint32_t __greg32_t;
typedef __greg32_t __gregset32_t[_NGREG];
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 4 12:42:09 UTC 2024 Modified Files: src/sys/arch/riscv/include: mcontext.h Log Message: Fix the __greg_t typedef for riscv32 To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/mcontext.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri May 3 07:24:31 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu_subr.c
Log Message:
Small simplification. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu_subr.c
diff -u src/sys/arch/riscv/riscv/cpu_subr.c:1.4 src/sys/arch/riscv/riscv/cpu_subr.c:1.5
--- src/sys/arch/riscv/riscv/cpu_subr.c:1.4 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/cpu_subr.c Fri May 3 07:24:31 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.4 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.5 2024/05/03 07:24:31 skrll Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "opt_riscv_debug.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.4 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.5 2024/05/03 07:24:31 skrll Exp $");
#include
#include
@@ -212,7 +212,7 @@ cpu_ipi_wait(const char *s, const kcpuse
kcpuset_t *kcp = ci->ci_watchcpus;
/* some finite amount of time */
- for (u_long limit = curcpu()->ci_cpu_freq /* / 10 */; !done && limit--; ) {
+ for (u_long limit = ci->ci_cpu_freq /* / 10 */; !done && limit--; ) {
kcpuset_copy(kcp, watchset);
kcpuset_intersect(kcp, wanted);
done = kcpuset_match(kcp, wanted);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri May 3 07:24:31 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: cpu_subr.c Log Message: Small simplification. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu_subr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Fri May 3 07:11:14 UTC 2024
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
Use the _X_FOO register macros instead of magic numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/ptrace.h
diff -u src/sys/arch/riscv/include/ptrace.h:1.5 src/sys/arch/riscv/include/ptrace.h:1.6
--- src/sys/arch/riscv/include/ptrace.h:1.5 Thu Sep 14 03:25:31 2023
+++ src/sys/arch/riscv/include/ptrace.h Fri May 3 07:11:14 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.5 2023/09/14 03:25:31 rin Exp $ */
+/* $NetBSD: ptrace.h,v 1.6 2024/05/03 07:11:14 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -49,10 +49,10 @@
#include
#define PTRACE_REG_PC(r) (r)->r_pc
-#define PTRACE_REG_FP(r) (r)->r_reg[7]
+#define PTRACE_REG_FP(r) (r)->r_reg[_X_S0]
#define PTRACE_REG_SET_PC(r, v) (r)->r_pc = (v)
-#define PTRACE_REG_SP(r) (r)->r_reg[1]
-#define PTRACE_REG_INTRV(r) (r)->r_reg[9]
+#define PTRACE_REG_SP(r) (r)->r_reg[_X_SP]
+#define PTRACE_REG_INTRV(r) (r)->r_reg[_X_A0]
#define PTRACE_ILLEGAL_ASM __asm __volatile("c.unimp" ::: "memory")
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 3 07:11:14 UTC 2024 Modified Files: src/sys/arch/riscv/include: ptrace.h Log Message: Use the _X_FOO register macros instead of magic numbers. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/ptrace.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Thu May 2 18:18:17 UTC 2024
Modified Files:
src/sys/arch/riscv/include: locore.h
src/sys/arch/riscv/riscv: cpu_switch.S trap.c
Log Message:
risc-v: fix the error code when uvm_fault fails with cpu_set_onfault
Return the error from uvm_fault instead of EFAULT unconditionally when
faulting with cpu_set_onfault to fix several atf tests.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/locore.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu_switch.S
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/locore.h
diff -u src/sys/arch/riscv/include/locore.h:1.12 src/sys/arch/riscv/include/locore.h:1.13
--- src/sys/arch/riscv/include/locore.h:1.12 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/locore.h Thu May 2 18:18:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.12 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.13 2024/05/02 18:18:17 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -126,8 +126,8 @@ fpu_valid_p(lwp_t *l)
void __syncicache(const void *, size_t);
-int cpu_set_onfault(struct faultbuf *, register_t) __returns_twice;
-void cpu_jump_onfault(struct trapframe *, const struct faultbuf *);
+int cpu_set_onfault(struct faultbuf *) __returns_twice;
+void cpu_jump_onfault(struct trapframe *, const struct faultbuf *, int);
static inline void
cpu_unset_onfault(void)
Index: src/sys/arch/riscv/riscv/cpu_switch.S
diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.5 src/sys/arch/riscv/riscv/cpu_switch.S:1.6
--- src/sys/arch/riscv/riscv/cpu_switch.S:1.5 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/riscv/cpu_switch.S Thu May 2 18:18:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_switch.S,v 1.5 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: cpu_switch.S,v 1.6 2024/05/02 18:18:17 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -459,7 +459,7 @@ END(cpu_exception_handler)
/*
* int
- * cpu_set_onfault(struct faultbuf *fb, register_t retval)
+ * cpu_set_onfault(struct faultbuf *fb)
*/
ENTRY_NP(cpu_set_onfault)
REG_S ra, FB_RA(a0)
@@ -476,7 +476,6 @@ ENTRY_NP(cpu_set_onfault)
REG_S s10, FB_S10(a0)
REG_S s11, FB_S11(a0)
REG_S sp, FB_SP(a0)
- REG_S a1, FB_A0(a0)
PTR_S a0, L_MD_ONFAULT(tp)
li a0, 0
ret
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.25 src/sys/arch/riscv/riscv/trap.c:1.26
--- src/sys/arch/riscv/riscv/trap.c:1.25 Mon Apr 1 16:24:01 2024
+++ src/sys/arch/riscv/riscv/trap.c Thu May 2 18:18:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.26 2024/05/02 18:18:17 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.26 2024/05/02 18:18:17 skrll Exp $");
#include
@@ -90,10 +90,11 @@ static const char * const causenames[] =
[CAUSE_STORE_PAGE_FAULT] = "store page fault",
};
+
void
-cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb)
+cpu_jump_onfault(struct trapframe *tf, const struct faultbuf *fb, int error)
{
- tf->tf_a0 = fb->fb_reg[FB_A0];
+ tf->tf_a0 = error;
tf->tf_ra = fb->fb_reg[FB_RA];
tf->tf_s0 = fb->fb_reg[FB_S0];
tf->tf_s1 = fb->fb_reg[FB_S1];
@@ -131,7 +132,7 @@ copyin(const void *uaddr, void *kaddr, s
return EFAULT;
csr_sstatus_set(SR_SUM);
- if ((error = cpu_set_onfault(, EFAULT)) == 0) {
+ if ((error = cpu_set_onfault()) == 0) {
memcpy(kaddr, uaddr, len);
cpu_unset_onfault();
}
@@ -159,7 +160,7 @@ copyout(const void *kaddr, void *uaddr,
return EFAULT;
csr_sstatus_set(SR_SUM);
- if ((error = cpu_set_onfault(, EFAULT)) == 0) {
+ if ((error = cpu_set_onfault()) == 0) {
memcpy(uaddr, kaddr, len);
cpu_unset_onfault();
}
@@ -174,7 +175,7 @@ kcopy(const void *kfaddr, void *kdaddr,
struct faultbuf fb;
int error;
- if ((error = cpu_set_onfault(, EFAULT)) == 0) {
+ if ((error = cpu_set_onfault()) == 0) {
memcpy(kdaddr, kfaddr, len);
cpu_unset_onfault();
}
@@ -204,7 +205,7 @@ copyinstr(const void *uaddr, void *kaddr
return EFAULT;
csr_sstatus_set(SR_SUM);
- if ((error = cpu_set_onfault(, EFAULT)) == 0) {
+ if ((error = cpu_set_onfault()) == 0) {
retlen = strlcpy(kaddr, uaddr, len);
cpu_unset_onfault();
if (retlen >= len) {
@@ -240,7 +241,7 @@ copyoutstr(const void *kaddr, void *uadd
return EFAULT;
csr_sstatus_set(SR_SUM);
- if ((error = cpu_set_onfault(, EFAULT)) == 0) {
+ if ((error = cpu_set_onfault()) == 0) {
retlen = strlcpy(uaddr, kaddr, len);
cpu_unset_onfault();
if (retlen >= len) {
@@ -517,7 +518,7 @@
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Thu May 2 18:18:17 UTC 2024 Modified Files: src/sys/arch/riscv/include: locore.h src/sys/arch/riscv/riscv: cpu_switch.S trap.c Log Message: risc-v: fix the error code when uvm_fault fails with cpu_set_onfault Return the error from uvm_fault instead of EFAULT unconditionally when faulting with cpu_set_onfault to fix several atf tests. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/locore.h cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu_switch.S cvs rdiff -u -r1.25 -r1.26 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Wed Apr 17 06:11:56 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Re-enable HEARTBEAT To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Wed Apr 17 06:11:56 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Re-enable HEARTBEAT To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC.common diff -u src/sys/arch/riscv/conf/GENERIC.common:1.13 src/sys/arch/riscv/conf/GENERIC.common:1.14 --- src/sys/arch/riscv/conf/GENERIC.common:1.13 Sat Apr 6 13:42:46 2024 +++ src/sys/arch/riscv/conf/GENERIC.common Wed Apr 17 06:11:56 2024 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC.common,v 1.13 2024/04/06 13:42:46 skrll Exp $ +# $NetBSD: GENERIC.common,v 1.14 2024/04/17 06:11:56 skrll Exp $ # # GENERIC common RISC-V kernel config items shared between 32 and 64 # kernels @@ -17,8 +17,8 @@ options NTP # NTP phase/frequency lock options KTRACE # system call tracing via ktrace(1) # Heartbeat checks -#options HEARTBEAT -#options HEARTBEAT_MAX_PERIOD_DEFAULT=15 +options HEARTBEAT +options HEARTBEAT_MAX_PERIOD_DEFAULT=15 # Note: SysV IPC parameters could be changed dynamically, see sysctl(8). options SYSVMSG # System V-like message queues
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:59:13 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
riscv: Schedule next hardclock tick in the future, not the past.
If we have missed hardclock ticks, schedule up to one tick interval
in the future anyway; don't try to play hardclock catchup by
scheduling for when the next hardclock tick _should_ have been, in
the past, leading to ticking as fast as possible until we've caught
up. as fast as possible until we've caught up.
Playing hardclock catchup triggers heartbeat panics when continuing
from ddb, if you've been in ddb for >15sec. Other hardclock drivers
like x86 lapic don't play hardclock catchup either.
PR kern/57920
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/clock_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.7 src/sys/arch/riscv/riscv/clock_machdep.c:1.8
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.7 Thu Jan 18 07:41:50 2024
+++ src/sys/arch/riscv/riscv/clock_machdep.c Sun Apr 7 22:59:13 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $ */
+/* $NetBSD: clock_machdep.c,v 1.8 2024/04/07 22:59:13 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.8 2024/04/07 22:59:13 riastradh Exp $");
#include
#include
@@ -124,6 +124,10 @@ riscv_timer_intr(void *arg)
ci->ci_ev_timer.ev_count++;
ci->ci_lastintr_scheduled += timer_ticks_per_hz;
+ while (__predict_false(ci->ci_lastintr_scheduled < now)) {
+ ci->ci_lastintr_scheduled += timer_ticks_per_hz;
+ /* XXX count missed timer interrupts */
+ }
sbi_set_timer(ci->ci_lastintr_scheduled);
hardclock(cf);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Sun Apr 7 22:59:13 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: clock_machdep.c Log Message: riscv: Schedule next hardclock tick in the future, not the past. If we have missed hardclock ticks, schedule up to one tick interval in the future anyway; don't try to play hardclock catchup by scheduling for when the next hardclock tick _should_ have been, in the past, leading to ticking as fast as possible until we've caught up. as fast as possible until we've caught up. Playing hardclock catchup triggers heartbeat panics when continuing from ddb, if you've been in ddb for >15sec. Other hardclock drivers like x86 lapic don't play hardclock catchup either. PR kern/57920 To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/clock_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: riastradh
Date: Sun Apr 7 22:52:53 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: cpu.c
Log Message:
riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.
Otherwise this stays zero, which screws up cpu_ipi_wait.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu.c
diff -u src/sys/arch/riscv/riscv/cpu.c:1.5 src/sys/arch/riscv/riscv/cpu.c:1.6
--- src/sys/arch/riscv/riscv/cpu.c:1.5 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/cpu.c Sun Apr 7 22:52:53 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.5 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.6 2024/04/07 22:52:53 riastradh Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.5 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.6 2024/04/07 22:52:53 riastradh Exp $");
#include
@@ -184,6 +184,7 @@ cpu_attach(device_t dv, cpuid_t hartid)
ci = curcpu();
KASSERTMSG(ci == _info_store[0], "ci %p", ci);
ci->ci_cpuid = hartid;
+ ci->ci_cpu_freq = riscv_timer_frequency_get();
} else {
#ifdef MULTIPROCESSOR
if ((boothowto & RB_MD1) != 0) {
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Sun Apr 7 22:52:53 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: cpu.c Log Message: riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach. Otherwise this stays zero, which screws up cpu_ipi_wait. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/cpu.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Apr 6 13:42:46 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Attach qemufwcfg To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC.common diff -u src/sys/arch/riscv/conf/GENERIC.common:1.12 src/sys/arch/riscv/conf/GENERIC.common:1.13 --- src/sys/arch/riscv/conf/GENERIC.common:1.12 Tue Apr 2 22:56:51 2024 +++ src/sys/arch/riscv/conf/GENERIC.common Sat Apr 6 13:42:46 2024 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC.common,v 1.12 2024/04/02 22:56:51 charlotte Exp $ +# $NetBSD: GENERIC.common,v 1.13 2024/04/06 13:42:46 skrll Exp $ # # GENERIC common RISC-V kernel config items shared between 32 and 64 # kernels @@ -144,7 +144,7 @@ plic* at fdt? pass 2 com* at fdt? # UART # Firmware devices -#qemufwcfg* at fdt? # QEMU Firmware Configuration device +qemufwcfg* at fdt? # QEMU Firmware Configuration device # RTC devices gfrtc* at fdt? # Google Goldfish RTC
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Apr 6 13:42:46 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Attach qemufwcfg To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Apr 6 13:41:03 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: copy.S Log Message: Fix riscv32 build To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/copy.S diff -u src/sys/arch/riscv/riscv/copy.S:1.1 src/sys/arch/riscv/riscv/copy.S:1.2 --- src/sys/arch/riscv/riscv/copy.S:1.1 Sat Apr 6 10:08:54 2024 +++ src/sys/arch/riscv/riscv/copy.S Sat Apr 6 13:41:03 2024 @@ -118,6 +118,7 @@ ENTRY(_ucas_32) END(_ucas_32) +#ifdef _LP64 /* * int _ucas_64(volatile uint64_t *ptr, uint64_t old, * uint64_t new, uint64_t *ret) @@ -156,3 +157,4 @@ ENTRY(_ucas_64) li a0, EFAULT ret END(_ucas_64) +#endif
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Apr 6 13:41:03 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: copy.S Log Message: Fix riscv32 build To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/copy.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat Apr 6 10:08:54 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: files.riscv
src/sys/arch/riscv/include: types.h
src/sys/arch/riscv/riscv: genassym.cf
Added Files:
src/sys/arch/riscv/riscv: copy.S
Log Message:
Provide and use _ucas_{32,64} implementations
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/types.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/riscv/copy.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/genassym.cf
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.14 src/sys/arch/riscv/conf/files.riscv:1.15
--- src/sys/arch/riscv/conf/files.riscv:1.14 Sun Sep 3 08:48:19 2023
+++ src/sys/arch/riscv/conf/files.riscv Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.14 2023/09/03 08:48:19 skrll Exp $
+# $NetBSD: files.riscv,v 1.15 2024/04/06 10:08:54 skrll Exp $
#
maxpartitions 16
@@ -25,6 +25,7 @@ file arch/riscv/riscv/bus_space_generic.
file arch/riscv/riscv/bus_space_notimpl.S
file arch/riscv/riscv/bus_stubs.c
file arch/riscv/riscv/clock_machdep.c
+file arch/riscv/riscv/copy.S
file arch/riscv/riscv/core_machdep.c coredump
file arch/riscv/riscv/cpu.c cpu
file arch/riscv/riscv/cpu_subr.c
Index: src/sys/arch/riscv/include/types.h
diff -u src/sys/arch/riscv/include/types.h:1.16 src/sys/arch/riscv/include/types.h:1.17
--- src/sys/arch/riscv/include/types.h:1.16 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/types.h Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: types.h,v 1.16 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: types.h,v 1.17 2024/04/06 10:08:54 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -98,6 +98,7 @@ typedef __int32_t __register_t;
#define __HAVE_NEW_STYLE_BUS_H
#define __HAVE_SYSCALL_INTERN
#define __HAVE_TLS_VARIANT_I
+#define __HAVE_UCAS_FULL
/* XXX temporary */
#define __HAVE_UNLOCKED_PMAP
#define __HAVE___LWP_GETPRIVATE_FAST
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.15 src/sys/arch/riscv/riscv/genassym.cf:1.16
--- src/sys/arch/riscv/riscv/genassym.cf:1.15 Mon Jun 12 19:04:14 2023
+++ src/sys/arch/riscv/riscv/genassym.cf Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.15 2023/06/12 19:04:14 skrll Exp $
+# $NetBSD: genassym.cf,v 1.16 2024/04/06 10:08:54 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -148,6 +148,7 @@ define CI_MTX_COUNT offsetof(struct cpu_
define CI_MTX_OLDSPL offsetof(struct cpu_info, ci_mtx_oldspl)
define CI_SOFTINTS offsetof(struct cpu_info, ci_softints)
+define FB_LEN sizeof(struct faultbuf)
define FB_A0 offsetof(struct faultbuf, fb_reg[FB_A0])
define FB_RA offsetof(struct faultbuf, fb_reg[FB_RA])
define FB_S0 offsetof(struct faultbuf, fb_reg[FB_S0])
@@ -165,6 +166,8 @@ define FB_S11 offsetof(struct faultbuf,
define FB_SP offsetof(struct faultbuf, fb_reg[FB_SP])
define FB_SR offsetof(struct faultbuf, fb_sr)
+define EFAULT EFAULT
+
define PAGE_SIZE PAGE_SIZE
define PAGE_MASK PAGE_MASK
define PAGE_SHIFT PAGE_SHIFT
@@ -192,6 +195,7 @@ define RW_WRITE_LOCKED RW_WRITE_LOCKED
define RW_READ_INCR RW_READ_INCR
define RW_READER RW_READER
+define VM_MAXUSER_ADDRESS VM_MAXUSER_ADDRESS
define VM_MIN_KERNEL_ADDRESS VM_MIN_KERNEL_ADDRESS
define VM_MAX_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS
define VM_KERNEL_BASE VM_KERNEL_BASE
Added files:
Index: src/sys/arch/riscv/riscv/copy.S
diff -u /dev/null src/sys/arch/riscv/riscv/copy.S:1.1
--- /dev/null Sat Apr 6 10:08:54 2024
+++ src/sys/arch/riscv/riscv/copy.S Sat Apr 6 10:08:54 2024
@@ -0,0 +1,158 @@
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat Apr 6 10:08:54 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: files.riscv
src/sys/arch/riscv/include: types.h
src/sys/arch/riscv/riscv: genassym.cf
Added Files:
src/sys/arch/riscv/riscv: copy.S
Log Message:
Provide and use _ucas_{32,64} implementations
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/types.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/riscv/copy.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/genassym.cf
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
/usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in
__futex(_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Apr 1 16:24:01 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Return the correct error from {fetch,store}_user_data and fix
futex_wake_op_op: [0.273033s] Failed:
/usr/src/tests/lib/libc/sys/t_futex_ops.c:942: Expected errno 14, got 1, in
__futex(_word, FUTEX_WAKE_OP | flags, 0, NULL, NULL, 0, op) == -1
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.24 src/sys/arch/riscv/riscv/trap.c:1.25
--- src/sys/arch/riscv/riscv/trap.c:1.24 Thu Sep 7 12:48:49 2023
+++ src/sys/arch/riscv/riscv/trap.c Mon Apr 1 16:24:01 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.25 2024/04/01 16:24:01 skrll Exp $");
#include
@@ -672,7 +672,7 @@ fetch_user_data(const void *uaddr, void
if (__predict_false(uva > VM_MAXUSER_ADDRESS - size))
return EFAULT;
- if ((error = cpu_set_onfault(, 1)) != 0)
+ if ((error = cpu_set_onfault(, EFAULT)) != 0)
return error;
csr_sstatus_set(SR_SUM);
@@ -737,7 +737,7 @@ store_user_data(void *uaddr, const void
if (__predict_false(uva > VM_MAXUSER_ADDRESS - size))
return EFAULT;
- if ((error = cpu_set_onfault(, 1)) != 0)
+ if ((error = cpu_set_onfault(, EFAULT)) != 0)
return error;
csr_sstatus_set(SR_SUM);
CVS commit: src/sys/arch/riscv/dev
Module Name:src Committed By: skrll Date: Sun Mar 24 08:34:20 UTC 2024 Modified Files: src/sys/arch/riscv/dev: plic.c plic_fdt.c Log Message: Pretty print plic attachment To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/dev/plic.c cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/dev/plic_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/dev
Module Name:src
Committed By: skrll
Date: Sun Mar 24 08:34:20 UTC 2024
Modified Files:
src/sys/arch/riscv/dev: plic.c plic_fdt.c
Log Message:
Pretty print plic attachment
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/dev/plic.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/dev/plic_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/dev/plic.c
diff -u src/sys/arch/riscv/dev/plic.c:1.4 src/sys/arch/riscv/dev/plic.c:1.5
--- src/sys/arch/riscv/dev/plic.c:1.4 Mon Dec 25 13:01:59 2023
+++ src/sys/arch/riscv/dev/plic.c Sun Mar 24 08:34:20 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: plic.c,v 1.4 2023/12/25 13:01:59 skrll Exp $ */
+/* $NetBSD: plic.c,v 1.5 2024/03/24 08:34:20 skrll Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.4 2023/12/25 13:01:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.5 2024/03/24 08:34:20 skrll Exp $");
#include
@@ -204,7 +204,7 @@ plic_attach_common(struct plic_softc *sc
}
aprint_naive("\n");
- aprint_normal("RISC-V PLIC (%u IRQs)\n", sc->sc_ndev);
+ aprint_normal(": RISC-V PLIC (%u IRQs)\n", sc->sc_ndev);
plic_sc = sc;
Index: src/sys/arch/riscv/dev/plic_fdt.c
diff -u src/sys/arch/riscv/dev/plic_fdt.c:1.5 src/sys/arch/riscv/dev/plic_fdt.c:1.6
--- src/sys/arch/riscv/dev/plic_fdt.c:1.5 Fri Feb 9 18:39:53 2024
+++ src/sys/arch/riscv/dev/plic_fdt.c Sun Mar 24 08:34:20 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: plic_fdt.c,v 1.5 2024/02/09 18:39:53 andvar Exp $ */
+/* $NetBSD: plic_fdt.c,v 1.6 2024/03/24 08:34:20 skrll Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.5 2024/02/09 18:39:53 andvar Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.6 2024/03/24 08:34:20 skrll Exp $");
#include
@@ -240,7 +240,7 @@ plic_fdt_attach(device_t parent, device_
context++;
}
- aprint_verbose_dev(self, "");
+ aprint_verbose_dev(self, "attaching");
error = plic_attach_common(sc, addr, size);
if (error != 0) {
return;
CVS commit: src/sys/arch/riscv/conf
Module Name:src
Committed By: skrll
Date: Sun Feb 25 14:27:41 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv
Log Message:
Warn about building a kernel with the wrong toolchain.
Idea from mrg@
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/Makefile.riscv
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.10 src/sys/arch/riscv/conf/Makefile.riscv:1.11
--- src/sys/arch/riscv/conf/Makefile.riscv:1.10 Wed Jul 26 03:41:57 2023
+++ src/sys/arch/riscv/conf/Makefile.riscv Sun Feb 25 14:27:41 2024
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.riscv,v 1.10 2023/07/26 03:41:57 rin Exp $
+# $NetBSD: Makefile.riscv,v 1.11 2024/02/25 14:27:41 skrll Exp $
# Makefile for NetBSD
#
@@ -21,6 +21,18 @@ USETOOLS?= no
NEED_OWN_INSTALL_TARGET?=no
.include
+
+.if !defined(LP64) && ${MACHINE_ARCH} == "riscv64"
+. info (Building GENERIC instead of GENERIC64?)
+. error Don't build 32-bit kernel with 64-bit toolchain
+.endif
+
+.if defined(LP64) && ${MACHINE_ARCH} == "riscv32"
+. info (Building GENERIC64 instead of GENERIC?)
+. error Don't build 64-bit kernel with 32-bit toolchain
+.endif
+
+
##
## (1) port identification
##
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sun Feb 25 14:27:41 UTC 2024 Modified Files: src/sys/arch/riscv/conf: Makefile.riscv Log Message: Warn about building a kernel with the wrong toolchain. Idea from mrg@ To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/Makefile.riscv Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sun Feb 11 09:07:49 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Turn off HEARTBEAT To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sun Feb 11 09:07:49 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Turn off HEARTBEAT To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC.common diff -u src/sys/arch/riscv/conf/GENERIC.common:1.10 src/sys/arch/riscv/conf/GENERIC.common:1.11 --- src/sys/arch/riscv/conf/GENERIC.common:1.10 Mon Jan 29 18:27:14 2024 +++ src/sys/arch/riscv/conf/GENERIC.common Sun Feb 11 09:07:49 2024 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC.common,v 1.10 2024/01/29 18:27:14 christos Exp $ +# $NetBSD: GENERIC.common,v 1.11 2024/02/11 09:07:49 skrll Exp $ # # GENERIC common RISC-V kernel config items shared between 32 and 64 # kernels @@ -17,8 +17,8 @@ options NTP # NTP phase/frequency lock options KTRACE # system call tracing via ktrace(1) # Heartbeat checks -options HEARTBEAT -options HEARTBEAT_MAX_PERIOD_DEFAULT=15 +#options HEARTBEAT +#options HEARTBEAT_MAX_PERIOD_DEFAULT=15 # Note: SysV IPC parameters could be changed dynamically, see sysctl(8). options SYSVMSG # System V-like message queues
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Fri Feb 9 08:51:49 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Attach ld at sdmmc The SD card on my Beagle-V now works. Thanks jmcneill! To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.8 src/sys/arch/riscv/conf/GENERIC64:1.9 --- src/sys/arch/riscv/conf/GENERIC64:1.8 Wed Feb 7 17:17:59 2024 +++ src/sys/arch/riscv/conf/GENERIC64 Fri Feb 9 08:51:49 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.8 2024/02/07 17:17:59 skrll Exp $ +# $NetBSD: GENERIC64,v 1.9 2024/02/09 08:51:49 skrll Exp $ # # GENERIC machine description file # @@ -58,6 +58,11 @@ jh7100pinctrl* at fdt? pass 2 # StarFi # SDMMC dwcmmc* at fdt? # DesignWare SD/MMC sdmmc* at sdmmcbus? +ld0 at sdmmc0 +ld1 at sdmmc1 +ld2 at sdmmc2 +ld3 at sdmmc3 +ld* at sdmmc? bwfm* at sdmmc? # Broadcom BCM43xxx WiFi Interface # USB
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Fri Feb 9 08:51:49 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Attach ld at sdmmc The SD card on my Beagle-V now works. Thanks jmcneill! To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Feb 8 18:25:58 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: bus_dma.c Log Message: Define _RISCV_NEED_BUS_DMA_BOUNCE. Pointed out as being needed by jmcneill. Thanks! To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_dma.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Feb 8 18:25:58 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: bus_dma.c Log Message: Define _RISCV_NEED_BUS_DMA_BOUNCE. Pointed out as being needed by jmcneill. Thanks! To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/bus_dma.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/bus_dma.c diff -u src/sys/arch/riscv/riscv/bus_dma.c:1.1 src/sys/arch/riscv/riscv/bus_dma.c:1.2 --- src/sys/arch/riscv/riscv/bus_dma.c:1.1 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/riscv/bus_dma.c Thu Feb 8 18:25:58 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: bus_dma.c,v 1.1 2023/05/07 12:41:48 skrll Exp $ */ +/* $NetBSD: bus_dma.c,v 1.2 2024/02/08 18:25:58 skrll Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc. @@ -31,9 +31,10 @@ */ #define _RISCV_BUS_DMA_PRIVATE +#define _RISCV_NEED_BUS_DMA_BOUNCE #include -__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.1 2023/05/07 12:41:48 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.2 2024/02/08 18:25:58 skrll Exp $"); #include
CVS commit: src/sys/arch/riscv/starfive
Module Name:src
Committed By: skrll
Date: Thu Feb 8 07:13:10 UTC 2024
Modified Files:
src/sys/arch/riscv/starfive: jh7100_pinctrl.c
Log Message:
Some fixes from Roland Illig
- fix a locking bug
- '\n' at the end of error messages
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_pinctrl.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/starfive/jh7100_pinctrl.c
diff -u src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.1 src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.2
--- src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.1 Wed Feb 7 17:17:59 2024
+++ src/sys/arch/riscv/starfive/jh7100_pinctrl.c Thu Feb 8 07:13:10 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh7100_pinctrl.c,v 1.1 2024/02/07 17:17:59 skrll Exp $ */
+/* $NetBSD: jh7100_pinctrl.c,v 1.2 2024/02/08 07:13:10 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: jh7100_pinctrl.c,v 1.1 2024/02/07 17:17:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh7100_pinctrl.c,v 1.2 2024/02/08 07:13:10 skrll Exp $");
#include
@@ -222,7 +222,7 @@ jh7100_pinctrl_pin_properties(struct jh7
case -1:
break;
default:
- aprint_error_dev(sc->sc_dev, "invalid slew rate");
+ aprint_error_dev(sc->sc_dev, "invalid slew rate\n");
}
if (of_hasprop(phandle, "starfive,strong-pull-up")) {
@@ -322,7 +322,6 @@ jh7100_pinctrl_set_config_group(struct j
jh7100_padctl_rmw(sc, sc->sc_padctl_gpio + pin_no,
val, mask);
}
-
}
}
@@ -413,7 +412,7 @@ jh7100_pinctrl_gpio_write(device_t dev,
mutex_enter(>sc_lock);
GPIOWR4(sc, GPO_DOUT_CFG(pin_no), val);
- mutex_enter(>sc_lock);
+ mutex_exit(>sc_lock);
}
static struct fdtbus_gpio_controller_func jh7100_pinctrl_gpio_funcs = {
@@ -446,7 +445,7 @@ jh7100_pinctrl_attach(device_t parent, d
sc->sc_bst = faa->faa_bst;
if (!of_hasprop(phandle, "gpio-controller")) {
- aprint_error(": no gpio controller");
+ aprint_error(": no gpio controller\n");
return;
}
@@ -494,7 +493,7 @@ jh7100_pinctrl_attach(device_t parent, d
sc->sc_padctl_gpio = PAD_FUNC_SHARE(0);
break;
default:
- aprint_error_dev(sc->sc_dev, "invalid signal group %u", sel);
+ aprint_error_dev(sc->sc_dev, "invalid signal group %u\n", sel);
return;
}
CVS commit: src/sys/arch/riscv/starfive
Module Name:src Committed By: skrll Date: Thu Feb 8 07:13:10 UTC 2024 Modified Files: src/sys/arch/riscv/starfive: jh7100_pinctrl.c Log Message: Some fixes from Roland Illig - fix a locking bug - '\n' at the end of error messages To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_pinctrl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Wed Feb 7 17:17:59 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: GENERIC64
src/sys/arch/riscv/starfive: files.starfive
Added Files:
src/sys/arch/riscv/starfive: jh7100_pinctrl.c
Log Message:
risc-v: add a driver the JH7100 pin controller
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/GENERIC64
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/starfive/files.starfive
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/starfive/jh7100_pinctrl.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/GENERIC64
diff -u src/sys/arch/riscv/conf/GENERIC64:1.7 src/sys/arch/riscv/conf/GENERIC64:1.8
--- src/sys/arch/riscv/conf/GENERIC64:1.7 Wed Feb 7 17:03:35 2024
+++ src/sys/arch/riscv/conf/GENERIC64 Wed Feb 7 17:17:59 2024
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC64,v 1.7 2024/02/07 17:03:35 skrll Exp $
+# $NetBSD: GENERIC64,v 1.8 2024/02/07 17:17:59 skrll Exp $
#
# GENERIC machine description file
#
@@ -52,6 +52,9 @@ ccache* at fdt? # SiFive FU[57]40 L2
# Clock controller
jh7100clkc* at fdt? pass 2 # StarFive JH7100 clock controller
+# Pin control
+jh7100pinctrl* at fdt? pass 2 # StarFive JH7100 pinctrl driver
+
# SDMMC
dwcmmc* at fdt? # DesignWare SD/MMC
sdmmc* at sdmmcbus?
Index: src/sys/arch/riscv/starfive/files.starfive
diff -u src/sys/arch/riscv/starfive/files.starfive:1.2 src/sys/arch/riscv/starfive/files.starfive:1.3
--- src/sys/arch/riscv/starfive/files.starfive:1.2 Thu Jan 18 07:48:57 2024
+++ src/sys/arch/riscv/starfive/files.starfive Wed Feb 7 17:17:59 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.starfive,v 1.2 2024/01/18 07:48:57 skrll Exp $
+# $NetBSD: files.starfive,v 1.3 2024/02/07 17:17:59 skrll Exp $
#
# Configuration info for StarFive SoCs
#
@@ -12,3 +12,8 @@ file arch/riscv/starfive/jh7100_clkc.c
device jh71x0usb
attach jh71x0usb at fdt with jh71x0_usb
file arch/riscv/starfive/jh71x0_usb.c jh71x0_usb
+
+# JH7100 Pin control
+device jh7100pinctrl
+attach jh7100pinctrl at fdt with jh7100_pinctrl
+file arch/riscv/starfive/jh7100_pinctrl.c jh7100_pinctrl
Added files:
Index: src/sys/arch/riscv/starfive/jh7100_pinctrl.c
diff -u /dev/null src/sys/arch/riscv/starfive/jh7100_pinctrl.c:1.1
--- /dev/null Wed Feb 7 17:17:59 2024
+++ src/sys/arch/riscv/starfive/jh7100_pinctrl.c Wed Feb 7 17:17:59 2024
@@ -0,0 +1,513 @@
+/* $NetBSD: jh7100_pinctrl.c,v 1.1 2024/02/07 17:17:59 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2023 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+__KERNEL_RCSID(0, "$NetBSD: jh7100_pinctrl.c,v 1.1 2024/02/07 17:17:59 skrll Exp $");
+
+#include
+
+#include
+
+#include
+
+struct jh7100_pinctrl_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_gpio_bsh;
+ bus_space_handle_t sc_padctl_bsh;
+ int sc_phandle;
+
+ kmutex_t sc_lock;
+ u_int sc_padctl_gpio;
+};
+
+struct jh7100_pinctrl_gpio_pin {
+ struct jh7100_pinctrl_softc *pin_sc;
+ u_int pin_no;
+ bool pin_actlo;
+};
+
+#define GPIORD4(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg))
+#define GPIOWR4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg), (val))
+
+#define GPIO_DIN(pin) (0x0048 + (((pin) / 32) * 4))
+
+#define GPO_DOUT_CFG(pin) (0x0050 + ((pin) * 8))
+#define GPO_DOUT_REVERSE __BIT(31)
+#define GPO_DOUT_MASK __BITS(30, 0)
+#define
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Wed Feb 7 17:17:59 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 src/sys/arch/riscv/starfive: files.starfive Added Files: src/sys/arch/riscv/starfive: jh7100_pinctrl.c Log Message: risc-v: add a driver the JH7100 pin controller To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/GENERIC64 cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/starfive/files.starfive cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/starfive/jh7100_pinctrl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Wed Feb 7 17:03:35 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Use consistently To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.6 src/sys/arch/riscv/conf/GENERIC64:1.7 --- src/sys/arch/riscv/conf/GENERIC64:1.6 Sat Jan 20 08:05:37 2024 +++ src/sys/arch/riscv/conf/GENERIC64 Wed Feb 7 17:03:35 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.6 2024/01/20 08:05:37 skrll Exp $ +# $NetBSD: GENERIC64,v 1.7 2024/02/07 17:03:35 skrll Exp $ # # GENERIC machine description file # @@ -54,8 +54,8 @@ jh7100clkc* at fdt? pass 2 # StarFive # SDMMC dwcmmc* at fdt? # DesignWare SD/MMC -sdmmc* at sdmmcbus? -bwfm* at sdmmc? # Broadcom BCM43xxx WiFi Interface +sdmmc* at sdmmcbus? +bwfm* at sdmmc? # Broadcom BCM43xxx WiFi Interface # USB jh71x0usb* at fdt? # StarFive JH71x0 usb @@ -64,7 +64,7 @@ jh71x0usb* at fdt? # StarFive JH71x0 xhci* at fdt? # XHCI usb* at usbus? include "dev/usb/usbdevices.config" -midi* at midibus? +midi* at midibus? # Pull in optional local configuration - always at end cinclude "arch/riscv/conf/GENERIC64.local"
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Wed Feb 7 17:03:35 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Use consistently To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/fdt
Module Name:src
Committed By: skrll
Date: Sun Jan 21 08:48:21 UTC 2024
Modified Files:
src/sys/arch/riscv/fdt: intc_fdt.c
Log Message:
Make this compile without MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/fdt/intc_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/fdt/intc_fdt.c
diff -u src/sys/arch/riscv/fdt/intc_fdt.c:1.5 src/sys/arch/riscv/fdt/intc_fdt.c:1.6
--- src/sys/arch/riscv/fdt/intc_fdt.c:1.5 Sun Jan 21 08:41:00 2024
+++ src/sys/arch/riscv/fdt/intc_fdt.c Sun Jan 21 08:48:21 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: intc_fdt.c,v 1.5 2024/01/21 08:41:00 skrll Exp $ */
+/* $NetBSD: intc_fdt.c,v 1.6 2024/01/21 08:48:21 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.5 2024/01/21 08:41:00 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.6 2024/01/21 08:48:21 skrll Exp $");
#include
@@ -57,7 +57,6 @@ static const struct device_compatible_en
struct intc_irqhandler;
struct intc_irq;
-struct intc_softc;
typedef int (*intcih_t)(void *);
@@ -121,6 +120,20 @@ static const char * const intc_sources[I
"(reserved)"
};
+#ifndef MULTIPROCESSOR
+struct intc_fdt_softc *intc_sc;
+#endif
+
+
+static inline struct intc_fdt_softc *
+intc_getsc(struct cpu_info *ci)
+{
+#ifdef MULTIPROCESSOR
+ return ci->ci_intcsoftc;
+#else
+ return intc_sc;
+#endif
+}
static void *
intc_intr_establish(struct intc_fdt_softc *sc, u_int source, u_int ipl,
@@ -246,7 +259,7 @@ intc_intr_handler(struct trapframe *tf,
KASSERT(CAUSE_INTERRUPT_P(cause));
- struct intc_fdt_softc * const sc = ci->ci_intcsoftc;
+ struct intc_fdt_softc * const sc = intc_getsc(ci);
ci->ci_intr_depth++;
ci->ci_data.cpu_nintr++;
@@ -334,13 +347,15 @@ intc_attach(device_t parent, device_t se
sc->sc_dev = self;
sc->sc_ci = ci;
sc->sc_hartid = ci->ci_cpuid;
- ci->ci_intcsoftc = sc;
intc_intr_establish(sc, IRQ_SUPERVISOR_TIMER, IPL_SCHED, IST_MPSAFE,
riscv_timer_intr, NULL, "clock");
#ifdef MULTIPROCESSOR
+ ci->ci_intcsoftc = sc;
intc_intr_establish(sc, IRQ_SUPERVISOR_SOFTWARE, IPL_HIGH, IST_MPSAFE,
riscv_ipi_intr, NULL, "ipi");
+#else
+ intc_sc = sc;
#endif
}
CVS commit: src/sys/arch/riscv/fdt
Module Name:src Committed By: skrll Date: Sun Jan 21 08:48:21 UTC 2024 Modified Files: src/sys/arch/riscv/fdt: intc_fdt.c Log Message: Make this compile without MULTIPROCESSOR To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/fdt/intc_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/fdt
Module Name:src Committed By: skrll Date: Sun Jan 21 08:41:00 UTC 2024 Modified Files: src/sys/arch/riscv/fdt: intc_fdt.c Log Message: Remove an empty line To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/fdt/intc_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/fdt/intc_fdt.c diff -u src/sys/arch/riscv/fdt/intc_fdt.c:1.4 src/sys/arch/riscv/fdt/intc_fdt.c:1.5 --- src/sys/arch/riscv/fdt/intc_fdt.c:1.4 Sun Jan 21 08:39:50 2024 +++ src/sys/arch/riscv/fdt/intc_fdt.c Sun Jan 21 08:41:00 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: intc_fdt.c,v 1.4 2024/01/21 08:39:50 skrll Exp $ */ +/* $NetBSD: intc_fdt.c,v 1.5 2024/01/21 08:41:00 skrll Exp $ */ /*- * Copyright (c) 2023 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #include "opt_multiprocessor.h" #include -__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.4 2024/01/21 08:39:50 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.5 2024/01/21 08:41:00 skrll Exp $"); #include @@ -208,7 +208,6 @@ intc_fdt_disestablish(device_t dev, void #if 0 struct intc_fdt_softc * const sc = device_private(dev); #endif - } static bool
CVS commit: src/sys/arch/riscv/fdt
Module Name:src Committed By: skrll Date: Sun Jan 21 08:41:00 UTC 2024 Modified Files: src/sys/arch/riscv/fdt: intc_fdt.c Log Message: Remove an empty line To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/fdt/intc_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/fdt
Module Name:src Committed By: skrll Date: Sun Jan 21 08:39:50 UTC 2024 Modified Files: src/sys/arch/riscv/fdt: intc_fdt.c Log Message: spaces -> tab To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/fdt/intc_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/fdt
Module Name:src
Committed By: skrll
Date: Sun Jan 21 08:39:50 UTC 2024
Modified Files:
src/sys/arch/riscv/fdt: intc_fdt.c
Log Message:
spaces -> tab
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/fdt/intc_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/fdt/intc_fdt.c
diff -u src/sys/arch/riscv/fdt/intc_fdt.c:1.3 src/sys/arch/riscv/fdt/intc_fdt.c:1.4
--- src/sys/arch/riscv/fdt/intc_fdt.c:1.3 Mon Dec 25 13:21:30 2023
+++ src/sys/arch/riscv/fdt/intc_fdt.c Sun Jan 21 08:39:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: intc_fdt.c,v 1.3 2023/12/25 13:21:30 skrll Exp $ */
+/* $NetBSD: intc_fdt.c,v 1.4 2024/01/21 08:39:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.3 2023/12/25 13:21:30 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.4 2024/01/21 08:39:50 skrll Exp $");
#include
@@ -313,7 +313,7 @@ intc_attach(device_t parent, device_t se
const int phandle = faa->faa_phandle;
int error = fdtbus_register_interrupt_controller(self, phandle,
-_fdt_funcs);
+ _fdt_funcs);
if (error) {
aprint_error(": couldn't register with fdtbus: %d\n", error);
return;
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 20 08:05:37 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Add bwfm* at sdmmc? for the Broadcom BCM43xxx WiFi Interface To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.5 src/sys/arch/riscv/conf/GENERIC64:1.6 --- src/sys/arch/riscv/conf/GENERIC64:1.5 Sat Jan 20 08:04:35 2024 +++ src/sys/arch/riscv/conf/GENERIC64 Sat Jan 20 08:05:37 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.5 2024/01/20 08:04:35 skrll Exp $ +# $NetBSD: GENERIC64,v 1.6 2024/01/20 08:05:37 skrll Exp $ # # GENERIC machine description file # @@ -55,6 +55,7 @@ jh7100clkc* at fdt? pass 2 # StarFive # SDMMC dwcmmc* at fdt? # DesignWare SD/MMC sdmmc* at sdmmcbus? +bwfm* at sdmmc? # Broadcom BCM43xxx WiFi Interface # USB jh71x0usb* at fdt? # StarFive JH71x0 usb
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 20 08:05:37 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Add bwfm* at sdmmc? for the Broadcom BCM43xxx WiFi Interface To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 20 08:04:35 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Add DesignWare SD/MMC attachment. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.4 src/sys/arch/riscv/conf/GENERIC64:1.5 --- src/sys/arch/riscv/conf/GENERIC64:1.4 Thu Jan 18 07:48:56 2024 +++ src/sys/arch/riscv/conf/GENERIC64 Sat Jan 20 08:04:35 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.4 2024/01/18 07:48:56 skrll Exp $ +# $NetBSD: GENERIC64,v 1.5 2024/01/20 08:04:35 skrll Exp $ # # GENERIC machine description file # @@ -52,6 +52,10 @@ ccache* at fdt? # SiFive FU[57]40 L2 # Clock controller jh7100clkc* at fdt? pass 2 # StarFive JH7100 clock controller +# SDMMC +dwcmmc* at fdt? # DesignWare SD/MMC +sdmmc* at sdmmcbus? + # USB jh71x0usb* at fdt? # StarFive JH71x0 usb
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 20 08:04:35 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 Log Message: Add DesignWare SD/MMC attachment. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/conf/GENERIC64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri Jan 19 09:09:39 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: autoconf.c Log Message: Use fdt_cpu_rootconf To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri Jan 19 09:09:39 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Use fdt_cpu_rootconf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/autoconf.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/autoconf.c
diff -u src/sys/arch/riscv/riscv/autoconf.c:1.5 src/sys/arch/riscv/riscv/autoconf.c:1.6
--- src/sys/arch/riscv/riscv/autoconf.c:1.5 Mon Jul 10 07:04:20 2023
+++ src/sys/arch/riscv/riscv/autoconf.c Fri Jan 19 09:09:39 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $ */
+/* $NetBSD: autoconf.c,v 1.6 2024/01/19 09:09:39 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: autoconf.c,v 1.5 2023/07/10 07:04:20 rin Exp $");
+__RCSID("$NetBSD: autoconf.c,v 1.6 2024/01/19 09:09:39 skrll Exp $");
#include
@@ -57,10 +57,26 @@ cpu_configure(void)
spl0();
}
+/*
+ * Set up the root device from the boot args.
+ *
+ * cpu_bootconf() is called before RAIDframe root detection,
+ * and cpu_rootconf() is called after.
+ */
void
-cpu_rootconf(void)
+cpu_bootconf(void)
{
+#ifndef MEMORY_DISK_IS_ROOT
+ fdt_cpu_rootconf();
+#endif
+}
+void
+cpu_rootconf(void)
+{
+ cpu_bootconf();
+ aprint_normal("boot device: %s\n",
+ booted_device != NULL ? device_xname(booted_device) : "");
rootconf();
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Thu Jan 18 07:41:50 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c
Log Message:
Provide a working delay(9)
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/clock_machdep.c
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.6 src/sys/arch/riscv/riscv/clock_machdep.c:1.7
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.6 Wed Jul 26 06:13:44 2023
+++ src/sys/arch/riscv/riscv/clock_machdep.c Thu Jan 18 07:41:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $ */
+/* $NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.6 2023/07/26 06:13:44 skrll Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.7 2024/01/18 07:41:50 skrll Exp $");
#include
#include
@@ -47,6 +47,7 @@ static void (*_riscv_timer_init)(void) =
static uint32_t timer_frequency;
static uint32_t timer_ticks_per_hz;
+static uint32_t timer_ticks_per_usec;
static u_int
timer_get_timecount(struct timecounter *tc)
@@ -67,6 +68,7 @@ riscv_timer_frequency_set(uint32_t freq)
{
timer_frequency = freq;
timer_ticks_per_hz = freq / hz;
+ timer_ticks_per_usec = freq / 100;
}
uint32_t
@@ -143,3 +145,14 @@ void
setstatclockrate(int newhz)
{
}
+
+void
+delay(unsigned long us)
+{
+const uint64_t ticks = (uint64_t)us * timer_ticks_per_usec;
+const uint64_t finish = csr_time_read() + ticks;
+
+while (csr_time_read() < finish) {
+/* spin, baby spin */
+}
+}
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.35 src/sys/arch/riscv/riscv/riscv_machdep.c:1.36
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.35 Fri Dec 22 08:41:59 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Jan 18 07:41:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.36 2024/01/18 07:41:50 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.36 2024/01/18 07:41:50 skrll Exp $");
#include
@@ -136,18 +136,6 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
CTL_MACHDEP, CTL_EOL);
}
-void
-delay(unsigned long us)
-{
- const uint32_t cycles_per_us = curcpu()->ci_data.cpu_cc_freq / 100;
- const uint64_t cycles = (uint64_t)us * cycles_per_us;
- const uint64_t finish = csr_cycle_read() + cycles;
-
- while (csr_cycle_read() < finish) {
- /* spin, baby spin */
- }
-}
-
#ifdef MODULAR
/*
* Push any modules loaded by the boot loader.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Jan 18 07:41:50 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: clock_machdep.c riscv_machdep.c Log Message: Provide a working delay(9) To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/clock_machdep.c cvs rdiff -u -r1.35 -r1.36 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: msaitoh
Date: Thu Jan 18 03:36:24 UTC 2024
Modified Files:
src/sys/arch/riscv/riscv: kobj_machdep.c
Log Message:
s/FALLTHOUGH/FALLTHROUGH/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/kobj_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/kobj_machdep.c
diff -u src/sys/arch/riscv/riscv/kobj_machdep.c:1.5 src/sys/arch/riscv/riscv/kobj_machdep.c:1.6
--- src/sys/arch/riscv/riscv/kobj_machdep.c:1.5 Sun May 7 12:41:49 2023
+++ src/sys/arch/riscv/riscv/kobj_machdep.c Thu Jan 18 03:36:24 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: kobj_machdep.c,v 1.5 2023/05/07 12:41:49 skrll Exp $ */
+/* $NetBSD: kobj_machdep.c,v 1.6 2024/01/18 03:36:24 msaitoh Exp $ */
/*-
* Copyright (c) 2014,2023 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: kobj_machdep.c,v 1.5 2023/05/07 12:41:49 skrll Exp $");
+__RCSID("$NetBSD: kobj_machdep.c,v 1.6 2024/01/18 03:36:24 msaitoh Exp $");
#include
#include
@@ -168,7 +168,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
// XXXNH eh? what's with the symidx test?'
if (symidx == 0)
break;
- /* FALLTHOUGH */
+ /* FALLTHROUGH */
case R_RISCV_CALL_PLT:
case R_RISCV_CALL:
@@ -177,7 +177,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
case R_RISCV_RVC_JUMP:
case R_RISCV_32_PCREL:
addend -= (intptr_t)where; /* A -= P */
- /* FALLTHOUGH */
+ /* FALLTHROUGH */
#ifdef _LP64
case R_RISCV_64: /* doubleword64 S + A */
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: msaitoh Date: Thu Jan 18 03:36:24 UTC 2024 Modified Files: src/sys/arch/riscv/riscv: kobj_machdep.c Log Message: s/FALLTHOUGH/FALLTHROUGH/ in comment. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/kobj_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/starfive
Module Name:src Committed By: skrll Date: Wed Jan 17 07:05:35 UTC 2024 Modified Files: src/sys/arch/riscv/starfive: jh7100_clkc.h Log Message: Fix types of constants To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_clkc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/starfive/jh7100_clkc.h diff -u src/sys/arch/riscv/starfive/jh7100_clkc.h:1.1 src/sys/arch/riscv/starfive/jh7100_clkc.h:1.2 --- src/sys/arch/riscv/starfive/jh7100_clkc.h:1.1 Tue Jan 16 09:06:46 2024 +++ src/sys/arch/riscv/starfive/jh7100_clkc.h Wed Jan 17 07:05:35 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: jh7100_clkc.h,v 1.1 2024/01/16 09:06:46 skrll Exp $ */ +/* $NetBSD: jh7100_clkc.h,v 1.2 2024/01/17 07:05:35 skrll Exp $ */ /*- * Copyright (c) 2023 The NetBSD Foundation, Inc. @@ -49,8 +49,8 @@ #define JH7100_CLK_INT_MASK __BITS(7, 0) /* fractional divider min/max */ -#define JH7100_CLK_FRAC_MIN 100 -#define JH7100_CLK_FRAC_MAX (26600 - 1) +#define JH7100_CLK_FRAC_MIN 100UL +#define JH7100_CLK_FRAC_MAX (26600UL - 1) struct jh7100_clkc_softc; struct jh7100_clkc_clk;
CVS commit: src/sys/arch/riscv/starfive
Module Name:src Committed By: skrll Date: Wed Jan 17 07:05:35 UTC 2024 Modified Files: src/sys/arch/riscv/starfive: jh7100_clkc.h Log Message: Fix types of constants To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_clkc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/starfive
Module Name:src
Committed By: skrll
Date: Wed Jan 17 06:56:50 UTC 2024
Modified Files:
src/sys/arch/riscv/starfive: jh7100_clkc.c
Log Message:
Implement jh7100_clkc_fracdiv_get_rate
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_clkc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/starfive/jh7100_clkc.c
diff -u src/sys/arch/riscv/starfive/jh7100_clkc.c:1.1 src/sys/arch/riscv/starfive/jh7100_clkc.c:1.2
--- src/sys/arch/riscv/starfive/jh7100_clkc.c:1.1 Tue Jan 16 09:06:46 2024
+++ src/sys/arch/riscv/starfive/jh7100_clkc.c Wed Jan 17 06:56:50 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: jh7100_clkc.c,v 1.1 2024/01/16 09:06:46 skrll Exp $ */
+/* $NetBSD: jh7100_clkc.c,v 1.2 2024/01/17 06:56:50 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.1 2024/01/16 09:06:46 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.2 2024/01/17 06:56:50 skrll Exp $");
#include
@@ -395,9 +395,12 @@ jh7100_clkc_fracdiv_get_rate(struct jh71
if (rate == 0)
return 0;
- panic("Implement me");
+ uint32_t val = RD4(sc, jcc->jcc_reg);
+ unsigned long div100 =
+ 100UL * __SHIFTOUT(val, JH7100_CLK_INT_MASK) +
+ __SHIFTOUT(val, JH7100_CLK_FRAC_MASK);
- return rate;
+ return (div100 >= JH7100_CLK_FRAC_MIN) ? 100UL * rate / div100 : 0;
}
int
CVS commit: src/sys/arch/riscv/starfive
Module Name:src Committed By: skrll Date: Wed Jan 17 06:56:50 UTC 2024 Modified Files: src/sys/arch/riscv/starfive: jh7100_clkc.c Log Message: Implement jh7100_clkc_fracdiv_get_rate To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/starfive/jh7100_clkc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Tue Jan 16 09:06:47 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 files.generic64 Added Files: src/sys/arch/riscv/starfive: files.starfive jh7100_clkc.c jh7100_clkc.h Log Message: risc-v: add a StarTech JH7100 SoC clock driver The JH7100 is seen in the Beagle-V board. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/conf/GENERIC64 cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/files.generic64 cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/starfive/files.starfive \ src/sys/arch/riscv/starfive/jh7100_clkc.c \ src/sys/arch/riscv/starfive/jh7100_clkc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.2 src/sys/arch/riscv/conf/GENERIC64:1.3 --- src/sys/arch/riscv/conf/GENERIC64:1.2 Sat Jan 13 17:01:58 2024 +++ src/sys/arch/riscv/conf/GENERIC64 Tue Jan 16 09:06:46 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.2 2024/01/13 17:01:58 skrll Exp $ +# $NetBSD: GENERIC64,v 1.3 2024/01/16 09:06:46 skrll Exp $ # # GENERIC machine description file # @@ -49,5 +49,8 @@ options DEBUG # expensive debugging ch # Cache controller ccache* at fdt? # SiFive FU[57]40 L2 Cache +# Clock controller +jh7100clkc* at fdt? pass 2 # StarFive JH7100 clock controller + # Pull in optional local configuration - always at end cinclude "arch/riscv/conf/GENERIC64.local" Index: src/sys/arch/riscv/conf/files.generic64 diff -u src/sys/arch/riscv/conf/files.generic64:1.1 src/sys/arch/riscv/conf/files.generic64:1.2 --- src/sys/arch/riscv/conf/files.generic64:1.1 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/conf/files.generic64 Tue Jan 16 09:06:46 2024 @@ -1,7 +1,8 @@ -# $NetBSD: files.generic64,v 1.1 2023/05/07 12:41:48 skrll Exp $ +# $NetBSD: files.generic64,v 1.2 2024/01/16 09:06:46 skrll Exp $ # # Generic (RV64) kernel configuration info # -# Add other board files here +# Add other board / vendor files here include "arch/riscv/sifive/files.sifive" +include "arch/riscv/starfive/files.starfive" Added files: Index: src/sys/arch/riscv/starfive/files.starfive diff -u /dev/null src/sys/arch/riscv/starfive/files.starfive:1.1 --- /dev/null Tue Jan 16 09:06:47 2024 +++ src/sys/arch/riscv/starfive/files.starfive Tue Jan 16 09:06:46 2024 @@ -0,0 +1,10 @@ +# $NetBSD: files.starfive,v 1.1 2024/01/16 09:06:46 skrll Exp $ +# +# Configuration info for StarFive SoCs +# + +# JH7100 Clock controller +device jh7100clkc +attach jh7100clkc at fdt with jh7100_clkc +file arch/riscv/starfive/jh7100_clkc.c jh7100_clkc + Index: src/sys/arch/riscv/starfive/jh7100_clkc.c diff -u /dev/null src/sys/arch/riscv/starfive/jh7100_clkc.c:1.1 --- /dev/null Tue Jan 16 09:06:47 2024 +++ src/sys/arch/riscv/starfive/jh7100_clkc.c Tue Jan 16 09:06:46 2024 @@ -0,0 +1,924 @@ +/* $NetBSD: jh7100_clkc.c,v 1.1 2024/01/16 09:06:46 skrll Exp $ */ + +/*- + * Copyright (c) 2023 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Nick Hudson + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.1 2024/01/16 09:06:46 skrll Exp $"); + +#include + +#include +#include + +#include + +#include + +#include + + +#define JH7100_CLK_CPUNDBUS_ROOT 0 +#define JH7100_CLK_DSP_ROOT 2 +#define JH7100_CLK_GMACUSB_ROOT 3 +#define JH7100_CLK_PERH0_ROOT 4 +#define JH7100_CLK_PERH1_ROOT 5 +#define JH7100_CLK_VOUT_ROOT 7 +#define JH7100_CLK_AUDIO_ROOT 8 +#define JH7100_CLK_VOUTBUS_ROOT 11
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Tue Jan 16 09:06:47 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 files.generic64 Added Files: src/sys/arch/riscv/starfive: files.starfive jh7100_clkc.c jh7100_clkc.h Log Message: risc-v: add a StarTech JH7100 SoC clock driver The JH7100 is seen in the Beagle-V board. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/conf/GENERIC64 cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/files.generic64 cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/starfive/files.starfive \ src/sys/arch/riscv/starfive/jh7100_clkc.c \ src/sys/arch/riscv/starfive/jh7100_clkc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/sifive
Module Name:src Committed By: skrll Date: Sun Jan 14 07:13:15 UTC 2024 Modified Files: src/sys/arch/riscv/sifive: fu540_ccache.c Log Message: risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/fu540_ccache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/sifive
Module Name:src
Committed By: skrll
Date: Sun Jan 14 07:13:15 UTC 2024
Modified Files:
src/sys/arch/riscv/sifive: fu540_ccache.c
Log Message:
risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/fu540_ccache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/sifive/fu540_ccache.c
diff -u src/sys/arch/riscv/sifive/fu540_ccache.c:1.1 src/sys/arch/riscv/sifive/fu540_ccache.c:1.2
--- src/sys/arch/riscv/sifive/fu540_ccache.c:1.1 Sat Jan 13 17:01:58 2024
+++ src/sys/arch/riscv/sifive/fu540_ccache.c Sun Jan 14 07:13:15 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $ */
+/* $NetBSD: fu540_ccache.c,v 1.2 2024/01/14 07:13:15 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.2 2024/01/14 07:13:15 skrll Exp $");
#include
@@ -75,6 +75,9 @@ __KERNEL_RCSID(0, "$NetBSD: fu540_ccache
static const struct device_compatible_entry compat_data[] = {
{ .compat = "sifive,fu540-c000-ccache" },
{ .compat = "sifive,fu740-c000-ccache" },
+ { .compat = "starfive,jh7100-ccache" },
+ { .compat = "starfive,jh7110-ccache" },
+ { .compat = "starfive,ccache0" },
DEVICE_COMPAT_EOL
};
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Sat Jan 13 17:01:58 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 src/sys/arch/riscv/sifive: files.sifive Added Files: src/sys/arch/riscv/sifive: fu540_ccache.c Log Message: risc-v: add a SiFive FU[57]40/ L2 Cache controller driver To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/GENERIC64 cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/sifive/files.sifive cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/sifive/fu540_ccache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC64 diff -u src/sys/arch/riscv/conf/GENERIC64:1.1 src/sys/arch/riscv/conf/GENERIC64:1.2 --- src/sys/arch/riscv/conf/GENERIC64:1.1 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/conf/GENERIC64 Sat Jan 13 17:01:58 2024 @@ -1,4 +1,4 @@ -# $NetBSD: GENERIC64,v 1.1 2023/05/07 12:41:48 skrll Exp $ +# $NetBSD: GENERIC64,v 1.2 2024/01/13 17:01:58 skrll Exp $ # # GENERIC machine description file # @@ -46,5 +46,8 @@ options DEBUG # expensive debugging ch #options COMPAT_NETBSD32 #options EXEC_ELF32 +# Cache controller +ccache* at fdt? # SiFive FU[57]40 L2 Cache + # Pull in optional local configuration - always at end cinclude "arch/riscv/conf/GENERIC64.local" Index: src/sys/arch/riscv/sifive/files.sifive diff -u src/sys/arch/riscv/sifive/files.sifive:1.2 src/sys/arch/riscv/sifive/files.sifive:1.3 --- src/sys/arch/riscv/sifive/files.sifive:1.2 Sat Dec 3 09:40:56 2022 +++ src/sys/arch/riscv/sifive/files.sifive Sat Jan 13 17:01:58 2024 @@ -1,4 +1,4 @@ -# $NetBSD: files.sifive,v 1.2 2022/12/03 09:40:56 skrll Exp $ +# $NetBSD: files.sifive,v 1.3 2024/01/13 17:01:58 skrll Exp $ # # Configuration info for SiFive SoCs # @@ -8,3 +8,8 @@ device prci attach prci at fdt with fu540_prci file arch/riscv/sifive/fu540_prci.c fu540_prci + +# FU540 Level 2 Cache controller +device ccache: fdt +attach ccache at fdt with fu540_ccache +file arch/riscv/sifive/fu540_ccache.c fu540_ccache Added files: Index: src/sys/arch/riscv/sifive/fu540_ccache.c diff -u /dev/null src/sys/arch/riscv/sifive/fu540_ccache.c:1.1 --- /dev/null Sat Jan 13 17:01:58 2024 +++ src/sys/arch/riscv/sifive/fu540_ccache.c Sat Jan 13 17:01:58 2024 @@ -0,0 +1,226 @@ +/* $NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $ */ + +/*- + * Copyright (c) 2023 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Nick Hudson + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLinIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $"); + +#include + +#include + +#include + +#include + +#define CCACHE_CONFIG 0x +#define CCACHE_CONFIG_BANKS_MASK __BITS( 7, 0) +#define CCACHE_CONFIG_WAYS_MASK __BITS(15, 8) +#define CCACHE_CONFIG_LGSETS_MASK __BITS(23, 16) +#define CCACHE_CONFIG_LGBLOCKBYTES_MASK __BITS(31, 24) +#define CCACHE_WAYENABLE 0x0008 + +#define CCACHE_ECCINJECTERROR 0x0040 + +#define CCACHE_DIRECCFIX_LOW 0x0100 +#define CCACHE_DIRECCFIX_HIGH 0x0104 +#define CCACHE_DIRECCFIX_COUNT 0x0108 + +#define CCACHE_DIRECCFAIL_LOW 0x0120 +#define CCACHE_DIRECCFAIL_HIGH 0x0124 +#define CCACHE_DIRECCFAIL_COUNT 0x0128 + +#define CCACHE_DATECCFIX_LOW 0x0140 +#define CCACHE_DATECCFIX_HIGH 0x0144 +#define CCACHE_DATECCFIX_COUNT 0x0148 + +#define CCACHE_DATECCFAIL_LOW 0x0160 +#define CCACHE_DATECCFAIL_HIGH 0x0164 +#define CCACHE_DATECCFAIL_COUNT 0x0168 + +#define CCACHE_FLUSH64 0x0200 +#define CCACHE_FLUSH32 0x0250 + +#define
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Sat Jan 13 17:01:58 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC64 src/sys/arch/riscv/sifive: files.sifive Added Files: src/sys/arch/riscv/sifive: fu540_ccache.c Log Message: risc-v: add a SiFive FU[57]40/ L2 Cache controller driver To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/GENERIC64 cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/sifive/files.sifive cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/sifive/fu540_ccache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 13 16:43:08 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Attach generic system controllers To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC.common diff -u src/sys/arch/riscv/conf/GENERIC.common:1.8 src/sys/arch/riscv/conf/GENERIC.common:1.9 --- src/sys/arch/riscv/conf/GENERIC.common:1.8 Sat Jan 13 16:36:32 2024 +++ src/sys/arch/riscv/conf/GENERIC.common Sat Jan 13 16:43:08 2024 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC.common,v 1.8 2024/01/13 16:36:32 skrll Exp $ +# $NetBSD: GENERIC.common,v 1.9 2024/01/13 16:43:08 skrll Exp $ # # GENERIC common RISC-V kernel config items shared between 32 and 64 # kernels @@ -132,6 +132,9 @@ intc* at cpu? pass 1 # Fixed Clocks fclock* at fdt? pass 1 +# System Controller +syscon* at fdt? pass 1 # Generic System Controller + # Core-level Interrupt Control block #clint0 at fdt? pass 2
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 13 16:43:08 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Attach generic system controllers To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 13 16:36:32 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Group pass 1 attachments To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: skrll Date: Sat Jan 13 16:36:32 UTC 2024 Modified Files: src/sys/arch/riscv/conf: GENERIC.common Log Message: Group pass 1 attachments To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/GENERIC.common Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/GENERIC.common diff -u src/sys/arch/riscv/conf/GENERIC.common:1.7 src/sys/arch/riscv/conf/GENERIC.common:1.8 --- src/sys/arch/riscv/conf/GENERIC.common:1.7 Sun Sep 3 08:48:19 2023 +++ src/sys/arch/riscv/conf/GENERIC.common Sat Jan 13 16:36:32 2024 @@ -1,5 +1,5 @@ # -# $NetBSD: GENERIC.common,v 1.7 2023/09/03 08:48:19 skrll Exp $ +# $NetBSD: GENERIC.common,v 1.8 2024/01/13 16:36:32 skrll Exp $ # # GENERIC common RISC-V kernel config items shared between 32 and 64 # kernels @@ -129,15 +129,15 @@ cpu* at fdt? pass 0 intc* at cpu? pass 1 +# Fixed Clocks +fclock* at fdt? pass 1 + # Core-level Interrupt Control block #clint0 at fdt? pass 2 # Platform-Level Interrupt Controller plic* at fdt? pass 2 -# Clocks -fclock* at fdt? pass 1 - # UART com* at fdt? # UART
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Mon Jan 1 17:18:02 UTC 2024
Modified Files:
src/sys/arch/riscv/include: pmap.h
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
risc-v: probe the number of supported ASIDs
Flush the entire TLB if no ASIDs are supported on pmap_activate.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/include/pmap.h
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.22 src/sys/arch/riscv/include/pmap.h:1.23
--- src/sys/arch/riscv/include/pmap.h:1.22 Fri Oct 6 08:48:49 2023
+++ src/sys/arch/riscv/include/pmap.h Mon Jan 1 17:18:02 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.22 2023/10/06 08:48:49 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.23 2024/01/01 17:18:02 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -217,7 +217,16 @@ pmap_md_vca_clean(struct vm_page_md *mdp
static inline size_t
pmap_md_tlb_asid_max(void)
{
- return PMAP_TLB_NUM_PIDS - 1;
+ const register_t satp = csr_satp_read();
+ const register_t test = satp | SATP_ASID;
+
+ csr_satp_write(test);
+
+ const register_t ret = __SHIFTOUT(csr_satp_read(), SATP_ASID);
+ csr_satp_write(satp);
+
+ KASSERT(ret < PMAP_TLB_NUM_PIDS);
+ return ret;
}
static inline pt_entry_t *
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.19 src/sys/arch/riscv/riscv/pmap_machdep.c:1.20
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.19 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Mon Jan 1 17:18:02 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.19 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.20 2024/01/01 17:18:02 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#define __PMAP_PRIVATE
#include
-__RCSID("$NetBSD: pmap_machdep.c,v 1.19 2023/09/03 08:48:20 skrll Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.20 2024/01/01 17:18:02 skrll Exp $");
#include
#include
@@ -177,7 +177,8 @@ pmap_md_xtab_activate(struct pmap *pmap,
// UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
// struct cpu_info * const ci = curcpu();
- struct pmap_asid_info * const pai = PMAP_PAI(pmap, cpu_tlb_info(ci));
+ struct pmap_tlb_info * const ti = cpu_tlb_info(ci);
+ struct pmap_asid_info * const pai = PMAP_PAI(pmap, ti);
uint64_t satp =
#ifdef _LP64
@@ -189,6 +190,10 @@ pmap_md_xtab_activate(struct pmap *pmap,
__SHIFTIN(pmap->pm_md.md_ppn, SATP_PPN);
csr_satp_write(satp);
+
+ if (l && !tlbinfo_asids_p(ti)) {
+ tlb_invalidate_all();
+ }
}
void
@@ -329,6 +334,8 @@ pmap_bootstrap(vaddr_t vstart, vaddr_t v
// XXXNH per cpu?
pmap_tlb_info_init(_tlb0_info);
+ VPRINTF("ASID max %x ", pmap_tlb0_info.ti_asid_max);
+
#ifdef MULTIPROCESSOR
VPRINTF("kcpusets ");
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Mon Jan 1 17:18:02 UTC 2024 Modified Files: src/sys/arch/riscv/include: pmap.h src/sys/arch/riscv/riscv: pmap_machdep.c Log Message: risc-v: probe the number of supported ASIDs Flush the entire TLB if no ASIDs are supported on pmap_activate. To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/include/pmap.h cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/riscv/pmap_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Mon Jan 1 13:51:56 UTC 2024
Modified Files:
src/sys/arch/riscv/dev: plic_fdt.c
src/sys/arch/riscv/fdt: cpu_fdt.c riscv_fdtvar.h
Log Message:
Perform more checks before establishing external interrupt handlers for
each hart. The VisionFive2 DTS list the S7 core with status = "disabled".
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/dev/plic_fdt.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/fdt/cpu_fdt.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/fdt/riscv_fdtvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/dev/plic_fdt.c
diff -u src/sys/arch/riscv/dev/plic_fdt.c:1.3 src/sys/arch/riscv/dev/plic_fdt.c:1.4
--- src/sys/arch/riscv/dev/plic_fdt.c:1.3 Sat Sep 2 09:58:15 2023
+++ src/sys/arch/riscv/dev/plic_fdt.c Mon Jan 1 13:51:56 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: plic_fdt.c,v 1.3 2023/09/02 09:58:15 skrll Exp $ */
+/* $NetBSD: plic_fdt.c,v 1.4 2024/01/01 13:51:56 skrll Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.3 2023/09/02 09:58:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v 1.4 2024/01/01 13:51:56 skrll Exp $");
#include
@@ -42,6 +42,7 @@ __KERNEL_RCSID(0, "$NetBSD: plic_fdt.c,v
#include
#include
+#include
#include
#include
@@ -104,6 +105,58 @@ plic_fdt_match(device_t parent, cfdata_t
return of_compatible_match(faa->faa_phandle, compat_data);
}
+
+static void
+plic_fdt_attach_source(device_t self, int phandle, int context, int xref,
+int intr_source)
+{
+ struct plic_softc * const sc = device_private(self);
+ static const struct device_compatible_entry clint_compat_data[] = {
+ { .compat = "riscv,cpu-intc" },
+ DEVICE_COMPAT_EOL
+ };
+
+ if (!of_compatible_match(xref, clint_compat_data)) {
+ aprint_error_dev(self, "incompatiable CLINT "
+ "for PLIC for context %d\n", context);
+ return;
+ }
+
+ const int cpu_ref = OF_parent(xref);
+ if (!riscv_fdt_cpu_okay(cpu_ref)) {
+ aprint_verbose_dev(self, "inactive HART "
+ "for PLIC for context %d\n", context);
+ return;
+ }
+
+ /* What do we want to pass as arg to plic_intr */
+ void *ih = fdtbus_intr_establish_xname(phandle,
+ context, IPL_VM, FDT_INTR_MPSAFE,
+ plic_intr, sc, device_xname(self));
+ if (ih == NULL) {
+ aprint_error_dev(self, "couldn't install "
+ "interrupt handler\n");
+ } else {
+ char intrstr[128];
+ bool ok = fdtbus_intr_str(phandle, context,
+ intrstr, sizeof(intrstr));
+ aprint_verbose_dev(self, "interrupt %s handler "
+ "installed\n", ok ? intrstr : "(unk)");
+ }
+
+ if (intr_source == IRQ_SUPERVISOR_EXTERNAL) {
+ bus_addr_t hartid;
+ /* get cpuid for the parent node */
+ fdtbus_get_reg(cpu_ref, 0, , NULL);
+
+ KASSERT(context <= PLIC_MAX_CONTEXT);
+ sc->sc_context[hartid] = context;
+ aprint_verbose_dev(self, "hart %"PRId64" context %d\n",
+ hartid, context);
+ }
+}
+
+
static void
plic_fdt_attach(device_t parent, device_t self, void *aux)
{
@@ -179,49 +232,8 @@ plic_fdt_attach(device_t parent, device_
}
if (intr_source != -1) {
- /* What do we want to pass as arg to plic_intr */
- void *ih = fdtbus_intr_establish_xname(phandle,
- context, IPL_VM, FDT_INTR_MPSAFE,
- plic_intr, sc, device_xname(self));
- if (ih == NULL) {
-aprint_error_dev(self, "couldn't install "
-"interrupt handler\n");
- } else {
-char intrstr[128];
-bool ok = fdtbus_intr_str(phandle, context,
-intrstr, sizeof(intrstr));
-aprint_verbose_dev(self, "interrupt %s handler "
-"installed\n", ok ? intrstr : "(unk)");
- }
-
- if (intr_source == IRQ_SUPERVISOR_EXTERNAL) {
-/*
- * When finding context info, parent _must_ be a
- * compatbile clint device.
- */
-bus_addr_t hartid;
-int cpu_ref;
-static const struct device_compatible_entry clint_compat_data[] = {
- { .compat = "riscv,cpu-intc" },
- DEVICE_COMPAT_EOL
-};
-
-if (of_compatible_match(xref, clint_compat_data)) {
- /* get cpuid for the parent node */
- cpu_ref = OF_parent(xref);
- fdtbus_get_reg(cpu_ref, 0, , NULL);
-
- KASSERT(context <= PLIC_MAX_CONTEXT);
- sc->sc_context[hartid] = context;
- aprint_verbose_dev(self,
- "hart %"PRId64" context %d\n",
- hartid, context);
-} else {
- aprint_error_dev(self, "incompatiable CLINT "
- " for PLIC for context %d\n", context);
-}
-
- }
+ plic_fdt_attach_source(self, phandle, context, xref,
+intr_source);
}
len -= (intr_cells + 1) * 4;
data += (intr_cells + 1);
Index: src/sys/arch/riscv/fdt/cpu_fdt.c
diff -u src/sys/arch/riscv/fdt/cpu_fdt.c:1.3 src/sys/arch/riscv/fdt/cpu_fdt.c:1.4
--- src/sys/arch/riscv/fdt/cpu_fdt.c:1.3 Sun Sep 3 08:48:19 2023
+++
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Mon Jan 1 13:51:56 UTC 2024 Modified Files: src/sys/arch/riscv/dev: plic_fdt.c src/sys/arch/riscv/fdt: cpu_fdt.c riscv_fdtvar.h Log Message: Perform more checks before establishing external interrupt handlers for each hart. The VisionFive2 DTS list the S7 core with status = "disabled". To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/dev/plic_fdt.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/fdt/cpu_fdt.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/fdt/riscv_fdtvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Dec 25 13:31:01 UTC 2023 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: G/C ununsed and incorrect SIE_IM To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.29 src/sys/arch/riscv/include/sysreg.h:1.30 --- src/sys/arch/riscv/include/sysreg.h:1.29 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/include/sysreg.h Mon Dec 25 13:31:00 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.29 2023/05/07 12:41:48 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.30 2023/12/25 13:31:00 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -230,9 +230,6 @@ RISCVREG_READ_SET_CLEAR_INLINE(sie) // #define SIE_SSIE __BIT(1) // S-mode software interrupt enable /* Bit 0 is WIRI */ -/* Mask for all interrupts */ -#define SIE_IM (SIE_SEI | SIE_STIE | SIE_SSIE) /* XXX unused? */ - // U-mode sstatus values #ifdef _LP64 #define SR_USER64 (SR_SPIE | __SHIFTIN(SR_UXL_64, SR_UXL))
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Dec 25 13:31:01 UTC 2023 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: G/C ununsed and incorrect SIE_IM To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Mon Dec 25 13:21:30 UTC 2023
Modified Files:
src/sys/arch/riscv/fdt: intc_fdt.c
src/sys/arch/riscv/include: cpu.h
Log Message:
Count interrupts across harts and their local interrupt controllers
correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/fdt/intc_fdt.c
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/fdt/intc_fdt.c
diff -u src/sys/arch/riscv/fdt/intc_fdt.c:1.2 src/sys/arch/riscv/fdt/intc_fdt.c:1.3
--- src/sys/arch/riscv/fdt/intc_fdt.c:1.2 Mon Jun 12 19:04:13 2023
+++ src/sys/arch/riscv/fdt/intc_fdt.c Mon Dec 25 13:21:30 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: intc_fdt.c,v 1.2 2023/06/12 19:04:13 skrll Exp $ */
+/* $NetBSD: intc_fdt.c,v 1.3 2023/12/25 13:21:30 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.2 2023/06/12 19:04:13 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intc_fdt.c,v 1.3 2023/12/25 13:21:30 skrll Exp $");
#include
@@ -90,13 +90,36 @@ struct intc_fdt_softc {
struct intc_irq *sc_irq[IRQ_NSOURCES];
- struct evcnt *sc_evs[IRQ_NSOURCES];
+ struct evcnt sc_evs[IRQ_NSOURCES];
struct cpu_info *sc_ci;
cpuid_t sc_hartid;
};
-static struct intc_fdt_softc *intc_sc;
+static const char * const intc_sources[IRQ_NSOURCES] = {
+ /* Software interrupts */
+ "(reserved)",
+ "Supervisor software",
+ "Virtual Supervisor software",
+ "Machine software",
+
+ /* Timer interrupts */
+ "(reserved)",
+ "Supervisor timer",
+ "Virtual Supervisor timer",
+ "Machine timer",
+
+ /* External interrupts */
+ "(reserved)",
+ "Supervisor external",
+ "Virtual Supervisor external",
+ "Machine external",
+
+ "(reserved)",
+ "Supervisor guest external.",
+ "(reserved)",
+ "(reserved)"
+};
static void *
@@ -118,6 +141,9 @@ intc_intr_establish(struct intc_fdt_soft
irq->intr_source = source;
TAILQ_INIT(>intr_handlers);
sc->sc_irq[source] = irq;
+
+ evcnt_attach_dynamic(>sc_evs[source], EVCNT_TYPE_INTR, NULL,
+ device_xname(sc->sc_dev), intc_sources[source]);
} else {
if (irq->intr_arg == NULL || arg == NULL) {
device_printf(dev,
@@ -185,31 +211,6 @@ intc_fdt_disestablish(device_t dev, void
}
-static const char * const intc_sources[IRQ_NSOURCES] = {
- /* Software interrupts */
- "(reserved)",
- "Supervisor software",
- "Virtual Supervisor software",
- "Machine software",
-
- /* Timer interrupts */
- "(reserved)",
- "Supervisor timer",
- "Virtual Supervisor timer",
- "Machine timer",
-
- /* External interrupts */
- "(reserved)",
- "Supervisor external",
- "Virtual Supervisor external",
- "Machine external",
-
- "(reserved)",
- "Supervisor guest external.",
- "(reserved)",
- "(reserved)"
-};
-
static bool
intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
{
@@ -246,7 +247,7 @@ intc_intr_handler(struct trapframe *tf,
KASSERT(CAUSE_INTERRUPT_P(cause));
- struct intc_fdt_softc * const sc = intc_sc;
+ struct intc_fdt_softc * const sc = ci->ci_intcsoftc;
ci->ci_intr_depth++;
ci->ci_data.cpu_nintr++;
@@ -259,6 +260,8 @@ intc_intr_handler(struct trapframe *tf,
int source = ffs(pending) - 1;
struct intc_irq *irq = sc->sc_irq[source];
+ sc->sc_evs[source].ev_count++;
+
KASSERTMSG(irq != NULL, "source %d\n", source);
if (irq) {
@@ -326,13 +329,13 @@ intc_attach(device_t parent, device_t se
aprint_normal(": local interrupt controller\n");
struct intc_fdt_softc * const sc = device_private(self);
- intc_sc = sc;
riscv_intr_set_handler(intc_intr_handler);
sc->sc_dev = self;
sc->sc_ci = ci;
sc->sc_hartid = ci->ci_cpuid;
+ ci->ci_intcsoftc = sc;
intc_intr_establish(sc, IRQ_SUPERVISOR_TIMER, IPL_SCHED, IST_MPSAFE,
riscv_timer_intr, NULL, "clock");
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.14 src/sys/arch/riscv/include/cpu.h:1.15
--- src/sys/arch/riscv/include/cpu.h:1.14 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/include/cpu.h Mon Dec 25 13:21:30 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.14 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.15 2023/12/25 13:21:30 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -92,6 +92,7 @@ struct cpu_info {
#define CPUF_RUNNING __BIT(2) /* CPU is running */
#define CPUF_PAUSED __BIT(3) /* CPU is paused */
+ void *ci_intcsoftc;
volatile u_long ci_request_ipis;
/* bitmask of IPIs requested */
u_long ci_active_ipis; /* bitmask of IPIs being serviced */
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Mon Dec 25 13:21:30 UTC 2023 Modified Files: src/sys/arch/riscv/fdt: intc_fdt.c src/sys/arch/riscv/include: cpu.h Log Message: Count interrupts across harts and their local interrupt controllers correctly. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/fdt/intc_fdt.c cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/dev
Module Name:src Committed By: skrll Date: Mon Dec 25 13:01:59 UTC 2023 Modified Files: src/sys/arch/riscv/dev: plic.c Log Message: Deliver plic interrupts to the cpu^Whart establishing the interrupt handler. At least this is known to be a valid hart, but it might share some interrupts around too. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/dev/plic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/dev/plic.c diff -u src/sys/arch/riscv/dev/plic.c:1.3 src/sys/arch/riscv/dev/plic.c:1.4 --- src/sys/arch/riscv/dev/plic.c:1.3 Sat Dec 16 18:02:02 2023 +++ src/sys/arch/riscv/dev/plic.c Mon Dec 25 13:01:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: plic.c,v 1.3 2023/12/16 18:02:02 skrll Exp $ */ +/* $NetBSD: plic.c,v 1.4 2023/12/25 13:01:59 skrll Exp $ */ /*- * Copyright (c) 2022 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #include "opt_multiprocessor.h" #include -__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.3 2023/12/16 18:02:02 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.4 2023/12/25 13:01:59 skrll Exp $"); #include @@ -73,10 +73,10 @@ plic_intr_establish_xname(u_int irq, int struct plic_intrhand *ih; /* - * Choose hart 0. + * Choose calling hart. * XXX need a better hart selection method */ - u_int hartid = 0; + u_int hartid = curcpu()->ci_cpuid; evcnt_attach_dynamic(>sc_intrevs[irq], EVCNT_TYPE_INTR, NULL, "plic", xname);
CVS commit: src/sys/arch/riscv/dev
Module Name:src Committed By: skrll Date: Mon Dec 25 13:01:59 UTC 2023 Modified Files: src/sys/arch/riscv/dev: plic.c Log Message: Deliver plic interrupts to the cpu^Whart establishing the interrupt handler. At least this is known to be a valid hart, but it might share some interrupts around too. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/dev/plic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Fri Dec 22 08:41:59 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c
Log Message:
Minor stylistic changes. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_interface.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_interface.c
diff -u src/sys/arch/riscv/riscv/db_interface.c:1.4 src/sys/arch/riscv/riscv/db_interface.c:1.5
--- src/sys/arch/riscv/riscv/db_interface.c:1.4 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/db_interface.c Fri Dec 22 08:41:59 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.4 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.5 2023/12/22 08:41:59 skrll Exp $ */
/*
* Mach Operating System
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.4 2023/09/03 08:48:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.5 2023/12/22 08:41:59 skrll Exp $");
#ifdef _KERNEL_OPT
#include "opt_multiprocessor.h"
@@ -88,8 +88,6 @@ paddr_t kvtophys(vaddr_t);
int
kdb_trap(int type, db_regs_t *regs)
{
- int s;
-
switch (type) {
case CAUSE_BREAKPOINT: /* breakpoint */
printf("kernel: breakpoint\n");
@@ -106,7 +104,7 @@ kdb_trap(int type, db_regs_t *regs)
break;
}
- s = splhigh();
+ const int s = splhigh();
struct cpu_info * const ci = curcpu();
#if defined(MULTIPROCESSOR)
@@ -130,9 +128,9 @@ kdb_trap(int type, db_regs_t *regs)
ddb_regs = *regs;
ci->ci_ddb_regs = _regs;
db_active++;
- cnpollc(1);
+ cnpollc(true);
db_trap(type, 0 /*code*/);
- cnpollc(0);
+ cnpollc(false);
db_active--;
ci->ci_ddb_regs = NULL;
*regs = ddb_regs;
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.34 src/sys/arch/riscv/riscv/riscv_machdep.c:1.35
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.34 Sun Sep 3 08:48:20 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Fri Dec 22 08:41:59 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.34 2023/09/03 08:48:20 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include
-__RCSID("$NetBSD: riscv_machdep.c,v 1.34 2023/09/03 08:48:20 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.35 2023/12/22 08:41:59 skrll Exp $");
#include
@@ -460,13 +460,13 @@ cpu_reboot(int howto, char *bootstr)
printf("\n");
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
- cnpollc(1); /* for proper keyboard command handling */
+ cnpollc(true); /* for proper keyboard command handling */
if (cngetc() == 0) {
/* no console attached, so just hlt */
printf("No keyboard - cannot reboot after all.\n");
goto spin;
}
- cnpollc(0);
+ cnpollc(false);
}
printf("rebooting...\n");
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Fri Dec 22 08:41:59 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: db_interface.c riscv_machdep.c Log Message: Minor stylistic changes. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_interface.c cvs rdiff -u -r1.34 -r1.35 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/dev
Module Name:src
Committed By: skrll
Date: Sat Dec 16 18:02:02 UTC 2023
Modified Files:
src/sys/arch/riscv/dev: plic.c
Log Message:
Free memory on failure
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/dev/plic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/dev/plic.c
diff -u src/sys/arch/riscv/dev/plic.c:1.2 src/sys/arch/riscv/dev/plic.c:1.3
--- src/sys/arch/riscv/dev/plic.c:1.2 Sat Sep 2 09:58:15 2023
+++ src/sys/arch/riscv/dev/plic.c Sat Dec 16 18:02:02 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: plic.c,v 1.2 2023/09/02 09:58:15 skrll Exp $ */
+/* $NetBSD: plic.c,v 1.3 2023/12/16 18:02:02 skrll Exp $ */
/*-
* Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.2 2023/09/02 09:58:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.3 2023/12/16 18:02:02 skrll Exp $");
#include
@@ -190,17 +190,16 @@ plic_set_threshold(struct plic_softc *sc
int
plic_attach_common(struct plic_softc *sc, bus_addr_t addr, bus_size_t size)
{
- struct cpu_info *ci;
- CPU_INFO_ITERATOR cii;
- u_int irq;
+ const size_t szintrs = sizeof(*sc->sc_intr) * sc->sc_ndev;
+ const size_t szintrevs = sizeof(*sc->sc_intrevs) * sc->sc_ndev;
- sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * sc->sc_ndev,
- KM_SLEEP);
- sc->sc_intrevs = kmem_zalloc(sizeof(*sc->sc_intrevs) * sc->sc_ndev,
- KM_SLEEP);
+ sc->sc_intr = kmem_zalloc(szintrs, KM_SLEEP);
+ sc->sc_intrevs = kmem_zalloc(szintrevs, KM_SLEEP);
if (bus_space_map(sc->sc_bst, addr, size, 0, >sc_bsh) != 0) {
- aprint_error("couldn't map registers\n");
+ aprint_error_dev(sc->sc_dev, "couldn't map registers\n");
+ kmem_free(sc->sc_intr, szintrs);
+ kmem_free(sc->sc_intrevs, szintrevs);
return -1;
}
@@ -210,10 +209,13 @@ plic_attach_common(struct plic_softc *sc
plic_sc = sc;
/* Start with all interrupts disabled. */
+ u_int irq;
for (irq = PLIC_FIRST_IRQ; irq < sc->sc_ndev; irq++) {
plic_set_priority(sc, irq, 0);
}
+ struct cpu_info *ci;
+ CPU_INFO_ITERATOR cii;
/* Set priority thresholds for all interrupts to 0 (not masked). */
for (CPU_INFO_FOREACH(cii, ci)) {
plic_set_threshold(sc, ci->ci_cpuid, 0);
CVS commit: src/sys/arch/riscv/dev
Module Name:src Committed By: skrll Date: Sat Dec 16 18:02:02 UTC 2023 Modified Files: src/sys/arch/riscv/dev: plic.c Log Message: Free memory on failure To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/dev/plic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Oct 6 08:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Not all RISC-V CPUs have ASIDs To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.21 src/sys/arch/riscv/include/pmap.h:1.22 --- src/sys/arch/riscv/include/pmap.h:1.21 Sun Sep 3 08:48:20 2023 +++ src/sys/arch/riscv/include/pmap.h Fri Oct 6 08:48:49 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.21 2023/09/03 08:48:20 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.22 2023/10/06 08:48:49 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -81,6 +81,7 @@ #define PMAP_HWPAGEWALKER 1 #define PMAP_TLB_MAX 1 +#define PMAP_TLB_ALWAYS_ASIDS false #ifdef _LP64 #define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE)) #define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Oct 6 08:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Not all RISC-V CPUs have ASIDs To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: rin
Date: Thu Sep 14 03:25:31 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF
All related tests successfully pass.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/ptrace.h
diff -u src/sys/arch/riscv/include/ptrace.h:1.4 src/sys/arch/riscv/include/ptrace.h:1.5
--- src/sys/arch/riscv/include/ptrace.h:1.4 Thu Aug 24 05:40:08 2023
+++ src/sys/arch/riscv/include/ptrace.h Thu Sep 14 03:25:31 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.4 2023/08/24 05:40:08 rin Exp $ */
+/* $NetBSD: ptrace.h,v 1.5 2023/09/14 03:25:31 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -54,6 +54,8 @@
#define PTRACE_REG_SP(r) (r)->r_reg[1]
#define PTRACE_REG_INTRV(r) (r)->r_reg[9]
+#define PTRACE_ILLEGAL_ASM __asm __volatile("c.unimp" ::: "memory")
+
#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x02, 0x90 })
#define PTRACE_BREAKPOINT_ASM __asm __volatile("c.ebreak" ::: "memory")
#define PTRACE_BREAKPOINT_SIZE 2
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: rin Date: Thu Sep 14 03:25:31 UTC 2023 Modified Files: src/sys/arch/riscv/include: ptrace.h Log Message: riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF All related tests successfully pass. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/ptrace.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Thu Sep 7 12:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: trap.c Log Message: Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/riscv/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Thu Sep 7 12:48:49 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Handle CAUSE_LOAD_PAGE_FAULT in trap_pagefault_fixup
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.23 src/sys/arch/riscv/riscv/trap.c:1.24
--- src/sys/arch/riscv/riscv/trap.c:1.23 Tue Aug 22 07:11:15 2023
+++ src/sys/arch/riscv/riscv/trap.c Thu Sep 7 12:48:49 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $ */
+/* $NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.23 2023/08/22 07:11:15 rin Exp $");
+__RCSID("$NetBSD: trap.c,v 1.24 2023/09/07 12:48:49 skrll Exp $");
#include
@@ -358,6 +358,12 @@ trap_pagefault_fixup(struct trapframe *t
npte = opte;
switch (cause) {
+ case CAUSE_LOAD_PAGE_FAULT:
+ if ((npte & PTE_R) == 0) {
+npte |= PTE_A;
+attr |= VM_PAGEMD_REFERENCED;
+ }
+ break;
case CAUSE_STORE_ACCESS:
if ((npte & PTE_W) != 0) {
npte |= PTE_A | PTE_D;
@@ -380,8 +386,8 @@ trap_pagefault_fixup(struct trapframe *t
#endif
break;
default:
- panic("%s: Unhandled cause! 0x%016lx (%s)", __func__,
- (long)cause, cause_name(cause));
+ panic("%s: Unhandled cause (%#" PRIxREGISTER
+ ") for addr %lx", __func__, cause, addr);
}
if (attr == 0)
return false;
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sun Sep 3 08:48:20 UTC 2023
Modified Files:
src/sys/arch/riscv/conf: GENERIC.common files.riscv
src/sys/arch/riscv/fdt: cpu_fdt.c
src/sys/arch/riscv/include: cpu.h intr.h pmap.h
src/sys/arch/riscv/riscv: cpu.c cpu_subr.c db_interface.c ipifuncs.c
locore.S pmap_machdep.c riscv_machdep.c riscv_tlb.c
Log Message:
Fix and enable MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/GENERIC.common
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/fdt/cpu_fdt.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/cpu.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/intr.h
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/pmap.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_subr.c \
src/sys/arch/riscv/riscv/db_interface.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/ipifuncs.c \
src/sys/arch/riscv/riscv/riscv_tlb.c
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/riscv/pmap_machdep.c
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/GENERIC.common
diff -u src/sys/arch/riscv/conf/GENERIC.common:1.6 src/sys/arch/riscv/conf/GENERIC.common:1.7
--- src/sys/arch/riscv/conf/GENERIC.common:1.6 Tue Aug 1 22:06:23 2023
+++ src/sys/arch/riscv/conf/GENERIC.common Sun Sep 3 08:48:19 2023
@@ -1,5 +1,5 @@
#
-# $NetBSD: GENERIC.common,v 1.6 2023/08/01 22:06:23 rjs Exp $
+# $NetBSD: GENERIC.common,v 1.7 2023/09/03 08:48:19 skrll Exp $
#
# GENERIC common RISC-V kernel config items shared between 32 and 64
# kernels
@@ -8,7 +8,7 @@
maxusers 64 # estimated number of users
options FDT
-#options MULTIPROCESSOR
+options MULTIPROCESSOR
# Standard system options
options FPE # Floating-point extension support
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.13 src/sys/arch/riscv/conf/files.riscv:1.14
--- src/sys/arch/riscv/conf/files.riscv:1.13 Mon Jun 12 19:04:13 2023
+++ src/sys/arch/riscv/conf/files.riscv Sun Sep 3 08:48:19 2023
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.13 2023/06/12 19:04:13 skrll Exp $
+# $NetBSD: files.riscv,v 1.14 2023/09/03 08:48:19 skrll Exp $
#
maxpartitions 16
@@ -64,7 +64,6 @@ file kern/subr_disk_mbr.c disk
file uvm/pmap/pmap.c
file uvm/pmap/pmap_devmap.c
file uvm/pmap/pmap_segtab.c
-file uvm/pmap/pmap_synci.c
file uvm/pmap/pmap_tlb.c
device plic
Index: src/sys/arch/riscv/fdt/cpu_fdt.c
diff -u src/sys/arch/riscv/fdt/cpu_fdt.c:1.2 src/sys/arch/riscv/fdt/cpu_fdt.c:1.3
--- src/sys/arch/riscv/fdt/cpu_fdt.c:1.2 Mon Jun 12 19:04:13 2023
+++ src/sys/arch/riscv/fdt/cpu_fdt.c Sun Sep 3 08:48:19 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_fdt.c,v 1.2 2023/06/12 19:04:13 skrll Exp $ */
+/* $NetBSD: cpu_fdt.c,v 1.3 2023/09/03 08:48:19 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -29,7 +29,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.2 2023/06/12 19:04:13 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v 1.3 2023/09/03 08:48:19 skrll Exp $");
#include
#include
@@ -44,7 +44,6 @@ __KERNEL_RCSID(0, "$NetBSD: cpu_fdt.c,v
#include
-#ifdef MULTIPROCESSOR
static bool
riscv_fdt_cpu_okay(const int child)
{
@@ -65,33 +64,32 @@ riscv_fdt_cpu_okay(const int child)
return true;
}
}
-#endif /* MULTIPROCESSOR */
void
riscv_fdt_cpu_bootstrap(void)
{
-#ifdef MULTIPROCESSOR
-
const int cpus = OF_finddevice("/cpus");
if (cpus == -1) {
aprint_error("%s: no /cpus node found\n", __func__);
- riscv_cpu_max = 1;
return;
}
- /* Count harts and add hart IDs to to cpu_hartid array */
- size_t cpuindex = 1;
+ /* Count harts and add hart index numbers to the cpu_hartindex array */
+ u_int cpuindex = 1;
for (int child = OF_child(cpus); child; child = OF_peer(child)) {
if (!riscv_fdt_cpu_okay(child))
continue;
- riscv_cpu_max++;
-
uint64_t reg;
if (fdtbus_get_reg64(child, 0, , NULL) != 0)
continue;
const cpuid_t hartid = reg;
+ if (hartid > MAXCPUS) {
+ aprint_error("hart id too big %lu (%u)", hartid,
+ MAXCPUS);
+ continue;
+ }
struct sbiret sbiret = sbi_hart_get_status(hartid);
switch (sbiret.error) {
@@ -107,22 +105,19 @@ riscv_fdt_cpu_bootstrap(void)
/* Assume the BP is the only one started. */
if (sbiret.value == SBI_HART_STARTED) {
- if (cpu_hartid[0] != -1) {
+ if (cpu_bphartid != ~0UL) {
panic("more than 1 hart started");
}
- cpu_hartid[0] = hartid;
+ cpu_bphartid = hartid;
+ cpu_hartindex[hartid] = 0;
continue;
}
KASSERT(cpuindex < MAXCPUS);
-
CVS commit: src/sys/arch/riscv
Module Name:src Committed By: skrll Date: Sun Sep 3 08:48:20 UTC 2023 Modified Files: src/sys/arch/riscv/conf: GENERIC.common files.riscv src/sys/arch/riscv/fdt: cpu_fdt.c src/sys/arch/riscv/include: cpu.h intr.h pmap.h src/sys/arch/riscv/riscv: cpu.c cpu_subr.c db_interface.c ipifuncs.c locore.S pmap_machdep.c riscv_machdep.c riscv_tlb.c Log Message: Fix and enable MULTIPROCESSOR To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/GENERIC.common cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/conf/files.riscv cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/fdt/cpu_fdt.c cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/cpu.h cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/intr.h cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/pmap.h cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/cpu.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_subr.c \ src/sys/arch/riscv/riscv/db_interface.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/ipifuncs.c \ src/sys/arch/riscv/riscv/riscv_tlb.c cvs rdiff -u -r1.42 -r1.43 src/sys/arch/riscv/riscv/locore.S cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/riscv/pmap_machdep.c cvs rdiff -u -r1.33 -r1.34 src/sys/arch/riscv/riscv/riscv_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
