CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Tue May 28 06:57:03 UTC 2024
Modified Files:
src/sys/arch/riscv/include: netbsd32_machdep.h
Log Message:
Change MIPS to RISC-V.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/netbsd32_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/netbsd32_machdep.h
diff -u src/sys/arch/riscv/include/netbsd32_machdep.h:1.1 src/sys/arch/riscv/include/netbsd32_machdep.h:1.2
--- src/sys/arch/riscv/include/netbsd32_machdep.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/netbsd32_machdep.h Tue May 28 06:57:03 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: netbsd32_machdep.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: netbsd32_machdep.h,v 1.2 2024/05/28 06:57:03 skrll Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include
/*
- * On MIPS, pointers are signed.
+ * On RISC-V, pointers are signed.
*/
#define NETBSD32_POINTER_TYPE int32_t
typedef struct { NETBSD32_POINTER_TYPE i32; } netbsd32_pointer_t;
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue May 28 06:57:03 UTC 2024 Modified Files: src/sys/arch/riscv/include: netbsd32_machdep.h Log Message: Change MIPS to RISC-V. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/netbsd32_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:17:57 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: No volatile needed on asm to _read_ rounding mode, exceptions.
These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).
I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine. But I don't know how to
spell the right thing in gcclish.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.32 src/sys/arch/riscv/include/sysreg.h:1.33
--- src/sys/arch/riscv/include/sysreg.h:1.32 Tue May 14 15:16:51 2024
+++ src/sys/arch/riscv/include/sysreg.h Tue May 14 15:17:57 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.32 2024/05/14 15:16:51 riastradh Exp $ */
+/* $NetBSD: sysreg.h,v 1.33 2024/05/14 15:17:57 riastradh Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@ static inline uint32_t
fcsr_read(void)
{
uint32_t __fcsr;
- asm volatile("frcsr %0" : "=r"(__fcsr) :: "memory");
+ asm("frcsr %0" : "=r"(__fcsr) :: "memory");
return __fcsr;
}
@@ -73,7 +73,7 @@ static inline uint32_t
fcsr_fflags_read(void)
{
uint32_t __old;
- asm volatile("frflags %0" : "=r"(__old) :: "memory");
+ asm("frflags %0" : "=r"(__old) :: "memory");
return __old;
}
@@ -89,7 +89,7 @@ static inline uint32_t
fcsr_frm_read(void)
{
uint32_t __old;
- asm volatile("frrm\t%0" : "=r"(__old) :: "memory");
+ asm("frrm\t%0" : "=r"(__old) :: "memory");
return __old;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue May 14 15:17:57 UTC 2024 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: riscv: No volatile needed on asm to _read_ rounding mode, exceptions. These instructions can be omitted if the return values are unused. In contrast, _writes_ to the rounding mode or exceptions must not be omitted (even if we ignore the return value, which is the old value of the field). I think "memory" is the wrong clobber on these asm blocks too; they can't be reordered around _floating-point_ instructions, while reordering around loads and stores is fine. But I don't know how to spell the right thing in gcclish. To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: riastradh
Date: Tue May 14 15:16:51 UTC 2024
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
riscv: Fix reading and writing frm and fflags.
The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.31 src/sys/arch/riscv/include/sysreg.h:1.32
--- src/sys/arch/riscv/include/sysreg.h:1.31 Mon Feb 5 21:46:05 2024
+++ src/sys/arch/riscv/include/sysreg.h Tue May 14 15:16:51 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.31 2024/02/05 21:46:05 andvar Exp $ */
+/* $NetBSD: sysreg.h,v 1.32 2024/05/14 15:16:51 riastradh Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -61,7 +61,6 @@ fcsr_read(void)
return __fcsr;
}
-
static inline uint32_t
fcsr_write(uint32_t __new)
{
@@ -75,16 +74,15 @@ fcsr_fflags_read(void)
{
uint32_t __old;
asm volatile("frflags %0" : "=r"(__old) :: "memory");
- return __SHIFTOUT(__old, FCSR_FFLAGS);
+ return __old;
}
static inline uint32_t
fcsr_fflags_write(uint32_t __new)
{
uint32_t __old;
- __new = __SHIFTIN(__new, FCSR_FFLAGS);
asm volatile("fsflags %0, %1" : "=r"(__old) : "r"(__new) : "memory");
- return __SHIFTOUT(__old, FCSR_FFLAGS);
+ return __old;
}
static inline uint32_t
@@ -92,19 +90,17 @@ fcsr_frm_read(void)
{
uint32_t __old;
asm volatile("frrm\t%0" : "=r"(__old) :: "memory");
- return __SHIFTOUT(__old, FCSR_FRM);
+ return __old;
}
static inline uint32_t
fcsr_frm_write(uint32_t __new)
{
uint32_t __old;
- __new = __SHIFTIN(__new, FCSR_FRM);
asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new) : "memory");
- return __SHIFTOUT(__old, FCSR_FRM);
+ return __old;
}
-
#define RISCVREG_READ_INLINE(regname) \
static inline uintptr_t \
csr_##regname##_read(void) \
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue May 14 15:16:51 UTC 2024 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: riscv: Fix reading and writing frm and fflags. The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and shifting needed -- __SHIFTIN/__SHIFTOUT is wrong. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Sun May 12 20:04:12 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: riscv fenv.h: Make sure FE_* exception constants have type int. This may not be formally required by the standard, but the values must be representable by int since that's the type that functions like fetestexcept and feclearexcept traffic in. And this is less work than changing all the printf %d users in tree. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Sun May 12 20:04:12 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: riscv fenv.h: Make sure FE_* exception constants have type int. This may not be formally required by the standard, but the values must be representable by int since that's the type that functions like fetestexcept and feclearexcept traffic in. And this is less work than changing all the printf %d users in tree. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/fenv.h diff -u src/sys/arch/riscv/include/fenv.h:1.4 src/sys/arch/riscv/include/fenv.h:1.5 --- src/sys/arch/riscv/include/fenv.h:1.4 Fri May 10 08:20:37 2024 +++ src/sys/arch/riscv/include/fenv.h Sun May 12 20:04:12 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: fenv.h,v 1.4 2024/05/10 08:20:37 skrll Exp $ */ +/* $NetBSD: fenv.h,v 1.5 2024/05/12 20:04:12 riastradh Exp $ */ /* * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 @@ -11,11 +11,11 @@ typedef int fenv_t; /* FPSCR */ typedef int fexcept_t; -#define FE_INEXACT __BIT(0) /* Result inexact */ -#define FE_UNDERFLOW __BIT(1) /* Result underflowed */ -#define FE_OVERFLOW __BIT(2) /* Result overflowed */ -#define FE_DIVBYZERO __BIT(3) /* divide-by-zero */ -#define FE_INVALID __BIT(4) /* Result invalid */ +#define FE_INEXACT ((int)__BIT(0)) /* Result inexact */ +#define FE_UNDERFLOW ((int)__BIT(1)) /* Result underflowed */ +#define FE_OVERFLOW ((int)__BIT(2)) /* Result overflowed */ +#define FE_DIVBYZERO ((int)__BIT(3)) /* divide-by-zero */ +#define FE_INVALID ((int)__BIT(4)) /* Result invalid */ #define FE_ALL_EXCEPT \ (FE_INEXACT | FE_UNDERFLOW | FE_OVERFLOW | FE_DIVBYZERO | FE_INVALID)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 10 08:20:37 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: Use __BIT and fix FE_INEXACT To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/fenv.h diff -u src/sys/arch/riscv/include/fenv.h:1.3 src/sys/arch/riscv/include/fenv.h:1.4 --- src/sys/arch/riscv/include/fenv.h:1.3 Sat Mar 14 16:12:16 2020 +++ src/sys/arch/riscv/include/fenv.h Fri May 10 08:20:37 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: fenv.h,v 1.3 2020/03/14 16:12:16 skrll Exp $ */ +/* $NetBSD: fenv.h,v 1.4 2024/05/10 08:20:37 skrll Exp $ */ /* * Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995 @@ -11,13 +11,14 @@ typedef int fenv_t; /* FPSCR */ typedef int fexcept_t; -#define FE_INEXACT 0x00 /* Result inexact */ -#define FE_UNDERFLOW 0x02 /* Result underflowed */ -#define FE_OVERFLOW 0x04 /* Result overflowed */ -#define FE_DIVBYZERO 0x08 /* divide-by-zero */ -#define FE_INVALID 0x10 /* Result invalid */ +#define FE_INEXACT __BIT(0) /* Result inexact */ +#define FE_UNDERFLOW __BIT(1) /* Result underflowed */ +#define FE_OVERFLOW __BIT(2) /* Result overflowed */ +#define FE_DIVBYZERO __BIT(3) /* divide-by-zero */ +#define FE_INVALID __BIT(4) /* Result invalid */ -#define FE_ALL_EXCEPT 0x1f +#define FE_ALL_EXCEPT \ +(FE_INEXACT | FE_UNDERFLOW | FE_OVERFLOW | FE_DIVBYZERO | FE_INVALID) #define FE_TONEAREST 0 /* round to nearest representable number */ #define FE_TOWARDZERO 1 /* round to zero (truncate) */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 10 08:20:37 UTC 2024 Modified Files: src/sys/arch/riscv/include: fenv.h Log Message: Use __BIT and fix FE_INEXACT To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/fenv.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat May 4 12:42:09 UTC 2024
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix the __greg_t typedef for riscv32
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/mcontext.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/mcontext.h
diff -u src/sys/arch/riscv/include/mcontext.h:1.7 src/sys/arch/riscv/include/mcontext.h:1.8
--- src/sys/arch/riscv/include/mcontext.h:1.7 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/mcontext.h Sat May 4 12:42:09 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.7 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: mcontext.h,v 1.8 2024/05/04 12:42:09 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -48,7 +48,7 @@ union __fpreg {
#define _BSD_FPREG_T_ union __fpreg
#endif
-typedef __uint64_t __greg_t;
+typedef long __greg_t;
typedef __greg_t __gregset_t[_NGREG];
typedef __uint32_t __greg32_t;
typedef __greg32_t __gregset32_t[_NGREG];
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 4 12:42:09 UTC 2024 Modified Files: src/sys/arch/riscv/include: mcontext.h Log Message: Fix the __greg_t typedef for riscv32 To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/mcontext.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Fri May 3 07:11:14 UTC 2024
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
Use the _X_FOO register macros instead of magic numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/ptrace.h
diff -u src/sys/arch/riscv/include/ptrace.h:1.5 src/sys/arch/riscv/include/ptrace.h:1.6
--- src/sys/arch/riscv/include/ptrace.h:1.5 Thu Sep 14 03:25:31 2023
+++ src/sys/arch/riscv/include/ptrace.h Fri May 3 07:11:14 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.5 2023/09/14 03:25:31 rin Exp $ */
+/* $NetBSD: ptrace.h,v 1.6 2024/05/03 07:11:14 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -49,10 +49,10 @@
#include
#define PTRACE_REG_PC(r) (r)->r_pc
-#define PTRACE_REG_FP(r) (r)->r_reg[7]
+#define PTRACE_REG_FP(r) (r)->r_reg[_X_S0]
#define PTRACE_REG_SET_PC(r, v) (r)->r_pc = (v)
-#define PTRACE_REG_SP(r) (r)->r_reg[1]
-#define PTRACE_REG_INTRV(r) (r)->r_reg[9]
+#define PTRACE_REG_SP(r) (r)->r_reg[_X_SP]
+#define PTRACE_REG_INTRV(r) (r)->r_reg[_X_A0]
#define PTRACE_ILLEGAL_ASM __asm __volatile("c.unimp" ::: "memory")
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri May 3 07:11:14 UTC 2024 Modified Files: src/sys/arch/riscv/include: ptrace.h Log Message: Use the _X_FOO register macros instead of magic numbers. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/ptrace.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Dec 25 13:31:01 UTC 2023 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: G/C ununsed and incorrect SIE_IM To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.29 src/sys/arch/riscv/include/sysreg.h:1.30 --- src/sys/arch/riscv/include/sysreg.h:1.29 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/include/sysreg.h Mon Dec 25 13:31:00 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.29 2023/05/07 12:41:48 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.30 2023/12/25 13:31:00 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -230,9 +230,6 @@ RISCVREG_READ_SET_CLEAR_INLINE(sie) // #define SIE_SSIE __BIT(1) // S-mode software interrupt enable /* Bit 0 is WIRI */ -/* Mask for all interrupts */ -#define SIE_IM (SIE_SEI | SIE_STIE | SIE_SSIE) /* XXX unused? */ - // U-mode sstatus values #ifdef _LP64 #define SR_USER64 (SR_SPIE | __SHIFTIN(SR_UXL_64, SR_UXL))
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Dec 25 13:31:01 UTC 2023 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: G/C ununsed and incorrect SIE_IM To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Oct 6 08:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Not all RISC-V CPUs have ASIDs To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.21 src/sys/arch/riscv/include/pmap.h:1.22 --- src/sys/arch/riscv/include/pmap.h:1.21 Sun Sep 3 08:48:20 2023 +++ src/sys/arch/riscv/include/pmap.h Fri Oct 6 08:48:49 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.21 2023/09/03 08:48:20 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.22 2023/10/06 08:48:49 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -81,6 +81,7 @@ #define PMAP_HWPAGEWALKER 1 #define PMAP_TLB_MAX 1 +#define PMAP_TLB_ALWAYS_ASIDS false #ifdef _LP64 #define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE)) #define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Oct 6 08:48:49 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Not all RISC-V CPUs have ASIDs To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: rin
Date: Thu Sep 14 03:25:31 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF
All related tests successfully pass.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/ptrace.h
diff -u src/sys/arch/riscv/include/ptrace.h:1.4 src/sys/arch/riscv/include/ptrace.h:1.5
--- src/sys/arch/riscv/include/ptrace.h:1.4 Thu Aug 24 05:40:08 2023
+++ src/sys/arch/riscv/include/ptrace.h Thu Sep 14 03:25:31 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.4 2023/08/24 05:40:08 rin Exp $ */
+/* $NetBSD: ptrace.h,v 1.5 2023/09/14 03:25:31 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -54,6 +54,8 @@
#define PTRACE_REG_SP(r) (r)->r_reg[1]
#define PTRACE_REG_INTRV(r) (r)->r_reg[9]
+#define PTRACE_ILLEGAL_ASM __asm __volatile("c.unimp" ::: "memory")
+
#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x02, 0x90 })
#define PTRACE_BREAKPOINT_ASM __asm __volatile("c.ebreak" ::: "memory")
#define PTRACE_BREAKPOINT_SIZE 2
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: rin Date: Thu Sep 14 03:25:31 UTC 2023 Modified Files: src/sys/arch/riscv/include: ptrace.h Log Message: riscv: ptrace: Add PTRACE_ILLEGAL_ASM for ATF All related tests successfully pass. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/ptrace.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Sep 2 09:27:09 UTC 2023 Modified Files: src/sys/arch/riscv/include: db_machdep.h Log Message: Fix a comment and enable RISC-V ddb mach commands To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/db_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Sep 2 09:27:09 UTC 2023 Modified Files: src/sys/arch/riscv/include: db_machdep.h Log Message: Fix a comment and enable RISC-V ddb mach commands To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/db_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/db_machdep.h diff -u src/sys/arch/riscv/include/db_machdep.h:1.8 src/sys/arch/riscv/include/db_machdep.h:1.9 --- src/sys/arch/riscv/include/db_machdep.h:1.8 Mon Jun 12 19:04:14 2023 +++ src/sys/arch/riscv/include/db_machdep.h Sat Sep 2 09:27:09 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: db_machdep.h,v 1.8 2023/06/12 19:04:14 skrll Exp $ */ +/* $NetBSD: db_machdep.h,v 1.9 2023/09/02 09:27:09 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -107,7 +107,7 @@ typedef register_t kgdb_reg_t; #define KGDB_BUFLEN 1024 /* - * RISCV cpus have no hardware single-step. + * RISC-V harts have no hardware single-step. */ #define SOFTWARE_SSTEP @@ -126,12 +126,10 @@ bool ddb_running_on_this_cpu_p(void); bool ddb_running_on_any_cpu_p(void); void db_resume_others(void); -#if 0 /* * We have machine-dependent commands. */ #define DB_MACHINE_COMMANDS -#endif void dump_trapframe(const struct trapframe *, void (*)(const char *, ...) __printflike(1, 2));
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: rin
Date: Thu Aug 24 05:40:08 UTC 2023
Modified Files:
src/sys/arch/riscv/include: ptrace.h
Log Message:
riscv: Add PTRACE_BREAKPOINT and friends for ATF
Since its size must be determined a priori, explicitly use
c.ebreak for sure.
Now, related tests in ATF successfully pass for riscv64,
as far as I can see.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/ptrace.h
diff -u src/sys/arch/riscv/include/ptrace.h:1.3 src/sys/arch/riscv/include/ptrace.h:1.4
--- src/sys/arch/riscv/include/ptrace.h:1.3 Tue Jun 18 21:18:12 2019
+++ src/sys/arch/riscv/include/ptrace.h Thu Aug 24 05:40:08 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.3 2019/06/18 21:18:12 kamil Exp $ */
+/* $NetBSD: ptrace.h,v 1.4 2023/08/24 05:40:08 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -54,4 +54,8 @@
#define PTRACE_REG_SP(r) (r)->r_reg[1]
#define PTRACE_REG_INTRV(r) (r)->r_reg[9]
+#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x02, 0x90 })
+#define PTRACE_BREAKPOINT_ASM __asm __volatile("c.ebreak" ::: "memory")
+#define PTRACE_BREAKPOINT_SIZE 2
+
#endif /* _RISCV_PTRACE_H_ */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: rin Date: Thu Aug 24 05:40:08 UTC 2023 Modified Files: src/sys/arch/riscv/include: ptrace.h Log Message: riscv: Add PTRACE_BREAKPOINT and friends for ATF Since its size must be determined a priori, explicitly use c.ebreak for sure. Now, related tests in ATF successfully pass for riscv64, as far as I can see. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/ptrace.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Aug 12 07:48:12 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache
Match other definitions of pmap_md_page_syncicache argument naming by
renaming the 2nd arg to 'onproc'
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.19 src/sys/arch/riscv/include/pmap.h:1.20
--- src/sys/arch/riscv/include/pmap.h:1.19 Wed Jul 26 06:58:34 2023
+++ src/sys/arch/riscv/include/pmap.h Sat Aug 12 07:48:11 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.19 2023/07/26 06:58:34 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.20 2023/08/12 07:48:11 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -191,7 +191,7 @@ pmap_md_tlb_check_entry(void *ctx, vaddr
}
static inline void
-pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *kc)
+pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *onproc)
{
__asm __volatile("fence\trw,rw; fence.i" ::: "memory");
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Aug 12 07:48:12 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: risc-v: Use 'onproc' for 2nd arg of pmap_md_page_syncicache Match other definitions of pmap_md_page_syncicache argument naming by renaming the 2nd arg to 'onproc' To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Jul 29 06:59:47 UTC 2023 Modified Files: src/sys/arch/riscv/include: cpu.h Log Message: Slight reformatting. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Jul 29 06:59:47 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Slight reformatting. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.12 src/sys/arch/riscv/include/cpu.h:1.13
--- src/sys/arch/riscv/include/cpu.h:1.12 Mon Jun 12 19:04:14 2023
+++ src/sys/arch/riscv/include/cpu.h Sat Jul 29 06:59:47 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.12 2023/06/12 19:04:14 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.13 2023/07/29 06:59:47 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -86,23 +86,23 @@ struct cpu_info {
struct pmap_tlb_info *ci_tlb_info;
#ifdef MULTIPROCESSOR
-
volatile u_long ci_flags;
+#define CPUF_PRIMARY __BIT(0) /* CPU is primary CPU */
+#define CPUF_PRESENT __BIT(1) /* CPU is present */
+#define CPUF_RUNNING __BIT(2) /* CPU is running */
+#define CPUF_PAUSED __BIT(3) /* CPU is paused */
+#define CPUF_USERPMAP __BIT(4) /* CPU has a user pmap activated */
+
volatile u_long ci_request_ipis;
- /* bitmask of IPIs requested */
- u_long ci_active_ipis; /* bitmask of IPIs being serviced */
+ /* bitmask of IPIs requested */
+ u_long ci_active_ipis; /* bitmask of IPIs being serviced */
- struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */
+ struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */
struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters */
struct evcnt ci_evcnt_synci_onproc_rqst;
struct evcnt ci_evcnt_synci_deferred_rqst;
struct evcnt ci_evcnt_synci_ipi_rqst;
-#define CPUF_PRIMARY __BIT(0) /* CPU is primary CPU */
-#define CPUF_PRESENT __BIT(1) /* CPU is present */
-#define CPUF_RUNNING __BIT(2) /* CPU is running */
-#define CPUF_PAUSED __BIT(3) /* CPU is paused */
-#define CPUF_USERPMAP __BIT(4) /* CPU has a user pmap activated */
kcpuset_t *ci_shootdowncpus;
kcpuset_t *ci_multicastcpus;
kcpuset_t *ci_watchcpus;
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue Jul 4 01:02:50 UTC 2023 Modified Files: src/sys/arch/riscv/include: int_const.h Log Message: riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types. XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/int_const.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/int_const.h diff -u src/sys/arch/riscv/include/int_const.h:1.1 src/sys/arch/riscv/include/int_const.h:1.2 --- src/sys/arch/riscv/include/int_const.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/int_const.h Tue Jul 4 01:02:50 2023 @@ -1,19 +1,32 @@ -/* $NetBSD: int_const.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: int_const.h,v 1.2 2023/07/04 01:02:50 riastradh Exp $ */ #ifndef __INTMAX_C_SUFFIX__ #define __INT8_C_SUFFIX__ #define __INT16_C_SUFFIX__ #define __INT32_C_SUFFIX__ +#ifdef _LP64 +#define __INT64_C_SUFFIX__ L +#else #define __INT64_C_SUFFIX__ LL +#endif #define __UINT8_C_SUFFIX__ #define __UINT16_C_SUFFIX__ #define __UINT32_C_SUFFIX__ +#ifdef _LP64 +#define __UINT64_C_SUFFIX__ UL +#else #define __UINT64_C_SUFFIX__ ULL +#endif +#ifdef _LP64 +#define __INTMAX_C_SUFFIX__ L +#define __UINTMAX_C_SUFFIX__ UL +#else #define __INTMAX_C_SUFFIX__ LL #define __UINTMAX_C_SUFFIX__ ULL +#endif #endif
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: riastradh Date: Tue Jul 4 01:02:50 UTC 2023 Modified Files: src/sys/arch/riscv/include: int_const.h Log Message: riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types. XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/int_const.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Fri Jun 23 12:11:22 UTC 2023
Modified Files:
src/sys/arch/riscv/include: frame.h
Log Message:
Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe
is created on the stack SP remains 16-byte aligned as per the ABI
requirements.
Patch from Rin with some updates from me.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/frame.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/frame.h
diff -u src/sys/arch/riscv/include/frame.h:1.5 src/sys/arch/riscv/include/frame.h:1.6
--- src/sys/arch/riscv/include/frame.h:1.5 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/frame.h Fri Jun 23 12:11:22 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.5 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: frame.h,v 1.6 2023/06/23 12:11:22 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -39,6 +39,7 @@ struct trapframe {
register_t tf_tval; // supervisor trap value
register_t tf_cause; // supervisor cause register
register_t tf_sr; // supervisor status register
+ register_t tf_pad; // For 16-byte alignment
#define tf_reg tf_regs.r_reg
#define tf_pc tf_regs.r_pc
#define tf_ra tf_reg[_X_RA]
@@ -74,6 +75,12 @@ struct trapframe {
#define tf_t6 tf_reg[_X_T6]
};
+/*
+ * Ensure the trapframe is a multiple of 16bytes so that stack
+ * alignment is preserved.
+ */
+__CTASSERT((sizeof(struct trapframe) & (16 - 1)) == 0);
+
#ifdef _LP64
// For COMPAT_NETBSD32 coredumps
struct trapframe32 {
@@ -81,11 +88,11 @@ struct trapframe32 {
register32_t tf_tval;
register32_t tf_cause;
register32_t tf_sr;
+ register32_t tf_pad;
};
#endif
-
#define lwp_trapframe(l) ((l)->l_md.md_utf)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Jun 23 12:11:22 UTC 2023 Modified Files: src/sys/arch/riscv/include: frame.h Log Message: Pad the trapframe so it's a multiple of 16 bytes so that when a trapframe is created on the stack SP remains 16-byte aligned as per the ABI requirements. Patch from Rin with some updates from me. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/frame.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Thu May 25 06:17:18 UTC 2023 Modified Files: src/sys/arch/riscv/include: cpu.h Log Message: Fix CLKF_INTR so that not all time is shown as being spent in interrupts. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Thu May 25 06:17:18 UTC 2023
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Fix CLKF_INTR so that not all time is shown as being spent in interrupts.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.10 src/sys/arch/riscv/include/cpu.h:1.11
--- src/sys/arch/riscv/include/cpu.h:1.10 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/cpu.h Thu May 25 06:17:18 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.10 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: cpu.h,v 1.11 2023/05/25 06:17:18 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -42,7 +42,7 @@ struct clockframe {
#define CLKF_USERMODE(cf) (((cf)->cf_status & SR_SPP) == 0)
#define CLKF_PC(cf) ((cf)->cf_epc)
-#define CLKF_INTR(cf) ((cf)->cf_intr_depth > 0)
+#define CLKF_INTR(cf) ((cf)->cf_intr_depth > 1)
#include
#include
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 8 20:51:53 UTC 2023 Modified Files: src/sys/arch/riscv/include: proc.h Log Message: Don't expose vaddr_t or register_t to userland. The gdb configure script needs this so it can detect struct lwp correctly. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/proc.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Mon May 8 20:51:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: proc.h
Log Message:
Don't expose vaddr_t or register_t to userland. The gdb configure script
needs this so it can detect struct lwp correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/proc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/proc.h
diff -u src/sys/arch/riscv/include/proc.h:1.4 src/sys/arch/riscv/include/proc.h:1.5
--- src/sys/arch/riscv/include/proc.h:1.4 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/proc.h Mon May 8 20:51:53 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.4 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: proc.h,v 1.5 2023/05/08 20:51:53 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,8 +46,8 @@ struct mdlwp {
struct trapframe *md_utf; /* trapframe from userspace */
struct trapframe *md_ktf; /* trapframe from userspace */
struct faultbuf *md_onfault; /* registers to store on fault */
- register_t md_usp; /* for locore.S */
- vaddr_t md_ss_addr; /* single step address for ptrace */
+ unsigned long md_usp; /* for locore.S */
+ unsigned long md_ss_addr; /* single step address for ptrace */
int md_ss_instr; /* single step instruction for ptrace */
volatile int md_astpending; /* AST pending on return to userland */
#if 0
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 8 08:07:36 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Remove some #if 0'ed code To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 8 08:07:36 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Remove some #if 0'ed code To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.16 src/sys/arch/riscv/include/pmap.h:1.17 --- src/sys/arch/riscv/include/pmap.h:1.16 Mon May 8 07:56:08 2023 +++ src/sys/arch/riscv/include/pmap.h Mon May 8 08:07:36 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.16 2023/05/08 07:56:08 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.17 2023/05/08 08:07:36 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -147,15 +147,9 @@ vsize_t pmap_kenter_range(vaddr_t, paddr #ifdef _LP64 extern vaddr_t pmap_direct_base; extern vaddr_t pmap_direct_end; -#if 0 /* XXXSB is pmap_direct_base not initialised correctly somehow? didn't check */ -#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa)) -#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - pmap_direct_base) -#else #define PMAP_DIRECT_MAP(pa) RISCV_PA_TO_KVA(pa) #define PMAP_DIRECT_UNMAP(va) RISCV_KVA_TO_PA(va) -#endif - /* * Other hooks for the pool allocator. */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 8 07:56:08 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.15 src/sys/arch/riscv/include/pmap.h:1.16 --- src/sys/arch/riscv/include/pmap.h:1.15 Sun May 7 12:41:48 2023 +++ src/sys/arch/riscv/include/pmap.h Mon May 8 07:56:08 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.15 2023/05/07 12:41:48 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.16 2023/05/08 07:56:08 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -140,7 +140,7 @@ void pmap_md_pdetab_init(struct pmap *); void pmap_md_pdetab_fini(struct pmap *); bool pmap_md_ok_to_steal_p(const uvm_physseg_t, size_t); -void pmap_bootstrap(vaddr_t kstart, vaddr_t kend); +void pmap_bootstrap(vaddr_t, vaddr_t); vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 8 07:56:08 UTC 2023 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Apr 22 10:03:53 UTC 2023
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
G/C pte_index
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.11 src/sys/arch/riscv/include/pte.h:1.12
--- src/sys/arch/riscv/include/pte.h:1.11 Sat Nov 12 07:34:18 2022
+++ src/sys/arch/riscv/include/pte.h Sat Apr 22 10:03:53 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.11 2022/11/12 07:34:18 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.12 2023/04/22 10:03:53 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -104,11 +104,6 @@ typedef uint32_t pd_entry_t;
#define pl1_i(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
#define pl0_i(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)
-static inline const size_t
-pte_index(vaddr_t va)
-{
- return ((va >> PGSHIFT) & (NPTEPG - 1));
-}
static inline bool
pte_valid_p(pt_entry_t pte)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Apr 22 10:03:53 UTC 2023 Modified Files: src/sys/arch/riscv/include: pte.h Log Message: G/C pte_index To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Tue Dec 13 22:25:08 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.9 src/sys/arch/riscv/include/reg.h:1.10
--- src/sys/arch/riscv/include/reg.h:1.9 Wed Oct 12 07:50:56 2022
+++ src/sys/arch/riscv/include/reg.h Tue Dec 13 22:25:08 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.9 2022/10/12 07:50:56 simonb Exp $ */
+/* $NetBSD: reg.h,v 1.10 2022/12/13 22:25:08 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@ struct reg32 { // synced with register_t
};
#endif
-#define _XREG(n) ((n)-1)
+#define _XREG(n) ((n) - 1)
#define _X_RA _XREG(1)
#define _X_SP _XREG(2)
#define _X_GP _XREG(3)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Dec 13 22:25:08 UTC 2022 Modified Files: src/sys/arch/riscv/include: reg.h Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Dec 3 11:09:59 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: leading whitespace... oops To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.27 src/sys/arch/riscv/include/sysreg.h:1.28 --- src/sys/arch/riscv/include/sysreg.h:1.27 Fri Nov 18 06:53:06 2022 +++ src/sys/arch/riscv/include/sysreg.h Sat Dec 3 11:09:59 2022 @@ -1,4 +1,4 @@ - /* $NetBSD: sysreg.h,v 1.27 2022/11/18 06:53:06 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.28 2022/12/03 11:09:59 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Dec 3 11:09:59 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: leading whitespace... oops To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Dec 3 08:54:39 UTC 2022 Modified Files: src/sys/arch/riscv/include: elf_machdep.h Log Message: Correct some pre-existing relocations and add some new ones. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/elf_machdep.h diff -u src/sys/arch/riscv/include/elf_machdep.h:1.8 src/sys/arch/riscv/include/elf_machdep.h:1.9 --- src/sys/arch/riscv/include/elf_machdep.h:1.8 Sat Mar 14 16:12:16 2020 +++ src/sys/arch/riscv/include/elf_machdep.h Sat Dec 3 08:54:38 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.8 2020/03/14 16:12:16 skrll Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.9 2022/12/03 08:54:38 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -65,8 +65,8 @@ #define R_RISCV_COPY 4 #define R_RISCV_JMP_SLOT 5 #define R_RISCV_TLS_DTPMOD32 6 -#define R_RISCV_TLS_DTPREL32 7 -#define R_RISCV_TLS_DTPMOD64 8 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 @@ -86,9 +86,9 @@ #define R_RISCV_LO12_I 27 // (A >> 16) & 0x #define R_RISCV_LO12_S 28 // (S + A - P) >> 2 #define R_RISCV_TPREL_HI20 29 -#define R_RISCV_TLREL_LO12_I 30 -#define R_RISCV_TLREL_LO12_S 31 -#define R_RISCV_TLREL_ADD 32 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 #define R_RISCV_ADD8 33 #define R_RISCV_ADD16 34 #define R_RISCV_ADD32 35 @@ -102,6 +102,18 @@ #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 +#define R_RISCV_RVC_LUI 46 +#define R_RISCV_GPREL_I 47 +#define R_RISCV_GPREL_S 48 +#define R_RISCV_TPREL_I 49 +#define R_RISCV_TPREL_S 50 +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 +#define R_RISCV_32_PCREL 57 /* These are aliases we can use R_TYPESZ */ #define R_RISCV_ADDR32 R_RISCV_32
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Dec 3 08:54:39 UTC 2022 Modified Files: src/sys/arch/riscv/include: elf_machdep.h Log Message: Correct some pre-existing relocations and add some new ones. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:16:03 UTC 2022
Modified Files:
src/sys/arch/riscv/include: bus_defs.h bus_funcs.h
Log Message:
Fix some types
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/bus_defs.h \
src/sys/arch/riscv/include/bus_funcs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/bus_defs.h
diff -u src/sys/arch/riscv/include/bus_defs.h:1.1 src/sys/arch/riscv/include/bus_defs.h:1.2
--- src/sys/arch/riscv/include/bus_defs.h:1.1 Sun Sep 11 15:31:12 2022
+++ src/sys/arch/riscv/include/bus_defs.h Sat Nov 19 12:16:03 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_defs.h,v 1.1 2022/09/11 15:31:12 skrll Exp $ */
+/* $NetBSD: bus_defs.h,v 1.2 2022/11/19 12:16:03 skrll Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -339,7 +339,7 @@ typedef struct riscv_bus_dma_segment bus
* This structure describes a valid DMA range.
*/
struct riscv_dma_range {
- bus_addr_t dr_sysbase; /* system base address */
+ paddr_t dr_sysbase; /* system base address */
bus_addr_t dr_busbase; /* appears here on bus */
bus_size_t dr_len; /* length of range */
uint32_t dr_flags; /* flags for range */
Index: src/sys/arch/riscv/include/bus_funcs.h
diff -u src/sys/arch/riscv/include/bus_funcs.h:1.1 src/sys/arch/riscv/include/bus_funcs.h:1.2
--- src/sys/arch/riscv/include/bus_funcs.h:1.1 Sun Sep 11 15:31:12 2022
+++ src/sys/arch/riscv/include/bus_funcs.h Sat Nov 19 12:16:03 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_funcs.h,v 1.1 2022/09/11 15:31:12 skrll Exp $ */
+/* $NetBSD: bus_funcs.h,v 1.2 2022/11/19 12:16:03 skrll Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -720,7 +720,7 @@ paddr_t _bus_dmamem_mmap(bus_dma_tag_t t
int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
bus_size_t alignment, bus_size_t boundary,
bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
- vaddr_t low, vaddr_t high);
+ paddr_t low, paddr_t high);
int _bus_dmatag_subregion(bus_dma_tag_t, bus_addr_t, bus_addr_t,
bus_dma_tag_t *, int);
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Nov 19 12:16:03 UTC 2022 Modified Files: src/sys/arch/riscv/include: bus_defs.h bus_funcs.h Log Message: Fix some types To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/bus_defs.h \ src/sys/arch/riscv/include/bus_funcs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Nov 18 06:53:06 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Fix SR_WPRI. Tweak csr_cycle_read and csr_asid_write for code style, and add some KNF whitespace. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Fri Nov 18 06:53:06 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Fix SR_WPRI. Tweak csr_cycle_read and csr_asid_write for code style, and add some KNF whitespace. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.26 src/sys/arch/riscv/include/sysreg.h:1.27 --- src/sys/arch/riscv/include/sysreg.h:1.26 Thu Nov 17 13:10:42 2022 +++ src/sys/arch/riscv/include/sysreg.h Fri Nov 18 06:53:06 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.26 2022/11/17 13:10:42 simonb Exp $ */ + /* $NetBSD: sysreg.h,v 1.27 2022/11/18 06:53:06 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -39,14 +39,14 @@ #include #define FCSR_FMASK 0 // no exception bits -#define FCSR_FRM __BITS(7,5) +#define FCSR_FRM __BITS(7, 5) #define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even #define FCSR_FRM_RTZ 0b001 // Round Towards Zero #define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) #define FCSR_FRM_RUP 0b011 // Round UP (+infinity) #define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude #define FCSR_FRM_DYN 0b111 // Dynamic rounding -#define FCSR_FFLAGS __BITS(4,0) // Sticky bits +#define FCSR_FFLAGS __BITS(4, 0) // Sticky bits #define FCSR_NV __BIT(4) // iNValid operation #define FCSR_DZ __BIT(3) // Divide by Zero #define FCSR_OF __BIT(2) // OverFlow @@ -163,18 +163,20 @@ RISCVREG_SET_CLEAR_INLINE(regname) /* Supervisor Status Register */ RISCVREG_READ_SET_CLEAR_INLINE(sstatus) // supervisor status register #ifdef _LP64 -#define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \ - __BITS(12,9) | __BITS(7,6) | __BITS(3,2) +#define SR_WPRI __BITS(62, 34) | __BITS(31, 20) | \ + __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ + __BIT(0) #define SR_SD __BIT(63) // any of FS or VS or XS dirty /* Bits 62-34 are WPRI */ -#define SR_UXL __BITS(33,32) // U-mode XLEN +#define SR_UXL __BITS(33, 32) // U-mode XLEN #define SR_UXL_32 1 // XLEN == 32 #define SR_UXL_64 2 // XLEN == 64 #define SR_UXL_128 3 // XLEN == 128 /* Bits 31-20 are WPRI*/ #else -#define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \ - __BITS(7,6) | __BITS(3,2) +#define SR_WPRI __BITS(30, 20) | \ + __BIT(17) | __BITS(12, 11) | __BIT(7) | __BITS(4, 2) | \ + __BIT(0) #define SR_SD __BIT(31) // any of FS or VS or XS dirty /* Bits 30-20 are WPRI*/ #endif /* _LP64 */ @@ -183,18 +185,18 @@ RISCVREG_READ_SET_CLEAR_INLINE(sstatus) #define SR_MXR __BIT(19) // Make eXecutable Readable #define SR_SUM __BIT(18) // permit Supervisor User Memory access /* Bit 17 is WPRI */ -#define SR_XS __BITS(16,15) // Vector extension state +#define SR_XS __BITS(16, 15) // Vector extension state #define SR_XS_OFF 0 // All off #define SR_XS_SOME_ON 1 // None dirty or clean, some on #define SR_XS_SOME_CLEAN 2 // None dirty, some clean #define SR_XS_SOME_DIRTY 3 // Some dirty -#define SR_FS __BITS(14,13) // Floating-point unit state +#define SR_FS __BITS(14, 13) // Floating-point unit state #define SR_FS_OFF 0 // Off #define SR_FS_INITIAL 1 // Initial #define SR_FS_CLEAN 2 // Clean #define SR_FS_DIRTY 3 // Dirty /* Bits 12-11 are WPRI */ -#define SR_VS __BITS(10,9) // User-mode extention state +#define SR_VS __BITS(10, 9) // User-mode extention state #define SR_VS_OFF SR_FS_OFF // Off #define SR_VS_INITIAL SR_FS_INITIAL // Initial #define SR_VS_CLEAN SR_FS_CLEAN // Clean @@ -229,7 +231,7 @@ RISCVREG_READ_SET_CLEAR_INLINE(sie) // /* Bit 0 is WIRI */ /* Mask for all interrupts */ -#define SIE_IM (SIE_SEI|SIE_STIE|SIE_SSIE) /* XXX unused? */ +#define SIE_IM (SIE_SEI |SIE_STIE | SIE_SSIE) #ifdef _LP64 #define SR_USER64 (SR_SPIE | SR_UXL_64) // 64-bit U-mode sstatus @@ -239,8 +241,8 @@ RISCVREG_READ_SET_CLEAR_INLINE(sie) // #endif // Cause register -#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1)) -#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN-2, 0)) +#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN - 1)) +#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN - 2, 0)) // Cause register - exceptions #define CAUSE_FETCH_MISALIGNED 0 @@ -287,12 +289,14 @@ csr_cycle_read(void) [__lo0] "=r"(__lo0), [__hi1] "=r"(__hi1)); } while (__hi0 != __hi1); - return ((uint64_t)__hi0 << 32) | (uint64_t)__lo0; + return + __SHIFTIN(__hi0, __BITS(63, 32)) | + __SHIFTIN(__lo0, __BITS(31, 0)); } #endif /* !_LP64 */ #ifdef _LP64 -#define SATP_MODE __BITS(63,60) // Translation mode +#define SATP_MODE __BITS(63, 60) // Translation mode #define SATP_MODE_BARE 0 // No translation or protection
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Thu Nov 17 13:10:43 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Document lots of bits. Remove bits no longer in the RISC-V supervisor spec. Update defines for the user-mode sstatus value. To generate a diff of this commit: cvs rdiff -u -r1.25 -r1.26 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.25 src/sys/arch/riscv/include/sysreg.h:1.26 --- src/sys/arch/riscv/include/sysreg.h:1.25 Tue Nov 15 14:33:33 2022 +++ src/sys/arch/riscv/include/sysreg.h Thu Nov 17 13:10:42 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.25 2022/11/15 14:33:33 simonb Exp $ */ +/* $NetBSD: sysreg.h,v 1.26 2022/11/17 13:10:42 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -165,75 +165,77 @@ RISCVREG_READ_SET_CLEAR_INLINE(sstatus) #ifdef _LP64 #define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \ __BITS(12,9) | __BITS(7,6) | __BITS(3,2) -#define SR_SD __BIT(63) +#define SR_SD __BIT(63) // any of FS or VS or XS dirty /* Bits 62-34 are WPRI */ -#define SR_UXL __BITS(33,32) -#define SR_UXL_32 1 -#define SR_UXL_64 2 -#define SR_UXL_128 3 +#define SR_UXL __BITS(33,32) // U-mode XLEN +#define SR_UXL_32 1 // XLEN == 32 +#define SR_UXL_64 2 // XLEN == 64 +#define SR_UXL_128 3 // XLEN == 128 /* Bits 31-20 are WPRI*/ #else #define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \ __BITS(7,6) | __BITS(3,2) -#define SR_SD __BIT(31) +#define SR_SD __BIT(31) // any of FS or VS or XS dirty /* Bits 30-20 are WPRI*/ #endif /* _LP64 */ /* Both RV32 and RV64 have the bottom 20 bits shared */ -#define SR_MXR __BIT(19) -#define SR_SUM __BIT(18) +#define SR_MXR __BIT(19) // Make eXecutable Readable +#define SR_SUM __BIT(18) // permit Supervisor User Memory access /* Bit 17 is WPRI */ -#define SR_XS __BITS(16,15) -#define SR_FS __BITS(14,13) -#define SR_FS_OFF 0 -#define SR_FS_INITIAL 1 -#define SR_FS_CLEAN 2 -#define SR_FS_DIRTY 3 - - /* Bits 12-9 are WPRI */ -#define SR_SPP __BIT(8) - /* Bits 7-6 are WPRI */ -#define SR_SPIE __BIT(5) -#define SR_UPIE __BIT(4) - /* Bits 3-2 are WPRI */ -#define SR_SIE __BIT(1) -#define SR_UIE __BIT(0) +#define SR_XS __BITS(16,15) // Vector extension state +#define SR_XS_OFF 0 // All off +#define SR_XS_SOME_ON 1 // None dirty or clean, some on +#define SR_XS_SOME_CLEAN 2 // None dirty, some clean +#define SR_XS_SOME_DIRTY 3 // Some dirty +#define SR_FS __BITS(14,13) // Floating-point unit state +#define SR_FS_OFF 0 // Off +#define SR_FS_INITIAL 1 // Initial +#define SR_FS_CLEAN 2 // Clean +#define SR_FS_DIRTY 3 // Dirty + /* Bits 12-11 are WPRI */ +#define SR_VS __BITS(10,9) // User-mode extention state +#define SR_VS_OFF SR_FS_OFF // Off +#define SR_VS_INITIAL SR_FS_INITIAL // Initial +#define SR_VS_CLEAN SR_FS_CLEAN // Clean +#define SR_VS_DIRTY SR_FS_DIRTY // Dirty +#define SR_SPP __BIT(8) // Priv level before supervisor mode + /* Bit 7 is WPRI */ +#define SR_UBE __BIT(6) // User-mode endianness +#define SR_SPIE __BIT(5) // S-Mode interrupts enabled before trap + /* Bits 4-2 are WPRI */ +#define SR_SIE __BIT(1) // Supervisor mode interrupt enable + /* Bit 0 is WPRI */ /* Supervisor interrupt registers */ /* ... interrupt pending register (sip) */ RISCVREG_READ_SET_CLEAR_INLINE(sip) // supervisor interrupt pending /* Bit (XLEN-1) - 10 is WIRI */ -#define SIP_SEIP __BIT(9) -#define SIP_UEIP __BIT(8) - /* Bit 7-6 is WIRI */ -#define SIP_STIP __BIT(5) -#define SIP_UTIP __BIT(4) - /* Bit 3-2 is WIRI */ -#define SIP_SSIP __BIT(1) -#define SIP_USIP __BIT(0) +#define SIP_SEIP __BIT(9) // S-mode interrupt pending + /* Bit 8-6 is WIRI */ +#define SIP_STIP __BIT(5) // S-mode timer interrupt pending + /* Bit 4-2 is WIRI */ +#define SIP_SSIP __BIT(1) // S-mode software interrupt pending + /* Bit 0 is WIRI */ /* ... interrupt-enable register (sie) */ RISCVREG_READ_SET_CLEAR_INLINE(sie) // supervisor interrupt enable /* Bit (XLEN-1) - 10 is WIRI */ -#define SIE_SEIE __BIT(9) -#define SIE_UEIE __BIT(8) - /* Bit 7-6 is WIRI */ -#define SIE_STIE __BIT(5) -#define SIE_UTIE __BIT(4) - /* Bit 3-2 is WIRI */ -#define SIE_SSIE __BIT(1) -#define SIE_USIE __BIT(0) +#define SIE_SEIE __BIT(9) // S-mode interrupt enable + /* Bit 8-6 is WIRI */ +#define SIE_STIE __BIT(5) // S-mode timer interrupt enable + /* Bit 4-2 is WIRI */ +#define SIE_SSIE __BIT(1) // S-mode software interrupt enable + /* Bit 0 is WIRI */ /* Mask for all interrupts */ -#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE) +#define SIE_IM (SIE_SEI|SIE_STIE|SIE_SSIE) /* XXX unused? */ #ifdef _LP64 -#define SR_USER (SR_UIE)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Thu Nov 17 13:10:43 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Document lots of bits. Remove bits no longer in the RISC-V supervisor spec. Update defines for the user-mode sstatus value. To generate a diff of this commit: cvs rdiff -u -r1.25 -r1.26 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: simonb
Date: Thu Nov 17 09:50:23 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Use better types and struct member names in the clockframe.
Avoid a magic number in CLKF_USERMODE().
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.8 src/sys/arch/riscv/include/cpu.h:1.9
--- src/sys/arch/riscv/include/cpu.h:1.8 Sat Aug 14 17:51:19 2021
+++ src/sys/arch/riscv/include/cpu.h Thu Nov 17 09:50:23 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.8 2021/08/14 17:51:19 ryo Exp $ */
+/* $NetBSD: cpu.h,v 1.9 2022/11/17 09:50:23 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,13 +35,13 @@
#if defined(_KERNEL) || defined(_KMEMUSER)
struct clockframe {
- uintptr_t cf_pc;
- uint32_t cf_sr;
+ vaddr_t cf_epc;
+ register_t cf_status;
int cf_intr_depth;
};
-#define CLKF_USERMODE(cf) (((cf)->cf_sr & 1) == 0)
-#define CLKF_PC(cf) ((cf)->cf_pc)
+#define CLKF_USERMODE(cf) (((cf)->cf_status & SR_SPP) == 0)
+#define CLKF_PC(cf) ((cf)->cf_epc)
#define CLKF_INTR(cf) ((cf)->cf_intr_depth > 0)
#include
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Thu Nov 17 09:50:23 UTC 2022 Modified Files: src/sys/arch/riscv/include: cpu.h Log Message: Use better types and struct member names in the clockframe. Avoid a magic number in CLKF_USERMODE(). To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sun Nov 13 08:13:55 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Comment fix To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.23 src/sys/arch/riscv/include/sysreg.h:1.24 --- src/sys/arch/riscv/include/sysreg.h:1.23 Sat Nov 12 07:05:40 2022 +++ src/sys/arch/riscv/include/sysreg.h Sun Nov 13 08:13:55 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.23 2022/11/12 07:05:40 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.24 2022/11/13 08:13:55 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -233,7 +233,7 @@ riscvreg_status_set(uintptr_t __mask) #define CAUSE_STORE_PAGE_FAULT 15 /* >= 16 is reserved/custom */ -// Cause register - traps +// Cause register - interrupts #define IRQ_SUPERVISOR_SOFTWARE 1 #define IRQ_MACHINE_SOFTWARE 3 #define IRQ_SUPERVISOR_TIMER 5
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sun Nov 13 08:13:55 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Comment fix To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Note some SV39 PTE bits defined in extensions.
Fix pte_nv_entry for the kernel.
Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.10 src/sys/arch/riscv/include/pte.h:1.11
--- src/sys/arch/riscv/include/pte.h:1.10 Tue Oct 18 06:44:43 2022
+++ src/sys/arch/riscv/include/pte.h Sat Nov 12 07:34:18 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.10 2022/10/18 06:44:43 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.11 2022/11/12 07:34:18 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -56,8 +56,14 @@ typedef uint32_t pd_entry_t;
#define NSEGPG NPTEPG
#define NPDEPG NPTEPG
+
+/* HardWare PTE bits SV39 */
+#define PTE_N __BIT(63) // Svnapot
+#define PTE_PBMT __BITS(62, 61) // Svpbmt
+#define PTE_reserved0 __BITS(60, 54) //
+
/* Software PTE bits. */
-#define PTE_RSW __BITS(9,8)
+#define PTE_RSW __BITS(9, 8)
#define PTE_WIRED __BIT(9)
/* Hardware PTE bits. */
@@ -155,7 +161,7 @@ pte_to_paddr(pt_entry_t pte)
static inline pt_entry_t
pte_nv_entry(bool kernel_p)
{
- return kernel_p ? PTE_G : 0;
+ return 0;
}
static inline pt_entry_t
@@ -265,7 +271,7 @@ pte_pde_pdetab(paddr_t pa, bool kernel_p
static inline pd_entry_t
pte_pde_ptpage(paddr_t pa, bool kernel_p)
{
- return PTE_V | PTE_X | PTE_W | PTE_R | (pa >> PAGE_SHIFT) << PTE_PPN_SHIFT;
+ return PTE_V | (pa >> PAGE_SHIFT) << PTE_PPN_SHIFT;
}
static inline bool
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:34:18 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Note some SV39 PTE bits defined in extensions.
Fix pte_nv_entry for the kernel.
Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 12 07:05:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Use uintptr_t consistently rather than register_t
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.22 src/sys/arch/riscv/include/sysreg.h:1.23
--- src/sys/arch/riscv/include/sysreg.h:1.22 Fri Nov 11 01:18:32 2022
+++ src/sys/arch/riscv/include/sysreg.h Sat Nov 12 07:05:40 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.22 2022/11/11 01:18:32 simonb Exp $ */
+/* $NetBSD: sysreg.h,v 1.23 2022/11/12 07:05:40 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -177,18 +177,18 @@ riscvreg_fcsr_write_frm(uint32_t __new)
#define SR_KERNEL (SR_SIE | SR_UIE)
#endif
-static inline register_t
+static inline uintptr_t
riscvreg_status_read(void)
{
- register_t __sr;
+ uintptr_t __sr;
__asm("csrr\t%0, sstatus" : "=r"(__sr));
return __sr;
}
-static inline register_t
-riscvreg_status_clear(register_t __mask)
+static inline uintptr_t
+riscvreg_status_clear(uintptr_t __mask)
{
- register_t __sr;
+ uintptr_t __sr;
if (__builtin_constant_p(__mask) && __mask < 0x20) {
__asm("csrrci\t%0, sstatus, %1" : "=r"(__sr) : "i"(__mask));
} else {
@@ -197,10 +197,10 @@ riscvreg_status_clear(register_t __mask)
return __sr;
}
-static inline register_t
-riscvreg_status_set(register_t __mask)
+static inline uintptr_t
+riscvreg_status_set(uintptr_t __mask)
{
- register_t __sr;
+ uintptr_t __sr;
if (__builtin_constant_p(__mask) && __mask < 0x20) {
__asm("csrrsi\t%0, sstatus, %1" : "=r"(__sr) : "i"(__mask));
} else {
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Nov 12 07:05:41 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Use uintptr_t consistently rather than register_t To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: simonb
Date: Fri Nov 11 01:18:32 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
The supervisor status register is the native word width, not fixed
at 32 bits.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.21 src/sys/arch/riscv/include/sysreg.h:1.22
--- src/sys/arch/riscv/include/sysreg.h:1.21 Tue Nov 8 13:47:09 2022
+++ src/sys/arch/riscv/include/sysreg.h Fri Nov 11 01:18:32 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.21 2022/11/08 13:47:09 simonb Exp $ */
+/* $NetBSD: sysreg.h,v 1.22 2022/11/11 01:18:32 simonb Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -177,18 +177,18 @@ riscvreg_fcsr_write_frm(uint32_t __new)
#define SR_KERNEL (SR_SIE | SR_UIE)
#endif
-static inline uint32_t
+static inline register_t
riscvreg_status_read(void)
{
- uint32_t __sr;
+ register_t __sr;
__asm("csrr\t%0, sstatus" : "=r"(__sr));
return __sr;
}
-static inline uint32_t
-riscvreg_status_clear(uint32_t __mask)
+static inline register_t
+riscvreg_status_clear(register_t __mask)
{
- uint32_t __sr;
+ register_t __sr;
if (__builtin_constant_p(__mask) && __mask < 0x20) {
__asm("csrrci\t%0, sstatus, %1" : "=r"(__sr) : "i"(__mask));
} else {
@@ -197,10 +197,10 @@ riscvreg_status_clear(uint32_t __mask)
return __sr;
}
-static inline uint32_t
-riscvreg_status_set(uint32_t __mask)
+static inline register_t
+riscvreg_status_set(register_t __mask)
{
- uint32_t __sr;
+ register_t __sr;
if (__builtin_constant_p(__mask) && __mask < 0x20) {
__asm("csrrsi\t%0, sstatus, %1" : "=r"(__sr) : "i"(__mask));
} else {
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Fri Nov 11 01:18:32 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: The supervisor status register is the native word width, not fixed at 32 bits. To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:47:09 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Parentheses police. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.20 src/sys/arch/riscv/include/sysreg.h:1.21 --- src/sys/arch/riscv/include/sysreg.h:1.20 Tue Nov 8 13:35:32 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 13:47:09 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.20 2022/11/08 13:35:32 simonb Exp $ */ +/* $NetBSD: sysreg.h,v 1.21 2022/11/08 13:47:09 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -210,8 +210,8 @@ riscvreg_status_set(uint32_t __mask) } // Cause register -#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1))) -#define CAUSE_CODE(cause) ((cause) & __BITS((XLEN-2), 0)) +#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1)) +#define CAUSE_CODE(cause) ((cause) & __BITS(XLEN-2, 0)) // Cause register - exceptions #define CAUSE_FETCH_MISALIGNED 0
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:47:09 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Parentheses police. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:35:32 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add cause register trap types, and some macros to access cause register fields. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:35:32 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add cause register trap types, and some macros to access cause register fields. To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.19 src/sys/arch/riscv/include/sysreg.h:1.20 --- src/sys/arch/riscv/include/sysreg.h:1.19 Tue Nov 8 12:48:28 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 13:35:32 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.19 2022/11/08 12:48:28 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.20 2022/11/08 13:35:32 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -210,6 +210,10 @@ riscvreg_status_set(uint32_t __mask) } // Cause register +#define CAUSE_INTERRUPT_P(cause) ((cause) & __BIT(XLEN-1))) +#define CAUSE_CODE(cause) ((cause) & __BITS((XLEN-2), 0)) + +// Cause register - exceptions #define CAUSE_FETCH_MISALIGNED 0 #define CAUSE_FETCH_ACCESS 1 #define CAUSE_ILLEGAL_INSTRUCTION 2 @@ -218,8 +222,8 @@ riscvreg_status_set(uint32_t __mask) #define CAUSE_LOAD_ACCESS 5 #define CAUSE_STORE_MISALIGNED 6 #define CAUSE_STORE_ACCESS 7 -#define CAUSE_SYSCALL 8 #define CAUSE_USER_ECALL 8 +#define CAUSE_SYSCALL CAUSE_USER_ECALL /* convenience alias */ #define CAUSE_SUPERVISOR_ECALL 9 /* 10 is reserved */ #define CAUSE_MACHINE_ECALL 11 @@ -227,7 +231,15 @@ riscvreg_status_set(uint32_t __mask) #define CAUSE_LOAD_PAGE_FAULT 13 /* 14 is Reserved */ #define CAUSE_STORE_PAGE_FAULT 15 -/* >= 16 is reserved */ +/* >= 16 is reserved/custom */ + +// Cause register - traps +#define IRQ_SUPERVISOR_SOFTWARE 1 +#define IRQ_MACHINE_SOFTWARE 3 +#define IRQ_SUPERVISOR_TIMER 5 +#define IRQ_MACHINE_TIMER 7 +#define IRQ_SUPERVISOR_EXTERNAL 9 +#define IRQ_MACHINE_EXTERNAL 11 static inline uint64_t riscvreg_cycle_read(void)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:34:18 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Add a #define for XLEN, the RISC-V native base integer ISA width. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/types.h diff -u src/sys/arch/riscv/include/types.h:1.14 src/sys/arch/riscv/include/types.h:1.15 --- src/sys/arch/riscv/include/types.h:1.14 Tue Oct 18 07:07:51 2022 +++ src/sys/arch/riscv/include/types.h Tue Nov 8 13:34:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.14 2022/10/18 07:07:51 skrll Exp $ */ +/* $NetBSD: types.h,v 1.15 2022/11/08 13:34:17 simonb Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -38,6 +38,9 @@ #if defined(_KERNEL) || defined(_KMEMUSER) || defined(_KERNTYPES) || defined(_STANDALONE) +/* XLEN is the native base integer ISA width */ +#define XLEN (sizeof(long) * NBBY) + typedef __uint64_t paddr_t; typedef __uint64_t psize_t; #define PRIxPADDR PRIx64
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Tue Nov 8 13:34:18 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Add a #define for XLEN, the RISC-V native base integer ISA width. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Nov 8 12:48:28 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: whitepsace nit To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.18 src/sys/arch/riscv/include/sysreg.h:1.19 --- src/sys/arch/riscv/include/sysreg.h:1.18 Sat Oct 15 06:53:49 2022 +++ src/sys/arch/riscv/include/sysreg.h Tue Nov 8 12:48:28 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.18 2022/10/15 06:53:49 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.19 2022/11/08 12:48:28 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -144,7 +144,7 @@ riscvreg_fcsr_write_frm(uint32_t __new) /* Supervisor interrupt registers */ /* ... interrupt pending register (sip) */ - /* Bit (XLEN-1)-10 is WIRI */ + /* Bit (XLEN-1) - 10 is WIRI */ #define SIP_SEIP __BIT(9) #define SIP_UEIP __BIT(8) /* Bit 7-6 is WIRI */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Nov 8 12:48:28 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: whitepsace nit To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Thu Oct 20 07:18:11 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Add the "memory" clobber in two places that it's needed.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.12 src/sys/arch/riscv/include/pmap.h:1.13
--- src/sys/arch/riscv/include/pmap.h:1.12 Tue Oct 18 04:39:38 2022
+++ src/sys/arch/riscv/include/pmap.h Thu Oct 20 07:18:11 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.12 2022/10/18 04:39:38 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.13 2022/10/20 07:18:11 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -104,7 +104,7 @@
static inline void
pmap_procwr(struct proc *p, vaddr_t va, vsize_t len)
{
- __asm __volatile("fence\trw,rw; fence.i");
+ __asm __volatile("fence\trw,rw; fence.i" ::: "memory");
}
#include
@@ -158,7 +158,7 @@ pmap_md_tlb_check_entry(void *ctx, vaddr
static inline void
pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *kc)
{
- __asm __volatile("fence\trw,rw; fence.i");
+ __asm __volatile("fence\trw,rw; fence.i" ::: "memory");
}
/*
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Thu Oct 20 07:18:11 UTC 2022 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Add the "memory" clobber in two places that it's needed. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Oct 18 07:07:51 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big enough. Spotted by Simon. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/types.h diff -u src/sys/arch/riscv/include/types.h:1.13 src/sys/arch/riscv/include/types.h:1.14 --- src/sys/arch/riscv/include/types.h:1.13 Sun Sep 11 15:31:12 2022 +++ src/sys/arch/riscv/include/types.h Tue Oct 18 07:07:51 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.13 2022/09/11 15:31:12 skrll Exp $ */ +/* $NetBSD: types.h,v 1.14 2022/10/18 07:07:51 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -63,7 +63,7 @@ typedef signed int register32_t; typedef unsigned int uregister32_t; #define PRIxREGISTER32 "x" -typedef unsigned short tlb_asid_t; +typedef unsigned int tlb_asid_t; #endif #if defined(_KERNEL)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Oct 18 07:07:51 UTC 2022 Modified Files: src/sys/arch/riscv/include: types.h Log Message: VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be big enough. Spotted by Simon. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Tue Oct 18 06:44:43 UTC 2022
Modified Files:
src/sys/arch/riscv/include: pte.h
Log Message:
Some fixes from Simon.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.9 src/sys/arch/riscv/include/pte.h:1.10
--- src/sys/arch/riscv/include/pte.h:1.9 Sat Oct 15 06:41:43 2022
+++ src/sys/arch/riscv/include/pte.h Tue Oct 18 06:44:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.9 2022/10/15 06:41:43 simonb Exp $ */
+/* $NetBSD: pte.h,v 1.10 2022/10/18 06:44:43 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -259,19 +259,19 @@ pte_invalid_pde(void)
static inline pd_entry_t
pte_pde_pdetab(paddr_t pa, bool kernel_p)
{
- return PTE_V | (pa >> PAGE_SHIFT) << L2_SHIFT;
+ return PTE_V | (pa >> PAGE_SHIFT) << PTE_PPN_SHIFT;
}
static inline pd_entry_t
pte_pde_ptpage(paddr_t pa, bool kernel_p)
{
- return PTE_V | PTE_X | PTE_W | PTE_R | (pa >> PAGE_SHIFT) << L2_SHIFT;
+ return PTE_V | PTE_X | PTE_W | PTE_R | (pa >> PAGE_SHIFT) << PTE_PPN_SHIFT;
}
static inline bool
pte_pde_valid_p(pd_entry_t pde)
{
- return (pde & (PTE_X | PTE_W | PTE_R)) == 0;
+ return (pde & (PTE_X | PTE_W | PTE_R | PTE_V)) == PTE_V;
}
static inline paddr_t
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Oct 18 06:44:43 UTC 2022 Modified Files: src/sys/arch/riscv/include: pte.h Log Message: Some fixes from Simon. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Oct 18 04:39:38 UTC 2022 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Correct XSEGSHIFT for RV32 case To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.11 src/sys/arch/riscv/include/pmap.h:1.12 --- src/sys/arch/riscv/include/pmap.h:1.11 Sat Oct 15 06:41:43 2022 +++ src/sys/arch/riscv/include/pmap.h Tue Oct 18 04:39:38 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.11 2022/10/15 06:41:43 simonb Exp $ */ +/* $NetBSD: pmap.h,v 1.12 2022/10/18 04:39:38 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -66,7 +66,7 @@ #define NXSEGPG (1 << XSEGLENGTH) #else #define PTPSHIFT 2 -#define XSEGSHIFT SEGLENGTH +#define XSEGSHIFT SEGSHIFT #endif #define SEGLENGTH (PGSHIFT - PTPSHIFT)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue Oct 18 04:39:38 UTC 2022 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: Correct XSEGSHIFT for RV32 case To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Oct 15 06:53:49 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Fix typo in SATP_MODE_SV64 To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.17 src/sys/arch/riscv/include/sysreg.h:1.18 --- src/sys/arch/riscv/include/sysreg.h:1.17 Sat Oct 15 06:52:35 2022 +++ src/sys/arch/riscv/include/sysreg.h Sat Oct 15 06:53:49 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.17 2022/10/15 06:52:35 simonb Exp $ */ +/* $NetBSD: sysreg.h,v 1.18 2022/10/15 06:53:49 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -257,7 +257,7 @@ riscvreg_cycle_read(void) #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 #define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 10 +#define SATP_MODE_SV64 11 #define SATP_ASID __BITS(59,44) #define SATP_PPN __BITS(43,0) #else
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Oct 15 06:53:49 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Fix typo in SATP_MODE_SV64 To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Sat Oct 15 06:52:35 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Consistency nit: use "__volatile" instead of "volatile" with asm()s. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:52:35 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Consistency nit: use "__volatile" instead of "volatile" with asm()s.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.16 src/sys/arch/riscv/include/sysreg.h:1.17
--- src/sys/arch/riscv/include/sysreg.h:1.16 Sat Oct 15 06:48:31 2022
+++ src/sys/arch/riscv/include/sysreg.h Sat Oct 15 06:52:35 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.16 2022/10/15 06:48:31 simonb Exp $ */
+/* $NetBSD: sysreg.h,v 1.17 2022/10/15 06:52:35 simonb Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -100,7 +100,7 @@ riscvreg_fcsr_write_frm(uint32_t __new)
{
uint32_t __old;
__new = __SHIFTIN(__new, FCSR_FRM);
- __asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new));
+ __asm __volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new));
return __SHIFTOUT(__old, FCSR_FRM);
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Sat Oct 15 06:48:31 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add SATP modes for bare, SV57 and SV64. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.15 src/sys/arch/riscv/include/sysreg.h:1.16 --- src/sys/arch/riscv/include/sysreg.h:1.15 Sat Oct 15 06:41:43 2022 +++ src/sys/arch/riscv/include/sysreg.h Sat Oct 15 06:48:31 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.15 2022/10/15 06:41:43 simonb Exp $ */ +/* $NetBSD: sysreg.h,v 1.16 2022/10/15 06:48:31 simonb Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -253,12 +253,16 @@ riscvreg_cycle_read(void) #ifdef _LP64 #define SATP_MODE __BITS(63,60) +#define SATP_MODE_BARE 0 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 10 #define SATP_ASID __BITS(59,44) #define SATP_PPN __BITS(43,0) #else #define SATP_MODE __BIT(31) +#define SATP_MODE_BARE 0 #define SATP_MODE_SV32 1 #define SATP_ASID __BITS(30,22) #define SATP_PPN __BITS(21,0)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Sat Oct 15 06:48:31 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add SATP modes for bare, SV57 and SV64. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: simonb
Date: Sat Oct 15 06:46:41 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu_counter.h
Log Message:
Use __volatile so the compiler doesn't optimise out successive calls
to cpu_counter().
Add a 64-bit cycle counter on _LP64.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/cpu_counter.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu_counter.h
diff -u src/sys/arch/riscv/include/cpu_counter.h:1.2 src/sys/arch/riscv/include/cpu_counter.h:1.3
--- src/sys/arch/riscv/include/cpu_counter.h:1.2 Sat Oct 15 06:41:43 2022
+++ src/sys/arch/riscv/include/cpu_counter.h Sat Oct 15 06:46:41 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_counter.h,v 1.2 2022/10/15 06:41:43 simonb Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.3 2022/10/15 06:46:41 simonb Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -25,7 +25,7 @@
* SUCH DAMAGE.
*/
-/* $NetBSD: cpu_counter.h,v 1.2 2022/10/15 06:41:43 simonb Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.3 2022/10/15 06:46:41 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -67,13 +67,28 @@
#ifdef _KERNEL
#define cpu_hascounter() true
+
+#ifdef _LP64
+static __inline uint64_t
+cpu_counter(void)
+{
+ uint64_t __count;
+
+ __asm __volatile("csrr\t%0, cycle" : "=r"(__count));
+ return __count;
+}
+
+
+#else /* 32-bit */
#define cpu_counter() cpu_counter32()
+#endif /* 32-bit */
static __inline uint32_t
cpu_counter32(void)
{
uint32_t __count;
- __asm("csrr\t%0, cycle" : "=r"(__count));
+
+ __asm __volatile("csrr\t%0, cycle" : "=r"(__count));
return __count;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Sat Oct 15 06:46:41 UTC 2022 Modified Files: src/sys/arch/riscv/include: cpu_counter.h Log Message: Use __volatile so the compiler doesn't optimise out successive calls to cpu_counter(). Add a 64-bit cycle counter on _LP64. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/cpu_counter.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Oct 15 06:07:04 UTC 2022 Modified Files: src/sys/arch/riscv/include: vmparam.h Log Message: Update a comment To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Oct 15 06:07:04 UTC 2022 Modified Files: src/sys/arch/riscv/include: vmparam.h Log Message: Update a comment To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/vmparam.h diff -u src/sys/arch/riscv/include/vmparam.h:1.11 src/sys/arch/riscv/include/vmparam.h:1.12 --- src/sys/arch/riscv/include/vmparam.h:1.11 Wed Oct 12 07:53:15 2022 +++ src/sys/arch/riscv/include/vmparam.h Sat Oct 15 06:07:04 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.11 2022/10/12 07:53:15 simonb Exp $ */ +/* $NetBSD: vmparam.h,v 1.12 2022/10/15 06:07:04 skrll Exp $ */ /*- * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. @@ -108,7 +108,7 @@ * User/kernel map constants. */ #define VM_MIN_ADDRESS ((vaddr_t)0x) -#ifdef _LP64 /* Sv39 */ +#ifdef _LP64 /* Sv39 / Sv48 / Sv57 */ /* * kernel virtual space layout: * 0x_ffc0__ - 64GiB KERNEL VM Space (inc. text/data/bss)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Wed Oct 12 07:53:15 UTC 2022 Modified Files: src/sys/arch/riscv/include: vmparam.h Log Message: Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0 for a 64bit constant. Bump VM_PHYSSEG_MAX from 1 to 16. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/vmparam.h diff -u src/sys/arch/riscv/include/vmparam.h:1.10 src/sys/arch/riscv/include/vmparam.h:1.11 --- src/sys/arch/riscv/include/vmparam.h:1.10 Tue Sep 20 07:18:23 2022 +++ src/sys/arch/riscv/include/vmparam.h Wed Oct 12 07:53:15 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.10 2022/09/20 07:18:23 skrll Exp $ */ +/* $NetBSD: vmparam.h,v 1.11 2022/10/12 07:53:15 simonb Exp $ */ /*- * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc. @@ -142,10 +142,10 @@ #ifdef _LP64 /* * Since we have the address space, we map all of physical memory (RAM) - * using block page table entries. + * using gigapages on SV39, terapages on SV48 and petapages on SV57. */ #define RISCV_DIRECTMAP_MASK ((vaddr_t) 0xffe0L) -#define RISCV_DIRECTMAP_SIZE (-RISCV_DIRECTMAP_MASK) /* 128GiB */ +#define RISCV_DIRECTMAP_SIZE (-RISCV_DIRECTMAP_MASK - PAGE_SIZE) /* 128GiB */ #define RISCV_DIRECTMAP_START RISCV_DIRECTMAP_MASK #define RISCV_DIRECTMAP_END (RISCV_DIRECTMAP_START + RISCV_DIRECTMAP_SIZE) #define RISCV_KVA_P(va) (((vaddr_t) (va) & RISCV_DIRECTMAP_MASK) != 0) @@ -173,7 +173,7 @@ /* VM_PHYSSEG_MAX defined by platform-dependent code. */ #ifndef VM_PHYSSEG_MAX -#define VM_PHYSSEG_MAX 1 +#define VM_PHYSSEG_MAX 16 #endif #if VM_PHYSSEG_MAX == 1 #define VM_PHYSSEG_STRAT VM_PSTRAT_BIGFIRST
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Wed Oct 12 07:53:15 UTC 2022 Modified Files: src/sys/arch/riscv/include: vmparam.h Log Message: Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0 for a 64bit constant. Bump VM_PHYSSEG_MAX from 1 to 16. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Wed Oct 12 07:50:57 UTC 2022 Modified Files: src/sys/arch/riscv/include: reg.h Log Message: Fix a tyop regname in a comment. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: simonb
Date: Wed Oct 12 07:50:57 UTC 2022
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Fix a tyop regname in a comment.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.8 src/sys/arch/riscv/include/reg.h:1.9
--- src/sys/arch/riscv/include/reg.h:1.8 Sat Nov 7 10:48:17 2020
+++ src/sys/arch/riscv/include/reg.h Wed Oct 12 07:50:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.8 2020/11/07 10:48:17 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.9 2022/10/12 07:50:56 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@
// x10 - x11 = a0 - a1 (arguments/return values) Caller
// x12 - x17 = a2 - a7 (arguments) Caller
// x18 - x27 = s2 - s11 (saved registers) Callee
-// x28 - x31 = t3 - r6 (temporaries) Caller
+// x28 - x31 = t3 - t6 (temporaries) Caller
struct reg { // synced with register_t in
#ifdef _LP64
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Wed Oct 12 07:50:00 UTC 2022 Modified Files: src/sys/arch/riscv/include: param.h Log Message: NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name). Also set NKMEMPAGES_MAX_UNLIMITED while we're here. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/param.h diff -u src/sys/arch/riscv/include/param.h:1.6 src/sys/arch/riscv/include/param.h:1.7 --- src/sys/arch/riscv/include/param.h:1.6 Mon Jul 19 10:28:58 2021 +++ src/sys/arch/riscv/include/param.h Wed Oct 12 07:50:00 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.6 2021/07/19 10:28:58 christos Exp $ */ +/* $NetBSD: param.h,v 1.7 2022/10/12 07:50:00 simonb Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -67,8 +67,8 @@ #define STACK_ALIGNBYTES (__BIGGEST_ALIGNMENT__ - 1) #define ALIGNBYTES32 __BIGGEST_ALIGNMENT__ -#define NKMEMPAGES_MAX_DEFAULT (2048UL * 1024 * 1024) -#define NKMEMPAGES_MIN_DEFAULT (128UL * 1024 * 1024) +#define NKMEMPAGES_MIN_DEFAULT ((128UL * 1024 * 1024) >> PAGE_SHIFT) +#define NKMEMPAGES_MAX_UNLIMITED 1 #define PGSHIFT 12 #define NBPG (1 << PGSHIFT)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: simonb Date: Wed Oct 12 07:50:00 UTC 2022 Modified Files: src/sys/arch/riscv/include: param.h Log Message: NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name). Also set NKMEMPAGES_MAX_UNLIMITED while we're here. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Wed Sep 21 06:34:30 UTC 2022 Modified Files: src/sys/arch/riscv/include: pte.h Log Message: Use c99 types. NFC. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pte.h diff -u src/sys/arch/riscv/include/pte.h:1.6 src/sys/arch/riscv/include/pte.h:1.7 --- src/sys/arch/riscv/include/pte.h:1.6 Sat May 1 07:41:24 2021 +++ src/sys/arch/riscv/include/pte.h Wed Sep 21 06:34:30 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.6 2021/05/01 07:41:24 skrll Exp $ */ +/* $NetBSD: pte.h,v 1.7 2022/09/21 06:34:30 skrll Exp $ */ /* * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc. @@ -38,15 +38,15 @@ #define PTE_PPN0 __BITS(18, 10) #define PTE_PPN1 __BITS(27, 19) #define PTE_PPN2 __BITS(53, 28) -typedef __uint64_t pt_entry_t; -typedef __uint64_t pd_entry_t; +typedef uint64_t pt_entry_t; +typedef uint64_t pd_entry_t; #define atomic_cas_pte atomic_cas_64 #else /* Sv32 */ #define PTE_PPN __BITS(31, 10) #define PTE_PPN0 __BITS(19, 10) #define PTE_PPN1 __BITS(31, 20) -typedef __uint32_t pt_entry_t; -typedef __uint32_t pd_entry_t; +typedef uint32_t pt_entry_t; +typedef uint32_t pd_entry_t; #define atomic_cas_pte atomic_cas_32 #endif
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Wed Sep 21 06:34:30 UTC 2022 Modified Files: src/sys/arch/riscv/include: pte.h Log Message: Use c99 types. NFC. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Sep 10 09:28:26 UTC 2022
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Remove unnecessary cast.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.13 src/sys/arch/riscv/include/sysreg.h:1.14
--- src/sys/arch/riscv/include/sysreg.h:1.13 Sat May 1 07:09:55 2021
+++ src/sys/arch/riscv/include/sysreg.h Sat Sep 10 09:28:26 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.13 2021/05/01 07:09:55 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.14 2022/09/10 09:28:26 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -292,7 +292,7 @@ riscvreg_asid_write(uint32_t asid)
uintptr_t satp;
__asm __volatile("csrr %0, satp" : "=r" (satp));
satp &= ~SATP_ASID;
- satp |= __SHIFTIN((uintptr_t)asid, SATP_ASID);
+ satp |= __SHIFTIN(asid, SATP_ASID);
__asm __volatile("csrw satp, %0" :: "r" (satp));
}
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Sep 10 09:28:26 UTC 2022 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Remove unnecessary cast. To generate a diff of this commit: cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
