CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: martin
Date: Sat Jul 29 10:23:07 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up the following revisions, via patch, requested by msaitoh
in ticket #1854:
usr.sbin/cpuctl/arch/i386.c 1.137-1.139
- CPU model 0x5a is not Atom E3500 but Atom Z3500.
- Add Alder Lake-N.
To generate a diff of this commit:
cvs rdiff -u -r1.74.6.17 -r1.74.6.18 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.17 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.18
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.17 Wed Jun 21 19:06:15 2023
+++ src/usr.sbin/cpuctl/arch/i386.c Sat Jul 29 10:23:07 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.17 2023/06/21 19:06:15 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.18 2023/07/29 10:23:07 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.17 2023/06/21 19:06:15 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.18 2023/07/29 10:23:07 martin Exp $");
#endif /* not lint */
#include
@@ -335,7 +335,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
[0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Xeon Phi [357]200 (Knights Landing)",
-[0x5a] = "Atom E3500",
+[0x5a] = "Atom Z3500",
[0x5c] = "Atom (Goldmont)",
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
@@ -361,8 +361,9 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa6] = "10th gen Core (Comet Lake)",
[0xa7] = "11th gen Core (Rocket Lake)",
[0xa8] = "11th gen Core (Rocket Lake)",
-[0xba] = "13th gen Core (Raptor Lake)",
[0xb7] = "13th gen Core (Raptor Lake)",
+[0xba] = "13th gen Core (Raptor Lake)",
+[0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)",
[0xbf] = "13th gen Core (Raptor Lake)",
},
"Pentium Pro, II or III", /* Default */
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src Committed By: martin Date: Sat Jul 29 10:23:07 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c Log Message: Pull up the following revisions, via patch, requested by msaitoh in ticket #1854: usr.sbin/cpuctl/arch/i386.c 1.137-1.139 - CPU model 0x5a is not Atom E3500 but Atom Z3500. - Add Alder Lake-N. To generate a diff of this commit: cvs rdiff -u -r1.74.6.17 -r1.74.6.18 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src Committed By: martin Date: Mon Jan 23 13:13:08 UTC 2023 Modified Files: src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c Log Message: Pull up the following revisions, requested by msaitoh in ticket #1792: usr.sbin/cpuctl/arch/i386.c 1.129-1.135 - Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx. - Add Raptor Lake and Sapphire Rapids. - Modify messages a little. To generate a diff of this commit: cvs rdiff -u -r1.74.6.15 -r1.74.6.16 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: martin
Date: Mon Jan 23 13:13:08 UTC 2023
Modified Files:
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up the following revisions, requested by msaitoh in ticket #1792:
usr.sbin/cpuctl/arch/i386.c 1.129-1.135
- Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.
- Add Raptor Lake and Sapphire Rapids.
- Modify messages a little.
To generate a diff of this commit:
cvs rdiff -u -r1.74.6.15 -r1.74.6.16 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.15 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.16
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.15 Sat Oct 15 10:16:08 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Jan 23 13:13:08 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.15 2022/10/15 10:16:08 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.16 2023/01/23 13:13:08 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.15 2022/10/15 10:16:08 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.16 2023/01/23 13:13:08 martin Exp $");
#endif /* not lint */
#include
@@ -351,7 +351,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x8c] = "11th gen Core (Tiger Lake)",
[0x8d] = "11th gen Core (Tiger Lake)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
-[0x8f] = "future Xeon (Sapphire Rapids)",
+[0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)",
[0x96] = "Atom x6000E (Elkhart Lake)",
[0x97] = "12th gen Core (Alder Lake)",
[0x9a] = "12th gen Core (Alder Lake)",
@@ -361,7 +361,9 @@ const struct cpu_cpuid_nameclass i386_cp
[0xa6] = "10th gen Core (Comet Lake)",
[0xa7] = "11th gen Core (Rocket Lake)",
[0xa8] = "11th gen Core (Rocket Lake)",
-[0xbf] = "12th gen Core (Alder Lake)",
+[0xba] = "13th gen Core (Raptor Lake)",
+[0xb7] = "13th gen Core (Raptor Lake)",
+[0xbf] = "13th gen Core (Raptor Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
@@ -2132,13 +2134,25 @@ identifycpu(int fd, const char *cpuname)
if ((ci->ci_max_cpuid >= 7)
&& ((cpu_vendor == CPUVENDOR_INTEL)
|| (cpu_vendor == CPUVENDOR_AMD))) {
+ unsigned int maxsubleaf;
+
x86_cpuid(7, descs);
+ maxsubleaf = descs[0];
aprint_verbose("%s: SEF highest subleaf %08x\n",
- cpuname, descs[0]);
- if (descs[0] >= 1) {
+ cpuname, maxsubleaf);
+ if (maxsubleaf >= 1) {
x86_cpuid2(7, 1, descs);
print_bits(cpuname, "SEF-subleaf1-eax",
CPUID_SEF1_FLAGS_A, descs[0]);
+ print_bits(cpuname, "SEF-subleaf1-ebx",
+ CPUID_SEF1_FLAGS_B, descs[1]);
+ print_bits(cpuname, "SEF-subleaf1-edx",
+ CPUID_SEF1_FLAGS_D, descs[3]);
+ }
+ if (maxsubleaf >= 2) {
+ x86_cpuid2(7, 2, descs);
+ print_bits(cpuname, "SEF-subleaf2-edx",
+ CPUID_SEF2_FLAGS_D, descs[3]);
}
}
@@ -2154,6 +2168,17 @@ identifycpu(int fd, const char *cpuname)
}
if (cpu_vendor == CPUVENDOR_AMD) {
+ if (ci->ci_max_ext_cpuid >= 0x8021) {
+ x86_cpuid(0x8021, descs);
+ print_bits(cpuname, "AMD Extended features2",
+ CPUID_AMDEXT2_FLAGS, descs[0]);
+ }
+
+ if (ci->ci_max_ext_cpuid >= 0x8007) {
+ x86_cpuid(0x8007, descs);
+ print_bits(cpuname, "RAS features",
+ CPUID_RAS_FLAGS, descs[1]);
+ }
if ((ci->ci_max_ext_cpuid >= 0x800a)
&& (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x800a, descs);
@@ -2164,11 +2189,32 @@ identifycpu(int fd, const char *cpuname)
print_bits(cpuname, "SVM features",
CPUID_AMD_SVM_FLAGS, descs[3]);
}
+ if (ci->ci_max_ext_cpuid >= 0x801b) {
+ x86_cpuid(0x801b, descs);
+ print_bits(cpuname, "IBS features",
+ CPUID_IBS_FLAGS, descs[0]);
+ }
if (ci->ci_max_ext_cpuid >= 0x801f) {
x86_cpuid(0x801f, descs);
print_bits(cpuname, "Encrypted Memory features",
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
}
+ if (ci->ci_max_ext_cpuid >= 0x8022) {
+ uint8_t ncore, nnb, nlbrs;
+
+ x86_cpuid(0x8022, descs);
+ print_bits(cpuname, "Perfmon:",
+ CPUID_AXPERF_FLAGS, descs[0]);
+
+ ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC);
+ nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC);
+ nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK);
+ aprint_verbose("%s: Perfmon: counters: "
+ "Core %hhu, Northbridge %hhu\n", cpuname,
+ ncore, nnb);
+ aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n",
+ cpuname, nlbrs);
+ }
} else if (cpu_vendor == CPUVENDOR_INTEL) {
if (ci->ci_max_cpuid >= 0x0a) {
unsigned int pmcver, ncounter, veclen;
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: martin
Date: Mon Jan 31 17:52:44 UTC 2022
Modified Files:
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1732):
usr.sbin/cpuctl/arch/i386.c: revision 1.125
usr.sbin/cpuctl/arch/i386.c: revision 1.126
usr.sbin/cpuctl/arch/i386.c: revision 1.127
Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.
Remove debug code and simplify. No functional change.
Decode Intel Hybrid Information Enumeration (CPUID Fn_001a).
To generate a diff of this commit:
cvs rdiff -u -r1.74.6.13 -r1.74.6.14 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.13 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.14
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.13 Fri Dec 24 13:02:24 2021
+++ src/usr.sbin/cpuctl/arch/i386.c Mon Jan 31 17:52:44 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.14 2022/01/31 17:52:44 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.13 2021/12/24 13:02:24 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.14 2022/01/31 17:52:44 martin Exp $");
#endif /* not lint */
#include
@@ -351,11 +351,17 @@ const struct cpu_cpuid_nameclass i386_cp
[0x8c] = "11th gen Core (Tiger Lake)",
[0x8d] = "11th gen Core (Tiger Lake)",
[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x8f] = "future Xeon (Sapphire Rapids)",
[0x96] = "Atom x6000E (Elkhart Lake)",
+[0x97] = "12th gen Core (Alder Lake)",
+[0x9a] = "12th gen Core (Alder Lake)",
[0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)",
[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
[0xa5] = "10th gen Core (Comet Lake)",
[0xa6] = "10th gen Core (Comet Lake)",
+[0xa7] = "11th gen Core (Rocket Lake)",
+[0xa8] = "11th gen Core (Rocket Lake)",
+[0xbf] = "12th gen Core (Alder Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
@@ -2164,31 +2170,25 @@ identifycpu(int fd, const char *cpuname)
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
}
} else if (cpu_vendor == CPUVENDOR_INTEL) {
- int32_t bi_index;
-
- for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) {
- x86_cpuid(bi_index, descs);
- switch (bi_index) {
- case 0x0a:
-print_bits(cpuname, "Perfmon-eax",
-CPUID_PERF_FLAGS0, descs[0]);
-print_bits(cpuname, "Perfmon-ebx",
-CPUID_PERF_FLAGS1, descs[1]);
-print_bits(cpuname, "Perfmon-edx",
-CPUID_PERF_FLAGS3, descs[3]);
-break;
- default:
-#if 0
-aprint_verbose("%s: basic %08x-eax %08x\n",
-cpuname, bi_index, descs[0]);
-aprint_verbose("%s: basic %08x-ebx %08x\n",
-cpuname, bi_index, descs[1]);
-aprint_verbose("%s: basic %08x-ecx %08x\n",
-cpuname, bi_index, descs[2]);
-aprint_verbose("%s: basic %08x-edx %08x\n",
-cpuname, bi_index, descs[3]);
-#endif
-break;
+ if (ci->ci_max_cpuid >= 0x0a) {
+ x86_cpuid(0x0a, descs);
+ print_bits(cpuname, "Perfmon-eax",
+ CPUID_PERF_FLAGS0, descs[0]);
+ print_bits(cpuname, "Perfmon-ebx",
+ CPUID_PERF_FLAGS1, descs[1]);
+ print_bits(cpuname, "Perfmon-edx",
+ CPUID_PERF_FLAGS3, descs[3]);
+ }
+ if (ci->ci_max_cpuid >= 0x1a) {
+ x86_cpuid(0x1a, descs);
+ if (descs[0] != 0) {
+aprint_verbose("%s: Hybrid: Core type %02x, "
+"Native Model ID %07x\n",
+cpuname,
+(uint8_t)__SHIFTOUT(descs[0],
+ CPUID_HYBRID_CORETYPE),
+(uint32_t)__SHIFTOUT(descs[0],
+ CPUID_HYBRID_NATIVEID));
}
}
}
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src Committed By: martin Date: Mon Jan 31 17:52:44 UTC 2022 Modified Files: src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c Log Message: Pull up following revision(s) (requested by msaitoh in ticket #1732): usr.sbin/cpuctl/arch/i386.c: revision 1.125 usr.sbin/cpuctl/arch/i386.c: revision 1.126 usr.sbin/cpuctl/arch/i386.c: revision 1.127 Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM. Remove debug code and simplify. No functional change. Decode Intel Hybrid Information Enumeration (CPUID Fn_001a). To generate a diff of this commit: cvs rdiff -u -r1.74.6.13 -r1.74.6.14 src/usr.sbin/cpuctl/arch/i386.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-8] src/usr.sbin/cpuctl/arch
Module Name:src
Committed By: martin
Date: Wed Jul 17 16:01:43 UTC 2019
Modified Files:
src/usr.sbin/cpuctl/arch [netbsd-8]: i386.c
Log Message:
Pull up the following revisions (via patch), requested by msaitoh
in ticket #1296:
usr.sbin/cpuctl/arch/i386.c 1.91,1.93-1.95,1.100-1.103
- Handle NVMM and HAXM's signature.
- Regard "TCGTCGTCGTCG" as QEMU(TCG).
- Dump CPUID leaf 0x4000 if available (for -v option).
- Add Cascade Lake, Copper Lake.
- Add Future Xeon (Cannon Lake)
- Add 06_7DH for another Ice Lake.
- Add Coffee Lake based Xeon E.
- White space fix. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.74.6.5 -r1.74.6.6 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.74.6.5 src/usr.sbin/cpuctl/arch/i386.c:1.74.6.6
--- src/usr.sbin/cpuctl/arch/i386.c:1.74.6.5 Mon Feb 11 13:23:03 2019
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Jul 17 16:01:43 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.74.6.5 2019/02/11 13:23:03 martin Exp $ */
+/* $NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.74.6.5 2019/02/11 13:23:03 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.74.6.6 2019/07/17 16:01:43 martin Exp $");
#endif /* not lint */
#include
@@ -167,7 +167,7 @@ static const char * const i386_intel_bra
"Pentium III", /* Intel (R) Pentium (R) III processor */
"", /* 0x05: Reserved */
"Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
- "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
+ "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
"Celeron", /* Intel (R) Celeron (TM) processor */
@@ -320,10 +320,10 @@ const struct cpu_cpuid_nameclass i386_cp
[0x06] = "Celeron (Mendocino)",
[0x07] = "Pentium III (Katmai)",
[0x08] = "Pentium III (Coppermine)",
-[0x09] = "Pentium M (Banias)",
+[0x09] = "Pentium M (Banias)",
[0x0a] = "Pentium III Xeon (Cascades)",
[0x0b] = "Pentium III (Tualatin)",
-[0x0d] = "Pentium M (Dothan)",
+[0x0d] = "Pentium M (Dothan)",
[0x0e] = "Pentium Core Duo, Core solo",
[0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, "
"Core 2 Quad 6xxx, "
@@ -372,7 +372,7 @@ const struct cpu_cpuid_nameclass i386_cp
[0x4d] = "Atom C2000",
[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
-[0x55] = "Xeon Scalable (Skylake)",
+[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
[0x56] = "Xeon D-1500 (Broadwell)",
[0x57] = "Xeon Phi [357]200 (Knights Landing)",
[0x5a] = "Atom E3500",
@@ -380,13 +380,16 @@ const struct cpu_cpuid_nameclass i386_cp
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x5f] = "Atom (Goldmont, Denverton)",
-[0x66] = "Future Core (Cannon Lake)",
+[0x66] = "8th gen Core i3 (Cannon Lake)",
+[0x6a] = "Future Xeon (Ice Lake)",
+[0x6c] = "Future Xeon (Ice Lake)",
[0x7a] = "Atom (Goldmont Plus)",
+[0x7d] = "Future Core (Ice Lake)",
[0x7e] = "Future Core (Ice Lake)",
[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
[0x86] = "Atom (Tremont)",
-[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
-[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
+[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
+[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
@@ -725,7 +728,7 @@ static void
cyrix6x86_cpu_setup(struct cpu_info *ci)
{
- /*
+ /*
* Do not disable the TSC on the Geode GX, it's reported to
* work fine.
*/
@@ -975,7 +978,7 @@ amd_family6_probe(struct cpu_info *ci)
if (*cpu_brand_string == '\0')
return;
-
+
for (i = 1; i < __arraycount(amd_brand); i++)
if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) {
ci->ci_brand_id = i;
@@ -1226,10 +1229,10 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
}
}
-static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
+static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
AMD_L2CACHE_INFO;
-static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
+static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] =
AMD_L3CACHE_INFO;
static void
@@ -1716,19 +1719,28 @@ cpu_probe_hv_features(struct cpu_info *c
/*
* HV vendor ID string
