CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: dyoung
Date: Sat May 4 02:04:55 UTC 2024
Modified Files:
src/sys/arch/arm/xilinx: zynq_uart.c
Log Message:
Initialize `struct consdev` members cn_dev and cn_pri like other
UART drivers do. If cn_dev is 0 instead of NODEV, then the kernel
may redirect console writes to major 0, minor 0, which is /dev/mem.
On my Zynq board the kernel overwrote the page free list with a
console message in this way.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/xilinx/zynq_uart.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_uart.c
diff -u src/sys/arch/arm/xilinx/zynq_uart.c:1.5 src/sys/arch/arm/xilinx/zynq_uart.c:1.6
--- src/sys/arch/arm/xilinx/zynq_uart.c:1.5 Thu Oct 27 07:57:46 2022
+++ src/sys/arch/arm/xilinx/zynq_uart.c Sat May 4 02:04:54 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $ */
+/* $NetBSD: zynq_uart.c,v 1.6 2024/05/04 02:04:54 dyoung Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@@ -96,7 +96,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.6 2024/05/04 02:04:54 dyoung Exp $");
#include "opt_soc.h"
#include "opt_console.h"
@@ -1974,7 +1974,9 @@ zynquart_init(struct zynquart_regs *regs
struct consdev zynquartcons = {
.cn_getc = zynquartcngetc,
.cn_putc = zynquartcnputc,
- .cn_pollc = nullcnpollc
+ .cn_pollc = nullcnpollc,
+ .cn_dev = NODEV,
+ .cn_pri = CN_NORMAL,
};
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: dyoung Date: Sat May 4 02:04:55 UTC 2024 Modified Files: src/sys/arch/arm/xilinx: zynq_uart.c Log Message: Initialize `struct consdev` members cn_dev and cn_pri like other UART drivers do. If cn_dev is 0 instead of NODEV, then the kernel may redirect console writes to major 0, minor 0, which is /dev/mem. On my Zynq board the kernel overwrote the page free list with a console message in this way. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/xilinx/zynq_uart.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Fri Nov 11 20:29:47 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq7000_clkc.c
Log Message:
Support PCAL clock control
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/xilinx/zynq7000_clkc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq7000_clkc.c
diff -u src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.4 src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.5
--- src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.4 Sat Nov 5 17:28:55 2022
+++ src/sys/arch/arm/xilinx/zynq7000_clkc.c Fri Nov 11 20:29:47 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $ */
+/* $NetBSD: zynq7000_clkc.c,v 1.5 2022/11/11 20:29:47 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.5 2022/11/11 20:29:47 jmcneill Exp $");
#include
#include
@@ -62,6 +62,7 @@ __KERNEL_RCSID(0, "$NetBSD: zynq7000_clk
#define SDI0_CPU_1XCLKACT __BIT(10)
#define SDIO_CLK_CTRL 0x150
#define UART_CLK_CTRL 0x154
+#define PCAP_CLK_CTRL 0x168
#define CLK_CTRL_DIVISOR __BITS(13,8)
#define CLK_CTRL_SRCSEL __BITS(5,4)
#define CLK_CTRL_CLKACT1 __BIT(1)
@@ -247,6 +248,8 @@ zynq7000_clkc_clk_get_rate(void *priv, s
} else if (clk == >sc_clk[clkid_uart0] ||
clk == >sc_clk[clkid_uart1]) {
return zynq7000_clkc_get_rate_iop(sc, UART_CLK_CTRL);
+ } else if (clk == >sc_clk[clkid_pcap]) {
+ return zynq7000_clkc_get_rate_iop(sc, PCAP_CLK_CTRL);
} else if (clk == >sc_clk[clkid_uart0_aper] ||
clk == >sc_clk[clkid_uart1_aper] ||
clk == >sc_clk[clkid_i2c0_aper] ||
@@ -290,6 +293,9 @@ zynq7000_clkc_clk_enable(void *priv, str
} else if (clk == >sc_clk[clkid_uart1]) {
reg = UART_CLK_CTRL;
mask = CLK_CTRL_CLKACT1;
+ } else if (clk == >sc_clk[clkid_pcap]) {
+ reg = PCAP_CLK_CTRL;
+ mask = CLK_CTRL_CLKACT0;
} else if (clk == >sc_clk[clkid_sdio0_aper]) {
reg = APER_CLK_CTRL;
mask = SDI0_CPU_1XCLKACT;
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Fri Nov 11 20:29:47 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq7000_clkc.c Log Message: Support PCAL clock control To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/xilinx/zynq7000_clkc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Sat Nov 5 17:28:55 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq7000_clkc.c
Log Message:
Add I2C clocks
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq7000_clkc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq7000_clkc.c
diff -u src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.3 src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.4
--- src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.3 Wed Oct 26 22:14:22 2022
+++ src/sys/arch/arm/xilinx/zynq7000_clkc.c Sat Nov 5 17:28:55 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $ */
+/* $NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $");
#include
#include
@@ -56,6 +56,8 @@ __KERNEL_RCSID(0, "$NetBSD: zynq7000_clk
#define APER_CLK_CTRL 0x12c
#define UART1_CPU_1XCLKACT __BIT(21)
#define UART0_CPU_1XCLKACT __BIT(20)
+#define I2C1_CPU_1XCLKACT __BIT(19)
+#define I2C0_CPU_1XCLKACT __BIT(18)
#define SDI1_CPU_1XCLKACT __BIT(11)
#define SDI0_CPU_1XCLKACT __BIT(10)
#define SDIO_CLK_CTRL 0x150
@@ -246,7 +248,9 @@ zynq7000_clkc_clk_get_rate(void *priv, s
clk == >sc_clk[clkid_uart1]) {
return zynq7000_clkc_get_rate_iop(sc, UART_CLK_CTRL);
} else if (clk == >sc_clk[clkid_uart0_aper] ||
- clk == >sc_clk[clkid_uart1_aper]) {
+ clk == >sc_clk[clkid_uart1_aper] ||
+ clk == >sc_clk[clkid_i2c0_aper] ||
+ clk == >sc_clk[clkid_i2c1_aper]) {
return zynq7000_clkc_clk_get_rate(sc,
>sc_clk[clkid_cpu_1x]);
} else {
@@ -298,6 +302,12 @@ zynq7000_clkc_clk_enable(void *priv, str
} else if (clk == >sc_clk[clkid_uart1_aper]) {
reg = APER_CLK_CTRL;
mask = UART1_CPU_1XCLKACT;
+ } else if (clk == >sc_clk[clkid_i2c0_aper]) {
+ reg = APER_CLK_CTRL;
+ mask = I2C0_CPU_1XCLKACT;
+ } else if (clk == >sc_clk[clkid_i2c1_aper]) {
+ reg = APER_CLK_CTRL;
+ mask = I2C1_CPU_1XCLKACT;
} else {
return ENXIO;
}
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Sat Nov 5 17:28:55 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq7000_clkc.c Log Message: Add I2C clocks To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq7000_clkc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Mon Oct 31 23:04:50 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_gpio.c Log Message: Fix MASK_DATA logic in previous commit -- the upper 16-bits are a mask of pin states to preserve, not to set. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq_gpio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Mon Oct 31 23:04:50 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_gpio.c
Log Message:
Fix MASK_DATA logic in previous commit -- the upper 16-bits are a mask
of pin states to preserve, not to set.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq_gpio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_gpio.c
diff -u src/sys/arch/arm/xilinx/zynq_gpio.c:1.3 src/sys/arch/arm/xilinx/zynq_gpio.c:1.4
--- src/sys/arch/arm/xilinx/zynq_gpio.c:1.3 Sat Oct 29 01:19:36 2022
+++ src/sys/arch/arm/xilinx/zynq_gpio.c Mon Oct 31 23:04:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_gpio.c,v 1.3 2022/10/29 01:19:36 jmcneill Exp $ */
+/* $NetBSD: zynq_gpio.c,v 1.4 2022/10/31 23:04:50 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.3 2022/10/29 01:19:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.4 2022/10/31 23:04:50 jmcneill Exp $");
#include
#include
@@ -46,8 +46,6 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,
#define ZYNQ_GPIO_NPINS (4 * 32)
#define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
-#define MASK_DATA_SET(pin, val) \
- ((1 << (((pin) % 16) + 16)) | ((val) << ((pin) % 16)))
#define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
#define DATA_RO_BIT(pin) __BIT((pin) % 32)
#define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
@@ -94,17 +92,21 @@ CFATTACH_DECL_NEW(zynqgpio, sizeof(struc
static int
zynq_gpio_ctl(struct zynq_gpio_softc *sc, u_int pin, int flags)
{
- uint32_t val;
+ uint32_t dirm, oen;
KASSERT(mutex_owned(>sc_lock));
- val = RD4(sc, OEN_REG(pin));
+ dirm = RD4(sc, DIRM_REG(pin));
+ oen = RD4(sc, OEN_REG(pin));
if ((flags & GPIO_PIN_INPUT) != 0) {
- val &= ~OEN_BIT(pin);
+ dirm &= ~DIRM_BIT(pin);
+ oen &= ~OEN_BIT(pin);
} else if ((flags & GPIO_PIN_OUTPUT) != 0) {
- val |= OEN_BIT(pin);
+ dirm |= DIRM_BIT(pin);
+ oen |= OEN_BIT(pin);
}
- WR4(sc, OEN_REG(pin), val);
+ WR4(sc, OEN_REG(pin), oen);
+ WR4(sc, DIRM_REG(pin), dirm);
return 0;
}
@@ -211,10 +213,15 @@ static void
zynq_gpio_pin_write(void *priv, int pin, int val)
{
struct zynq_gpio_softc * const sc = priv;
+ uint32_t mask_data;
KASSERT(pin < __arraycount(sc->sc_pins));
- WR4(sc, MASK_DATA_REG(pin), MASK_DATA_SET(pin, val));
+ mask_data = (0x & ~__BIT(pin % 16)) << 16;
+ if (val) {
+ mask_data |= __BIT(pin % 16);
+ }
+ WR4(sc, MASK_DATA_REG(pin), mask_data);
}
static void
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Mon Oct 31 22:23:39 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_platform.c
Log Message:
Implement zynq_platform_reset()
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/xilinx/zynq_platform.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_platform.c
diff -u src/sys/arch/arm/xilinx/zynq_platform.c:1.9 src/sys/arch/arm/xilinx/zynq_platform.c:1.10
--- src/sys/arch/arm/xilinx/zynq_platform.c:1.9 Fri Oct 28 20:37:03 2022
+++ src/sys/arch/arm/xilinx/zynq_platform.c Mon Oct 31 22:23:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_platform.c,v 1.9 2022/10/28 20:37:03 jmcneill Exp $ */
+/* $NetBSD: zynq_platform.c,v 1.10 2022/10/31 22:23:38 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "arml2cc.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.9 2022/10/28 20:37:03 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.10 2022/10/31 22:23:38 jmcneill Exp $");
#include
#include
@@ -69,7 +69,11 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor
#define ZYNQ_IOREG_PBASE 0xe000
#define ZYNQ_IOREG_SIZE 0x0020
-#define ZYNQ_GPV_VBASE (ZYNQ_IOREG_VBASE + ZYNQ_IOREG_SIZE)
+#define ZYNQ_SLCR_VBASE (ZYNQ_IOREG_VBASE + ZYNQ_IOREG_SIZE)
+#define ZYNQ_SLCR_PBASE 0xf800
+#define ZYNQ_SLCR_SIZE 0x0010
+
+#define ZYNQ_GPV_VBASE (ZYNQ_SLCR_VBASE + ZYNQ_SLCR_SIZE)
#define ZYNQ_GPV_PBASE 0xf890
#define ZYNQ_GPV_SIZE 0x0010
@@ -87,6 +91,12 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor
#define ZYNQ7000_CPU1_ENTRY 0xfff0
#define ZYNQ7000_CPU1_ENTRY_SZ 4
+/* SLCR registers */
+#define SLCR_UNLOCK 0x008
+#define UNLOCK_KEY 0xdf0d
+#define PSS_RST_CTRL 0x200
+#define SOFT_RST __BIT(0)
+
extern struct bus_space arm_generic_bs_tag;
extern struct arm32_bus_dma_tag arm_generic_dma_tag;
@@ -99,6 +109,9 @@ zynq_platform_devmap(void)
DEVMAP_ENTRY(ZYNQ_IOREG_VBASE,
ZYNQ_IOREG_PBASE,
ZYNQ_IOREG_SIZE),
+ DEVMAP_ENTRY(ZYNQ_SLCR_VBASE,
+ ZYNQ_SLCR_PBASE,
+ ZYNQ_SLCR_SIZE),
DEVMAP_ENTRY(ZYNQ_GPV_VBASE,
ZYNQ_GPV_PBASE,
ZYNQ_GPV_SIZE),
@@ -232,7 +245,11 @@ zynq_platform_bootstrap(void)
static void
zynq_platform_reset(void)
{
+ bus_space_tag_t bst = _generic_bs_tag;
+ bus_space_handle_t bsh = ZYNQ_SLCR_VBASE;
+ bus_space_write_4(bst, bsh, SLCR_UNLOCK, UNLOCK_KEY);
+ bus_space_write_4(bst, bsh, PSS_RST_CTRL, SOFT_RST);
}
static const struct arm_platform zynq_platform = {
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Mon Oct 31 22:23:39 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_platform.c Log Message: Implement zynq_platform_reset() To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/xilinx/zynq_platform.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Sat Oct 29 01:19:36 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_gpio.c Log Message: Fix MASK_DATA_SET macro To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq_gpio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/xilinx/zynq_gpio.c diff -u src/sys/arch/arm/xilinx/zynq_gpio.c:1.2 src/sys/arch/arm/xilinx/zynq_gpio.c:1.3 --- src/sys/arch/arm/xilinx/zynq_gpio.c:1.2 Thu Oct 27 22:35:31 2022 +++ src/sys/arch/arm/xilinx/zynq_gpio.c Sat Oct 29 01:19:36 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: zynq_gpio.c,v 1.2 2022/10/27 22:35:31 jmcneill Exp $ */ +/* $NetBSD: zynq_gpio.c,v 1.3 2022/10/29 01:19:36 jmcneill Exp $ */ /*- * Copyright (c) 2022 Jared McNeill @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.2 2022/10/27 22:35:31 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.3 2022/10/29 01:19:36 jmcneill Exp $"); #include #include @@ -46,7 +46,8 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c, #define ZYNQ_GPIO_NPINS (4 * 32) #define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16)) -#define MASK_DATA_SET(pin, val) pin) % 16) << 16) | ((val) << ((pin) % 16))) +#define MASK_DATA_SET(pin, val) \ + ((1 << (((pin) % 16) + 16)) | ((val) << ((pin) % 16))) #define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32)) #define DATA_RO_BIT(pin) __BIT((pin) % 32) #define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Sat Oct 29 01:19:36 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_gpio.c Log Message: Fix MASK_DATA_SET macro To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq_gpio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Thu Oct 27 22:35:32 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_gpio.c
Log Message:
Fix bit macros
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/xilinx/zynq_gpio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_gpio.c
diff -u src/sys/arch/arm/xilinx/zynq_gpio.c:1.1 src/sys/arch/arm/xilinx/zynq_gpio.c:1.2
--- src/sys/arch/arm/xilinx/zynq_gpio.c:1.1 Thu Oct 27 09:41:28 2022
+++ src/sys/arch/arm/xilinx/zynq_gpio.c Thu Oct 27 22:35:31 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_gpio.c,v 1.1 2022/10/27 09:41:28 jmcneill Exp $ */
+/* $NetBSD: zynq_gpio.c,v 1.2 2022/10/27 22:35:31 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.1 2022/10/27 09:41:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.2 2022/10/27 22:35:31 jmcneill Exp $");
#include
#include
@@ -48,11 +48,11 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,
#define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
#define MASK_DATA_SET(pin, val) pin) % 16) << 16) | ((val) << ((pin) % 16)))
#define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
-#define DATA_RO_BIT(pin) ((pin) % 32)
+#define DATA_RO_BIT(pin) __BIT((pin) % 32)
#define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
-#define DIRM_BIT(pin) ((pin) % 32)
+#define DIRM_BIT(pin) __BIT((pin) % 32)
#define OEN_REG(pin) (0x208 + 0x40 * ((pin) / 32))
-#define OEN_BIT(pin) ((pin) % 32)
+#define OEN_BIT(pin) __BIT((pin) % 32)
static const struct device_compatible_entry compat_data[] = {
{ .compat = "xlnx,zynq-gpio-1.0" },
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Thu Oct 27 22:35:32 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_gpio.c Log Message: Fix bit macros To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/xilinx/zynq_gpio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Thu Oct 27 20:37:10 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_platform.c Log Message: Add OCM to devmap To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/xilinx/zynq_platform.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/xilinx/zynq_platform.c diff -u src/sys/arch/arm/xilinx/zynq_platform.c:1.7 src/sys/arch/arm/xilinx/zynq_platform.c:1.8 --- src/sys/arch/arm/xilinx/zynq_platform.c:1.7 Thu Oct 27 08:49:08 2022 +++ src/sys/arch/arm/xilinx/zynq_platform.c Thu Oct 27 20:37:10 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: zynq_platform.c,v 1.7 2022/10/27 08:49:08 jmcneill Exp $ */ +/* $NetBSD: zynq_platform.c,v 1.8 2022/10/27 20:37:10 jmcneill Exp $ */ /*- * Copyright (c) 2019 The NetBSD Foundation, Inc. @@ -35,7 +35,7 @@ #include "arml2cc.h" #include -__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.7 2022/10/27 08:49:08 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.8 2022/10/27 20:37:10 jmcneill Exp $"); #include #include @@ -77,6 +77,10 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor #define ZYNQ_ARMCORE_PBASE 0xf8f0 #define ZYNQ_ARMCORE_SIZE 0x3000 +#define ZYNQ_OCM_VBASE (ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_SIZE) +#define ZYNQ_OCM_PBASE 0xfff0 +#define ZYNQ_OCM_SIZE 0x0010 + #define ZYNQ_ARMCORE_SCU_BASE 0x #define ZYNQ_ARMCORE_L2C_BASE 0x2000 @@ -101,6 +105,9 @@ zynq_platform_devmap(void) DEVMAP_ENTRY(ZYNQ_ARMCORE_VBASE, ZYNQ_ARMCORE_PBASE, ZYNQ_ARMCORE_SIZE), + DEVMAP_ENTRY(ZYNQ_OCM_VBASE, + ZYNQ_OCM_PBASE, + ZYNQ_OCM_SIZE), DEVMAP_ENTRY_END };
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Thu Oct 27 20:37:10 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_platform.c Log Message: Add OCM to devmap To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/xilinx/zynq_platform.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Thu Oct 27 08:49:08 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_platform.c
Log Message:
Add AP startup for Zynq-7000.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/xilinx/zynq_platform.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_platform.c
diff -u src/sys/arch/arm/xilinx/zynq_platform.c:1.6 src/sys/arch/arm/xilinx/zynq_platform.c:1.7
--- src/sys/arch/arm/xilinx/zynq_platform.c:1.6 Tue Oct 25 22:59:10 2022
+++ src/sys/arch/arm/xilinx/zynq_platform.c Thu Oct 27 08:49:08 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_platform.c,v 1.6 2022/10/25 22:59:10 jmcneill Exp $ */
+/* $NetBSD: zynq_platform.c,v 1.7 2022/10/27 08:49:08 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "arml2cc.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.6 2022/10/25 22:59:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.7 2022/10/27 08:49:08 jmcneill Exp $");
#include
#include
@@ -50,6 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor
#include
#include
+#include
#include
#include
@@ -58,8 +59,9 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor
#include
-#define ZYNQ_REF_FREQ 2400
+#include
+#define ZYNQ_REF_FREQ 2400
#define ZYNQ7000_DDR_PBASE 0x
#define ZYNQ7000_DDR_SIZE 0x4000
@@ -75,6 +77,12 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_platfor
#define ZYNQ_ARMCORE_PBASE 0xf8f0
#define ZYNQ_ARMCORE_SIZE 0x3000
+#define ZYNQ_ARMCORE_SCU_BASE 0x
+#define ZYNQ_ARMCORE_L2C_BASE 0x2000
+
+#define ZYNQ7000_CPU1_ENTRY 0xfff0
+#define ZYNQ7000_CPU1_ENTRY_SZ 4
+
extern struct bus_space arm_generic_bs_tag;
extern struct arm32_bus_dma_tag arm_generic_dma_tag;
@@ -135,7 +143,51 @@ zynq_platform_uart_freq(void)
return ZYNQ_REF_FREQ;
}
-#define ZYNQ_ARMCORE_L2C_BASE 0x2000
+#ifdef MULTIPROCESSOR
+static int
+zynq_platform_mpstart(void)
+{
+ bus_space_tag_t bst = _generic_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t val;
+ int error;
+ u_int i;
+
+ /* Invalidate all SCU cache tags and enable SCU. */
+ bsh = ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_SCU_BASE;
+ bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0x);
+ val = bus_space_read_4(bst, bsh, SCU_CTL);
+ bus_space_write_4(bst, bsh, SCU_CTL, val | SCU_CTL_SCU_ENA);
+ armv7_dcache_wbinv_all();
+
+ /* Write start address for CPU1. */
+ error = bus_space_map(bst, ZYNQ7000_CPU1_ENTRY,
+ ZYNQ7000_CPU1_ENTRY_SZ, 0, );
+ if (error) {
+ panic("%s: Couldn't map OCM: %d", __func__, error);
+ }
+ bus_space_write_4(bst, bsh, 0, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
+ bus_space_unmap(bst, bsh, ZYNQ7000_CPU1_ENTRY_SZ);
+
+ dsb(sy);
+ sev();
+
+ const u_int cpuindex = 1;
+ for (i = 0x1000; i > 0; i--) {
+ if (cpu_hatched_p(cpuindex)) {
+ break;
+ }
+ }
+ if (i == 0) {
+ aprint_error("cpu%d: WARNING: AP failed to start\n",
+ cpuindex);
+ return EIO;
+ }
+
+ return 0;
+}
+#endif
+
#define ZYNQ_ARM_PL310_BASE ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_L2C_BASE
static void
@@ -184,8 +236,8 @@ static const struct arm_platform zynq_pl
.ap_reset = zynq_platform_reset,
.ap_delay = a9tmr_delay,
.ap_uart_freq = zynq_platform_uart_freq,
-#if 0
- .ap_mpstart = arm_fdt_cpu_mpstart,
+#ifdef MULTIPROCESSOR
+ .ap_mpstart = zynq_platform_mpstart,
#endif
};
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Thu Oct 27 08:49:08 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_platform.c Log Message: Add AP startup for Zynq-7000. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/xilinx/zynq_platform.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: skrll
Date: Thu Oct 27 07:57:46 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_uart.c
Log Message:
Fix build.
Sprinkle some consistency
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/xilinx/zynq_uart.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_uart.c
diff -u src/sys/arch/arm/xilinx/zynq_uart.c:1.4 src/sys/arch/arm/xilinx/zynq_uart.c:1.5
--- src/sys/arch/arm/xilinx/zynq_uart.c:1.4 Wed Oct 26 23:38:07 2022
+++ src/sys/arch/arm/xilinx/zynq_uart.c Thu Oct 27 07:57:46 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_uart.c,v 1.4 2022/10/26 23:38:07 riastradh Exp $ */
+/* $NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@@ -96,7 +96,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.4 2022/10/26 23:38:07 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_uart.c,v 1.5 2022/10/27 07:57:46 skrll Exp $");
#include "opt_soc.h"
#include "opt_console.h"
@@ -1904,10 +1904,9 @@ zynquart_common_getc(dev_t dev, struct z
c = 0xff & bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
- {
+ if (!db_active) {
int cn_trapped __unused = 0;
- if (!db_active) {
- cn_check_magic(dev, c, zynquart_cnm_state);
+ cn_check_magic(dev, c, zynquart_cnm_state);
}
splx(s);
return (c);
@@ -1923,8 +1922,8 @@ zynquart_common_putc(dev_t dev, struct z
if (!READAHEAD_IS_FULL() &&
!(bus_space_read_4(iot, ioh, UART_CHANNEL_STS) & STS_REMPTY)) {
+ int cn_trapped __unused = 0;
- int __attribute__((__unused__))cn_trapped = 0;
cin = bus_space_read_4(iot, ioh, UART_TX_RX_FIFO);
cn_check_magic(dev, cin & 0xff, zynquart_cnm_state);
zynquart_readahead_in = (zynquart_readahead_in + 1) &
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: skrll Date: Thu Oct 27 07:57:46 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_uart.c Log Message: Fix build. Sprinkle some consistency To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/xilinx/zynq_uart.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Wed Oct 26 22:14:22 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq7000_clkc.c Log Message: Since this node is a child of a syscon, the reg property doesn't fully describe the device physical address. Use syscon accessors to read/write clock registers instead. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_clkc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Wed Oct 26 22:14:22 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq7000_clkc.c
Log Message:
Since this node is a child of a syscon, the reg property doesn't fully
describe the device physical address. Use syscon accessors to read/write
clock registers instead.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_clkc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq7000_clkc.c
diff -u src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.2 src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.3
--- src/sys/arch/arm/xilinx/zynq7000_clkc.c:1.2 Wed Oct 26 10:55:23 2022
+++ src/sys/arch/arm/xilinx/zynq7000_clkc.c Wed Oct 26 22:14:22 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_clkc.c,v 1.2 2022/10/26 10:55:23 jmcneill Exp $ */
+/* $NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.2 2022/10/26 10:55:23 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $");
#include
#include
@@ -41,29 +41,30 @@ __KERNEL_RCSID(0, "$NetBSD: zynq7000_clk
#include
#include
+#include
-#define ARM_PLL_CTRL 0x000
-#define DDR_PLL_CTRL 0x004
-#define IO_PLL_CTRL 0x008
+#define ARM_PLL_CTRL 0x100
+#define DDR_PLL_CTRL 0x104
+#define IO_PLL_CTRL 0x108
#define PLL_FDIV __BITS(18,12)
-#define ARM_CLK_CTRL 0x020
-#define ARM_CLK_CTRL_DIVISOR __BITS(13,8)
+#define ARM_CLK_CTRL 0x120
#define ARM_CLK_CTRL_CPU_1XCLKACT __BIT(27)
#define ARM_CLK_CTRL_CPU_2XCLKACT __BIT(26)
#define ARM_CLK_CTRL_CPU_3OR2XCLKACT __BIT(25)
#define ARM_CLK_CTRL_CPU_6OR4XCLKACT __BIT(24)
-#define APER_CLK_CTRL 0x02c
+#define ARM_CLK_CTRL_DIVISOR __BITS(13,8)
+#define APER_CLK_CTRL 0x12c
#define UART1_CPU_1XCLKACT __BIT(21)
#define UART0_CPU_1XCLKACT __BIT(20)
#define SDI1_CPU_1XCLKACT __BIT(11)
#define SDI0_CPU_1XCLKACT __BIT(10)
-#define SDIO_CLK_CTRL 0x050
-#define UART_CLK_CTRL 0x054
+#define SDIO_CLK_CTRL 0x150
+#define UART_CLK_CTRL 0x154
#define CLK_CTRL_DIVISOR __BITS(13,8)
#define CLK_CTRL_SRCSEL __BITS(5,4)
#define CLK_CTRL_CLKACT1 __BIT(1)
#define CLK_CTRL_CLKACT0 __BIT(0)
-#define CLK_621_TRUE 0x0C4
+#define CLK_621_TRUE 0x1C4
#define CLK_621_TRUE_EN __BIT(0)
enum xynq7000_clkid {
@@ -135,9 +136,7 @@ struct zynq7000_clkc_softc {
struct clk sc_clk[num_clkid];
u_int sc_ps_clk_frequency;
-
- bus_space_tag_t sc_bst;
- bus_space_handle_t sc_bsh;
+ struct syscon *sc_syscon;
};
CFATTACH_DECL_NEW(zynq7000_clkc, sizeof(struct zynq7000_clkc_softc),
@@ -169,7 +168,9 @@ zynq7000_clkc_get_rate_pll(struct zynq70
{
uint32_t val;
- val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);
+ syscon_lock(sc->sc_syscon);
+ val = syscon_read_4(sc->sc_syscon, reg);
+ syscon_unlock(sc->sc_syscon);
return sc->sc_ps_clk_frequency * __SHIFTOUT(val, PLL_FDIV);
}
@@ -181,7 +182,10 @@ zynq7000_clkc_get_rate_iop(struct zynq70
uint32_t val;
u_int prate, sel;
- val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);
+ syscon_lock(sc->sc_syscon);
+ val = syscon_read_4(sc->sc_syscon, reg);
+ syscon_unlock(sc->sc_syscon);
+
sel = __SHIFTOUT(val, CLK_CTRL_SRCSEL);
if (sel == 2) {
prate = zynq7000_clkc_clk_get_rate(sc,
@@ -211,15 +215,17 @@ zynq7000_clkc_clk_get_rate(void *priv, s
} else if (clk == >sc_clk[clkid_cpu_6or4x]) {
prate = zynq7000_clkc_clk_get_rate(sc,
>sc_clk[clkid_cpu_1x]);
- val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
- CLK_621_TRUE);
+ syscon_lock(sc->sc_syscon);
+ val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE);
+ syscon_unlock(sc->sc_syscon);
return (val & CLK_621_TRUE_EN) != 0 ?
prate * 6 : prate * 4;
} else if (clk == >sc_clk[clkid_cpu_3or2x]) {
prate = zynq7000_clkc_clk_get_rate(sc,
>sc_clk[clkid_cpu_1x]);
- val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
- CLK_621_TRUE);
+ syscon_lock(sc->sc_syscon);
+ val = syscon_read_4(sc->sc_syscon, CLK_621_TRUE);
+ syscon_unlock(sc->sc_syscon);
return (val & CLK_621_TRUE_EN) != 0 ?
prate * 3 : prate * 2;
} else if (clk == >sc_clk[clkid_cpu_2x]) {
@@ -229,9 +235,10 @@ zynq7000_clkc_clk_get_rate(void *priv, s
} else if (clk == >sc_clk[clkid_cpu_1x]) {
prate = zynq7000_clkc_clk_get_rate(sc,
>sc_clk[clkid_armpll]);
- val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
- ARM_CLK_CTRL);
- return prate / __SHIFTOUT(val, ARM_CLK_CTRL_DIVISOR);
+ syscon_lock(sc->sc_syscon);
+ val = syscon_read_4(sc->sc_syscon, ARM_CLK_CTRL);
+ syscon_unlock(sc->sc_syscon);
+ return prate / __SHIFTOUT(val, ARM_CLK_CTRL_DIVISOR) / 6;
} else if (clk == >sc_clk[clkid_sdio0] ||
clk == >sc_clk[clkid_sdio1]) {
return zynq7000_clkc_get_rate_iop(sc, SDIO_CLK_CTRL);
@@ -295,8 +302,10 @@
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Wed Oct 26 11:31:11 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_cemac.c
Log Message:
Inherit MAC address from Devicetree "local-mac-address" property.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq_cemac.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_cemac.c
diff -u src/sys/arch/arm/xilinx/zynq_cemac.c:1.3 src/sys/arch/arm/xilinx/zynq_cemac.c:1.4
--- src/sys/arch/arm/xilinx/zynq_cemac.c:1.3 Tue Oct 25 22:49:39 2022
+++ src/sys/arch/arm/xilinx/zynq_cemac.c Wed Oct 26 11:31:11 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_cemac.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $ */
+/* $NetBSD: zynq_cemac.c,v 1.4 2022/10/26 11:31:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -26,7 +26,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_cemac.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_cemac.c,v 1.4 2022/10/26 11:31:11 jmcneill Exp $");
#include "opt_soc.h"
@@ -41,6 +41,8 @@ __KERNEL_RCSID(0, "$NetBSD: zynq_cemac.c
#include
#include
+#include
+
#include
static const struct device_compatible_entry compat_data[] = {
@@ -61,11 +63,13 @@ cemac_attach(device_t parent, device_t s
{
struct fdt_attach_args * const faa = aux;
const int phandle = faa->faa_phandle;
+ prop_dictionary_t prop = device_properties(self);
bus_space_handle_t ioh;
char intrstr[128];
+ const char *macaddr;
bus_addr_t addr;
bus_size_t size;
- int error;
+ int error, len;
if (fdtbus_get_reg(phandle, 0, , ) != 0) {
aprint_error(": couldn't get registers\n");
@@ -90,6 +94,11 @@ cemac_attach(device_t parent, device_t s
return;
}
+ macaddr = fdtbus_get_prop(phandle, "local-mac-address", );
+ if (macaddr != NULL && len == ETHER_ADDR_LEN) {
+ prop_dictionary_set_data(prop, "mac-address", macaddr, len);
+ }
+
cemac_attach_common(self, faa->faa_bst, ioh, faa->faa_dmat, CEMAC_FLAG_GEM);
aprint_normal_dev(self, "interrupting on %s\n", intrstr);
}
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Wed Oct 26 11:31:11 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_cemac.c Log Message: Inherit MAC address from Devicetree "local-mac-address" property. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/xilinx/zynq_cemac.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Tue Oct 25 22:59:10 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq_platform.c
Log Message:
Remove unnecessary code in zynq_platform_device_register
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/xilinx/zynq_platform.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq_platform.c
diff -u src/sys/arch/arm/xilinx/zynq_platform.c:1.5 src/sys/arch/arm/xilinx/zynq_platform.c:1.6
--- src/sys/arch/arm/xilinx/zynq_platform.c:1.5 Sat Apr 24 23:36:29 2021
+++ src/sys/arch/arm/xilinx/zynq_platform.c Tue Oct 25 22:59:10 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_platform.c,v 1.5 2021/04/24 23:36:29 thorpej Exp $ */
+/* $NetBSD: zynq_platform.c,v 1.6 2022/10/25 22:59:10 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "arml2cc.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.5 2021/04/24 23:36:29 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.6 2022/10/25 22:59:10 jmcneill Exp $");
#include
#include
@@ -127,12 +127,6 @@ zynq_platform_early_putchar(char c)
static void
zynq_platform_device_register(device_t dev, void *aux)
{
- prop_dictionary_t dict = device_properties(dev);
-
- if (device_is_a(dev, "arma9tmr")) {
- prop_dictionary_set_uint32(dict, "frequency",
- ZYNQ_REF_FREQ / 4);
- }
}
static u_int
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Tue Oct 25 22:59:10 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq_platform.c Log Message: Remove unnecessary code in zynq_platform_device_register To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/xilinx/zynq_platform.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Tue Oct 25 22:52:48 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq7000_usb.c
Log Message:
Fixup mixed up log messages.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_usb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq7000_usb.c
diff -u src/sys/arch/arm/xilinx/zynq7000_usb.c:1.2 src/sys/arch/arm/xilinx/zynq7000_usb.c:1.3
--- src/sys/arch/arm/xilinx/zynq7000_usb.c:1.2 Wed Jan 27 03:10:20 2021
+++ src/sys/arch/arm/xilinx/zynq7000_usb.c Tue Oct 25 22:52:48 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_usb.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: zynq7000_usb.c,v 1.3 2022/10/25 22:52:48 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -26,7 +26,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_usb.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_usb.c,v 1.3 2022/10/25 22:52:48 jmcneill Exp $");
#include "opt_soc.h"
@@ -93,13 +93,13 @@ zynqusb_attach(device_t parent, device_t
}
if (fdtbus_intr_establish(phandle, 0, IPL_USB, IST_LEVEL, ehci_intr,
- hsc) == NULL) {
- aprint_error_dev(self, "failed to establish interrupt on %s\n",
+ hsc) == NULL) {
+ aprint_error("failed to establish interrupt on %s\n",
intrstr);
return;
}
- aprint_normal_dev(self, "interrupting on %s\n", intrstr);
zynqusb_attach_common(parent, self, faa->faa_bst, faa->faa_dmat,
addr, size, 0, ZYNQUSBC_IF_ULPI, ZYNQUSB_HOST);
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
}
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Tue Oct 25 22:52:48 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq7000_usb.c Log Message: Fixup mixed up log messages. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_usb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/xilinx
Module Name:src
Committed By: jmcneill
Date: Tue Oct 25 22:49:39 UTC 2022
Modified Files:
src/sys/arch/arm/xilinx: zynq7000_uart.c zynq_cemac.c
Log Message:
Fixup some mixed up log messages.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_uart.c \
src/sys/arch/arm/xilinx/zynq_cemac.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/xilinx/zynq7000_uart.c
diff -u src/sys/arch/arm/xilinx/zynq7000_uart.c:1.2 src/sys/arch/arm/xilinx/zynq7000_uart.c:1.3
--- src/sys/arch/arm/xilinx/zynq7000_uart.c:1.2 Wed Jan 27 03:10:20 2021
+++ src/sys/arch/arm/xilinx/zynq7000_uart.c Tue Oct 25 22:49:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_uart.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: zynq7000_uart.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Genetec Corporation. All rights reserved.
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_uart.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_uart.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $");
#include "opt_soc.h"
#include "opt_console.h"
@@ -75,13 +75,13 @@ zynquart_attach(device_t parent, device_
}
if (fdtbus_intr_establish(phandle, 0, IPL_SERIAL, IST_LEVEL,
- zynquartintr, device_private(self)) == NULL) {
- aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr);
+ zynquartintr, device_private(self)) == NULL) {
+ aprint_error(": failed to establish interrupt on %s\n", intrstr);
return;
}
- aprint_normal_dev(self, "interrupting on %s\n", intrstr);
zynquart_attach_common(parent, self, faa->faa_bst, addr, size, 0);
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
}
/*
Index: src/sys/arch/arm/xilinx/zynq_cemac.c
diff -u src/sys/arch/arm/xilinx/zynq_cemac.c:1.2 src/sys/arch/arm/xilinx/zynq_cemac.c:1.3
--- src/sys/arch/arm/xilinx/zynq_cemac.c:1.2 Wed Jan 27 03:10:20 2021
+++ src/sys/arch/arm/xilinx/zynq_cemac.c Tue Oct 25 22:49:39 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_cemac.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: zynq_cemac.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -26,7 +26,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: zynq_cemac.c,v 1.2 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_cemac.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $");
#include "opt_soc.h"
@@ -85,12 +85,12 @@ cemac_attach(device_t parent, device_t s
}
if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, cemac_intr,
- device_private(self)) == NULL) {
- aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr);
+ device_private(self)) == NULL) {
+ aprint_error(": failed to establish interrupt on %s\n", intrstr);
return;
}
- aprint_normal_dev(self, "interrupting on %s\n", intrstr);
cemac_attach_common(self, faa->faa_bst, ioh, faa->faa_dmat, CEMAC_FLAG_GEM);
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
}
CVS commit: src/sys/arch/arm/xilinx
Module Name:src Committed By: jmcneill Date: Tue Oct 25 22:49:39 UTC 2022 Modified Files: src/sys/arch/arm/xilinx: zynq7000_uart.c zynq_cemac.c Log Message: Fixup some mixed up log messages. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/xilinx/zynq7000_uart.c \ src/sys/arch/arm/xilinx/zynq_cemac.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
