Re: CVS commit: src/sys/arch/arm/arm
Oops, forgot to mention: No binary changes. On 2021/10/07 18:58, Rin Okuyama wrote: Module Name:src Committed By: rin Date: Thu Oct 7 09:58:27 UTC 2021 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_armv5_ec.S Log Message: Reduce diff with cpufunc_asm_armv5.S, from which this file was derived. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_armv5_ec.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: src/sys/arch/arm/arm
On 2020/11/12 6:52, matthew green wrote: "Rin Okuyama" writes: Module Name:src Committed By: rin Date: Tue Nov 10 21:40:07 UTC 2020 Modified Files: src/sys/arch/arm/arm: cpu_exec.c Log Message: Test (epp->ep_esch->es_emul != _netbsd) instead of nice, this is a step forward. an optimisation on it could be to remove this test entirely if neither MODULAR or COMAPT_NETBSD32 are set, as it will always be false there. Ah, yes. I will commit after some test. Thanks! rin
re: CVS commit: src/sys/arch/arm/arm
"Rin Okuyama" writes: > Module Name: src > Committed By: rin > Date: Tue Nov 10 21:40:07 UTC 2020 > > Modified Files: > src/sys/arch/arm/arm: cpu_exec.c > > Log Message: > Test (epp->ep_esch->es_emul != _netbsd) instead of nice, this is a step forward. an optimisation on it could be to remove this test entirely if neither MODULAR or COMAPT_NETBSD32 are set, as it will always be false there. thanks. .mrg.
Re: CVS commit: src/sys/arch/arm/arm
On Sat, Mar 09, 2013 at 10:10:45AM +, Michael van Elst wrote: Module Name: src Committed By: mlelstv Date: Sat Mar 9 10:10:45 UTC 2013 Modified Files: src/sys/arch/arm/arm: disksubr_acorn.c Log Message: Errors are supposed to be negative errno numbers, not -1 which is interpreted as EPERM. Hmmm... NetBSD usually uses +ve errno values. David -- David Laight: da...@l8s.co.uk
Re: CVS commit: src/sys/arch/arm/arm
On Dec 27, 2012, at 7:48 PM, SAITOH Masanobu wrote: Module Name: src Committed By: msaitoh Date: Fri Dec 28 03:48:00 UTC 2012 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: Enable DCache Streaming Switch and Write Allocate. This change improve system performance significantly. How does this affect L2 and DMA?
Re: CVS commit: src/sys/arch/arm/arm
Hi, matt. (2012/12/28 14:10), Matt Thomas wrote: On Dec 27, 2012, at 7:48 PM, SAITOH Masanobu wrote: Module Name:src Committed By: msaitoh Date: Fri Dec 28 03:48:00 UTC 2012 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: Enable DCache Streaming Switch and Write Allocate. This change improve system performance significantly. How does this affect L2 and DMA? Both are not affected. -- --- SAITOH Masanobu (msai...@execsw.org msai...@netbsd.org)
Re: CVS commit: src/sys/arch/arm/arm
On Sun, Dec 23, 2012 at 01:26:21PM +, Matt Thomas wrote: Module Name: src Committed By: matt Date: Sun Dec 23 13:26:21 UTC 2012 Modified Files: src/sys/arch/arm/arm: cpu_in_cksum_fold.S Log Message: Conditional execution still takes one cycle per skipped instruction. branch to unlikely cases instead of conditionally skipping them. Or more for 'ldm' and 'stm' - esp. I think on strongarm! Conditional execution might also be a full pipeline stall, rather than a branch which is likely (hopefully) to be predicted correctly. David -- David Laight: da...@l8s.co.uk