CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Thu Mar 27 21:11:11 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: param.h Log Message: #define ALIGNBYTES __ALIGNBYTES To generate a diff of this commit: cvs rdiff -u -r1.12.12.3 -r1.12.12.4 src/sys/arch/arm/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/param.h diff -u src/sys/arch/arm/include/param.h:1.12.12.3 src/sys/arch/arm/include/param.h:1.12.12.4 --- src/sys/arch/arm/include/param.h:1.12.12.3 Thu Mar 27 01:04:39 2014 +++ src/sys/arch/arm/include/param.h Thu Mar 27 21:11:11 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.12.12.3 2014/03/27 01:04:39 matt Exp $ */ +/* $NetBSD: param.h,v 1.12.12.4 2014/03/27 21:11:11 matt Exp $ */ /* * Copyright (c) 1994,1995 Mark Brinicombe. @@ -148,7 +148,7 @@ #define MID_MACHINE MID_ARM6 /* ARM-specific macro to align a stack pointer (downwards). */ -#define ALIGNBYTES (__ALIGNBYTES + 1) +#define ALIGNBYTES __ALIGNBYTES #define ALIGN(p) (((uintptr_t)(p) + ALIGNBYTES) ~ALIGNBYTES) #define ALIGNED_POINTER(p,t) (((uintptr_t)(p) % sizeof(t)) == 0) #define STACKALIGNBYTES (8 - 1)
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Wed Mar 26 22:44:42 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: cdefs.h Log Message: Make the minimal alignment 8 if EABI or ldrd/strd are supported. To generate a diff of this commit: cvs rdiff -u -r1.3.38.1 -r1.3.38.2 src/sys/arch/arm/include/cdefs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/cdefs.h diff -u src/sys/arch/arm/include/cdefs.h:1.3.38.1 src/sys/arch/arm/include/cdefs.h:1.3.38.2 --- src/sys/arch/arm/include/cdefs.h:1.3.38.1 Thu Dec 19 01:17:06 2013 +++ src/sys/arch/arm/include/cdefs.h Wed Mar 26 22:44:41 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: cdefs.h,v 1.3.38.1 2013/12/19 01:17:06 matt Exp $ */ +/* $NetBSD: cdefs.h,v 1.3.38.2 2014/03/26 22:44:41 matt Exp $ */ #ifndef _ARM_CDEFS_H_ #define _ARM_CDEFS_H_ @@ -40,8 +40,8 @@ #define _ARM_ARCH_DWORD_OK #endif -#ifdef __ARM_EABI__ -#define __ALIGNBYTES (8 - 1) +#if defined(__ARM_EABI__) || defined(_ARM_ARCH_DWORD_OK) +#define __ALIGNBYTES (sizeof(long long) - 1) #else #define __ALIGNBYTES (sizeof(int) - 1) #endif
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Thu Mar 27 01:04:39 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: param.h Log Message: Make ALIGNBYTES use __ALIGNBYTES To generate a diff of this commit: cvs rdiff -u -r1.12.12.2 -r1.12.12.3 src/sys/arch/arm/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/param.h diff -u src/sys/arch/arm/include/param.h:1.12.12.2 src/sys/arch/arm/include/param.h:1.12.12.3 --- src/sys/arch/arm/include/param.h:1.12.12.2 Sat Feb 15 16:30:23 2014 +++ src/sys/arch/arm/include/param.h Thu Mar 27 01:04:39 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.12.12.2 2014/02/15 16:30:23 matt Exp $ */ +/* $NetBSD: param.h,v 1.12.12.3 2014/03/27 01:04:39 matt Exp $ */ /* * Copyright (c) 1994,1995 Mark Brinicombe. @@ -148,7 +148,7 @@ #define MID_MACHINE MID_ARM6 /* ARM-specific macro to align a stack pointer (downwards). */ -#define ALIGNBYTES 3 +#define ALIGNBYTES (__ALIGNBYTES + 1) #define ALIGN(p) (((uintptr_t)(p) + ALIGNBYTES) ~ALIGNBYTES) #define ALIGNED_POINTER(p,t) (((uintptr_t)(p) % sizeof(t)) == 0) #define STACKALIGNBYTES (8 - 1)
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Wed Mar 26 01:15:48 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: armreg.h Log Message: sync with HEAD To generate a diff of this commit: cvs rdiff -u -r1.41.12.2 -r1.41.12.3 src/sys/arch/arm/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/armreg.h diff -u src/sys/arch/arm/include/armreg.h:1.41.12.2 src/sys/arch/arm/include/armreg.h:1.41.12.3 --- src/sys/arch/arm/include/armreg.h:1.41.12.2 Mon Mar 24 18:43:40 2014 +++ src/sys/arch/arm/include/armreg.h Wed Mar 26 01:15:48 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.41.12.2 2014/03/24 18:43:40 matt Exp $ */ +/* $NetBSD: armreg.h,v 1.41.12.3 2014/03/26 01:15:48 matt Exp $ */ /* * Copyright (c) 1998, 2001 Ben Harris @@ -58,13 +58,24 @@ #define PSR_V_bit (1 28) /* overflow */ #define PSR_Q_bit (1 27) /* saturation */ +#define PSR_IT1_bit (1 26) +#define PSR_IT0_bit (1 25) +#define PSR_J_bit (1 24) /* Jazelle mode */ +#define PSR_GE_bits (15 16) /* SIMD GE bits */ +#define PSR_IT7_bit (1 15) +#define PSR_IT6_bit (1 14) +#define PSR_IT5_bit (1 13) +#define PSR_IT4_bit (1 12) +#define PSR_IT3_bit (1 11) +#define PSR_IT2_bit (1 10) +#define PSR_E_BIT (1 9) /* Endian state */ +#define PSR_A_BIT (1 8) /* Async abort disable */ #define I32_bit (1 7) /* IRQ disable */ #define F32_bit (1 6) /* FIQ disable */ -#define IF32_bits (3 6) /* IRQ/FIQ disable */ +#define IF32_bits (3 6) /* IRQ/FIQ disable */ #define PSR_T_bit (1 5) /* Thumb state */ -#define PSR_J_bit (1 24) /* Java mode */ #define PSR_MODE 0x001f /* mode mask */ #define PSR_USR26_MODE 0x @@ -258,6 +269,11 @@ #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ /* CPUID registers */ +#define ARM_ISA3_SYNCHPRIM_MASK 0xf000 +#define ARM_ISA4_SYNCHPRIM_MASK 0x00f0 +#define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX +#define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH +#define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD #define ARM_PFR0_THUMBEE_MASK 0xf000 #define ARM_PFR1_GTIMER_MASK 0x000f #define ARM_PFR1_VIRT_MASK 0xf000 @@ -347,6 +363,9 @@ #define CPU_CONTROL_VECRELOC 0x2000 /* V: Vector relocation */ #define CPU_CONTROL_ROUNDROBIN 0x4000 /* RR: Predictable replacement */ #define CPU_CONTROL_V4COMPAT 0x8000 /* L4: ARMv4 compat LDR R15 etc */ +#define CPU_CONTROL_HA_ENABLE 0x0002 /* HA: Hardware Access flag enable */ +#define CPU_CONTROL_WXN_ENABLE 0x0008 /* WXN: Write Execute Never */ +#define CPU_CONTROL_UWXN_ENABLE 0x0010 /* UWXN: User Write eXecute Never */ #define CPU_CONTROL_FI_ENABLE 0x0020 /* FI: Low interrupt latency */ #define CPU_CONTROL_UNAL_ENABLE 0x0040 /* U: unaligned data access */ #define CPU_CONTROL_XP_ENABLE 0x0080 /* XP: extended page table */ @@ -368,6 +387,13 @@ #define CPACR_RESERVED 2 #define CPACR_ALL 3 /* Privileged and User mode access */ +/* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */ +#define NSACR_SMP 0x0004 /* ACTRL.SMP is writeable (!A8) */ +#define NSACR_L2ERR 0x0002 /* L2ECTRL is writeable (!A8) */ +#define NSACR_ASEDIS 0x8000 /* Deny Advanced SIMD Ext. */ +#define NSACR_D32DIS 0x4000 /* Deny VFP regs 15-31 */ +#define NSACR_CPn(n) (1 (n)) /* NonSecure access allowed */ + /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ #define ARM11X6_AUXCTL_RS 0x0001 /* return stack */ #define ARM11X6_AUXCTL_DB 0x0002 /* dynamic branch prediction */ @@ -521,7 +547,11 @@ #define FAULT_PERM_S0x0d /* Permission -- Section */ #define FAULT_PERM_P0x0f /* Permission -- Page */ -#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ +#define FAULT_LPAE 0x0200 /* (SW) used long descriptors */ +#define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */ +#define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */ +#define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */ +#define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */ /* * Address of the vector page, low and high versions. @@ -542,7 +572,21 @@ #define INSN_SIZE 4 /* Always 4 bytes */ #define INSN_COND_MASK 0xf000 /* Condition mask */ -#define INSN_COND_AL 0xe000 /* Always condition */ +#define INSN_COND_EQ 0 /* Z == 1 */ +#define INSN_COND_NE 1 /* Z == 0 */ +#define INSN_COND_CS 2 /* C == 1 */ +#define INSN_COND_CC 3 /* C == 0 */ +#define INSN_COND_MI 4 /* N == 1 */ +#define INSN_COND_PL 5 /* N == 0 */ +#define INSN_COND_VS 6 /* V == 1 */ +#define INSN_COND_VC 7 /* V == 0 */ +#define INSN_COND_HI 8 /* C == 1 Z == 0 */ +#define INSN_COND_LS 9 /* C == 0 || Z == 1 */ +#define INSN_COND_GE 10 /* N == V */ +#define INSN_COND_LT 11 /* N != V */ +#define INSN_COND_GT 12 /* Z ==
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include/arm32
Module Name:src Committed By: matt Date: Mon Mar 24 16:50:57 UTC 2014 Modified Files: src/sys/arch/arm/include/arm32 [matt-nb5-mips64]: pmap.h Log Message: Define PMAP_KMPAGE To generate a diff of this commit: cvs rdiff -u -r1.88.10.1 -r1.88.10.2 src/sys/arch/arm/include/arm32/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/arm32/pmap.h diff -u src/sys/arch/arm/include/arm32/pmap.h:1.88.10.1 src/sys/arch/arm/include/arm32/pmap.h:1.88.10.2 --- src/sys/arch/arm/include/arm32/pmap.h:1.88.10.1 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/include/arm32/pmap.h Mon Mar 24 16:50:56 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.88.10.1 2014/02/15 16:18:36 matt Exp $ */ +/* $NetBSD: pmap.h,v 1.88.10.2 2014/03/24 16:50:56 matt Exp $ */ /* * Copyright (c) 2002, 2003 Wasabi Systems, Inc. @@ -305,8 +305,8 @@ void pmap_remove_all(struct pmap *); bool pmap_extract(struct pmap *, vaddr_t, paddr_t *); #define PMAP_NEED_PROCWR -#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ -#define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ +#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ +#define PMAP_KMPAGE 0x0800 /* enable the PMAP_KMPAGE flag */ #if (ARM_MMU_V6 + ARM_MMU_V7) 0 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td))
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include/arm32
Module Name:src Committed By: matt Date: Mon Mar 24 18:42:50 UTC 2014 Modified Files: src/sys/arch/arm/include/arm32 [matt-nb5-mips64]: vmparam.h Log Message: Deal with those arms who only need one type of freelist. To generate a diff of this commit: cvs rdiff -u -r1.23.12.1 -r1.23.12.2 src/sys/arch/arm/include/arm32/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/arm32/vmparam.h diff -u src/sys/arch/arm/include/arm32/vmparam.h:1.23.12.1 src/sys/arch/arm/include/arm32/vmparam.h:1.23.12.2 --- src/sys/arch/arm/include/arm32/vmparam.h:1.23.12.1 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/include/arm32/vmparam.h Mon Mar 24 18:42:50 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.23.12.1 2014/02/15 16:18:36 matt Exp $ */ +/* $NetBSD: vmparam.h,v 1.23.12.2 2014/03/24 18:42:50 matt Exp $ */ /* * Copyright (c) 2001, 2002 Wasabi Systems, Inc. @@ -112,8 +112,12 @@ extern vaddr_t virtual_end; (VM_NFREELIST == 1 \ ? VM_PGCOLOR_BUCKET(pg) : (*arm_page_to_pggroup)((pg), (ncolors))) +#ifdef PMAP_NEED_ALLOC_POOLPAGE #define VM_FREELIST_NORMALOK_P(lcv) \ ((lcv) == VM_FREELIST_DEFAULT || (lcv) != arm_poolpage_vmfreelist) +#else +#define VM_FREELIST_NORMALOK_P(lcv) true +#endif struct vm_page; extern size_t (*arm_page_to_pggroup)(struct vm_page *, size_t);
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Mon Mar 24 18:43:40 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: armreg.h Log Message: merge l2ctrl from head To generate a diff of this commit: cvs rdiff -u -r1.41.12.1 -r1.41.12.2 src/sys/arch/arm/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/armreg.h diff -u src/sys/arch/arm/include/armreg.h:1.41.12.1 src/sys/arch/arm/include/armreg.h:1.41.12.2 --- src/sys/arch/arm/include/armreg.h:1.41.12.1 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/include/armreg.h Mon Mar 24 18:43:40 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.41.12.1 2014/02/15 16:18:36 matt Exp $ */ +/* $NetBSD: armreg.h,v 1.41.12.2 2014/03/24 18:43:40 matt Exp $ */ /* * Copyright (c) 1998, 2001 Ben Harris @@ -597,6 +597,10 @@ #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ +/* Defines for ARM Cortex A7/A15 L2CTRL */ +#define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1 +#define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present + /* Translate Table Base Control Register */ #define TTBCR_S_EAE __BIT(31) // Extended Address Extension #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 @@ -765,6 +769,8 @@ ARMREG_WRITE_INLINE(tlbimva, p15,0,%0,c ARMREG_WRITE_INLINE(tlbiasid, p15,0,%0,c8,c7,2) /* Invalidate unified TLB by ASID */ ARMREG_WRITE_INLINE(tlbimvaa, p15,0,%0,c8,c7,3) /* Invalidate unified TLB by MVA, all ASID */ /* cp15 c9 registers */ +ARMREG_READ_INLINE(l2ctrl, p15,1,%0,c9,c0,2) /* A7/A15 L2 Control Register */ +ARMREG_WRITE_INLINE(l2ctrl, p15,1,%0,c9,c0,2) /* A7/A15 L2 Control Register */ ARMREG_READ_INLINE(pmcr, p15,0,%0,c9,c12,0) /* PMC Control Register */ ARMREG_WRITE_INLINE(pmcr, p15,0,%0,c9,c12,0) /* PMC Control Register */ ARMREG_READ_INLINE(pmcntenset, p15,0,%0,c9,c12,1) /* PMC Count Enable Set */
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Wed Feb 26 00:59:27 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: elf_machdep.h Log Message: Use right name To generate a diff of this commit: cvs rdiff -u -r1.7.78.2 -r1.7.78.3 src/sys/arch/arm/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/elf_machdep.h diff -u src/sys/arch/arm/include/elf_machdep.h:1.7.78.2 src/sys/arch/arm/include/elf_machdep.h:1.7.78.3 --- src/sys/arch/arm/include/elf_machdep.h:1.7.78.2 Tue Feb 25 00:05:49 2014 +++ src/sys/arch/arm/include/elf_machdep.h Wed Feb 26 00:59:27 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.7.78.2 2014/02/25 00:05:49 matt Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.7.78.3 2014/02/26 00:59:27 matt Exp $ */ #ifndef _ARM_ELF_MACHDEP_H_ #define _ARM_ELF_MACHDEP_H_ @@ -146,7 +146,7 @@ #ifdef _KERNEL #ifdef ELFSIZE -#define ELF_MD_COREDUMP_FUNC ELFNAME2(arm_netbsd,coredump_setup) +#define ELF_MD_COREDUMP_SETUP ELFNAME2(arm_netbsd,coredump_setup) #endif struct exec_package;
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Sat Feb 15 16:30:24 UTC 2014 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: param.h Log Message: Fix typo STACK_ALIGNBYTES - STACKALIGNBYTES To generate a diff of this commit: cvs rdiff -u -r1.12.12.1 -r1.12.12.2 src/sys/arch/arm/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/param.h diff -u src/sys/arch/arm/include/param.h:1.12.12.1 src/sys/arch/arm/include/param.h:1.12.12.2 --- src/sys/arch/arm/include/param.h:1.12.12.1 Sat Feb 15 16:18:36 2014 +++ src/sys/arch/arm/include/param.h Sat Feb 15 16:30:23 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.12.12.1 2014/02/15 16:18:36 matt Exp $ */ +/* $NetBSD: param.h,v 1.12.12.2 2014/02/15 16:30:23 matt Exp $ */ /* * Copyright (c) 1994,1995 Mark Brinicombe. @@ -151,7 +151,7 @@ #define ALIGNBYTES 3 #define ALIGN(p) (((uintptr_t)(p) + ALIGNBYTES) ~ALIGNBYTES) #define ALIGNED_POINTER(p,t) (((uintptr_t)(p) % sizeof(t)) == 0) -#define STACK_ALIGNBYTES (8 - 1) +#define STACKALIGNBYTES (8 - 1) #define STACKALIGN(p) ((uintptr_t)(p) ~STACKALIGNBYTES) #define DEV_BSHIFT 9 /* log2(DEV_BSIZE) */
CVS commit: [matt-nb5-mips64] src/sys/arch/arm/include
Module Name:src Committed By: matt Date: Thu Dec 19 01:17:06 UTC 2013 Modified Files: src/sys/arch/arm/include [matt-nb5-mips64]: cdefs.h Log Message: Pull from HEAD (for post armv6 defines). To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.3.38.1 src/sys/arch/arm/include/cdefs.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/include/cdefs.h diff -u src/sys/arch/arm/include/cdefs.h:1.3 src/sys/arch/arm/include/cdefs.h:1.3.38.1 --- src/sys/arch/arm/include/cdefs.h:1.3 Wed Oct 17 19:53:41 2007 +++ src/sys/arch/arm/include/cdefs.h Thu Dec 19 01:17:06 2013 @@ -1,15 +1,31 @@ -/* $NetBSD: cdefs.h,v 1.3 2007/10/17 19:53:41 garbled Exp $ */ +/* $NetBSD: cdefs.h,v 1.3.38.1 2013/12/19 01:17:06 matt Exp $ */ -#ifndef _MACHINE_CDEFS_H_ -#define _MACHINE_CDEFS_H_ +#ifndef _ARM_CDEFS_H_ +#define _ARM_CDEFS_H_ -#if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) +#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) || \ +defined (__ARM_ARCH_7R__) || defined (__ARM_ARCH_7M__) || \ +defined (__ARM_ARCH_7EM__) /* 7R, 7M, 7EM are for non MMU arms */ +#define _ARM_ARCH_7 +#endif + +#if defined (_ARM_ARCH_7) || defined (__ARM_ARCH_6T2__) +#define _ARM_ARCH_T2 /* Thumb2 */ +#endif + +#if defined (_ARM_ARCH_T2) || defined (__ARM_ARCH_6__) || \ +defined (__ARM_ARCH_6J__) || defined (__ARM_ARCH_6K__) || \ +defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) || \ +defined (__ARM_ARCH_6ZM__) #define _ARM_ARCH_6 #endif -#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5__) || \ -defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5TE__) || \ -defined (__ARM_ARCH_5TEJ__) +#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5T__) || \ +defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__) +#define _ARM_ARCH_5T +#endif + +#if defined (_ARM_ARCH_6) || defined (_ARM_ARCH_5T) || defined (__ARM_ARCH_5__) #define _ARM_ARCH_5 #endif @@ -17,4 +33,17 @@ #define _ARM_ARCH_4T #endif -#endif /* !_MACHINE_CDEFS_H_ */ +#if defined (_ARM_ARCH_T2) || \ +(!defined (__thumb__) \ + (defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5TE__) || \ + defined (__ARM_ARCH_5TEJ__))) +#define _ARM_ARCH_DWORD_OK +#endif + +#ifdef __ARM_EABI__ +#define __ALIGNBYTES (8 - 1) +#else +#define __ALIGNBYTES (sizeof(int) - 1) +#endif + +#endif /* !_ARM_CDEFS_H_ */
