Module Name: src
Committed By: matt
Date: Wed Dec 13 01:33:19 UTC 2017
Added Files:
src/sys/external/gpl2/dts/dist/arch/arm/boot/dts [matt-nb8-mediatek]:
mtkatlas.dts mtkmercury.dtsi
Log Message:
DTS files for the Mediatek ATLAS board
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1.2.1 \
src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkatlas.dts \
src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkmercury.dtsi
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkatlas.dts
diff -u /dev/null src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkatlas.dts:1.1.2.1
--- /dev/null Wed Dec 13 01:33:19 2017
+++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkatlas.dts Wed Dec 13 01:33:19 2017
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2014-2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "mtkmercury.dtsi"
+
+/ {
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x18000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ /* chosen */
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+
+/* reg = <0 0x40000000 0 0x20000000>; */
+/* bootargs = "console=ttyS0,921600n1 root=/dev/ram initrd=0x44000200,0x200000"; */
+
+&pwrap {
+ status = "okay";
+
+ pmic: mt6392 {
+ compatible = "mediatek,mt6392";
+
+ mediatek,system-power-controller;
+
+ mt6392keys: mt6392keys {
+ compatible = "mediatek,mt6392-keys";
+ mediatek,pwrkey-code = <116>;
+ mediatek,homekey-code = <114>;
+ mediatek,long-press-mode = <0>;
+ mediatek,long-press-duration = <0>;
+ };
+
+ mt6392pmic: mt6392pmic {
+ compatible = "mediatek,mt6392-pmic";
+ };
+
+ mt6392regulator: mt6392regulator {
+ compatible = "mediatek,mt6392-regulator";
+
+ mt6392_vproc_reg: buck_vproc {
+ regulator-name = "vproc";
+ regulator-min-microvolt = < 700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vsys_reg: buck_vsys {
+ regulator-name = "vsys";
+ regulator-min-microvolt = <1400000>;
+ regulator-max-microvolt = <2987500>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcore_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = < 700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vxo22_reg: ldo_vxo22 {
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <110>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vaud22_reg: ldo_vaud22 {
+ regulator-name = "vaud22";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcama_reg: ldo_vcama {
+ regulator-name = "vcama";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vaud28_reg: ldo_vaud28 {
+ regulator-name = "vaud28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vadc18_reg: ldo_vadc18 {
+ regulator-name = "vadc18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcn35_reg: ldo_vcn35 {
+ regulator-name = "vcn35";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vio28_reg: ldo_vio28 {
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vusb_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vmc_reg: ldo_vmc {
+ regulator-name = "vmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-boot-on;
+ };
+
+ mt6392_vmch_reg: ldo_vmch {
+ regulator-name = "vmch";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-boot-on;
+ };
+
+ mt6392_vemc3v3_reg: ldo_vemc3v3 {
+ regulator-name = "vemc3v3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-boot-on;
+ };
+
+ mt6392_vgp1_reg: ldo_vgp1 {
+ regulator-name = "vgp1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vgp2_reg: ldo_vgp2 {
+ regulator-name = "vgp2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vcn18_reg: ldo_vcn18 {
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vcamaf_reg: ldo_vcamaf {
+ regulator-name = "vcamaf";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vm_reg: ldo_vm {
+ regulator-name = "vm";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1390000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vio18_reg: ldo_vio18 {
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ mt6392_vcamd_reg: ldo_vcamd {
+ regulator-name = "vcamd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vcamio_reg: ldo_vcamio {
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vm25_reg: ldo_vm25 {
+ regulator-name = "vm25";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+
+ mt6392_vefuse_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-enable-ramp-delay = <264>;
+ };
+ };
+
+ pio6392: pinctrl@c000 {
+ compatible = "mediatek,mt6392-pinctrl";
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ typec: typec {
+ compatible = "mediatek,mt6392-typec";
+ status = "disabled";
+ };
+ };
+};
+
+&feth {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&u2port0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&u2port1 {
+ status = "okay";
+};
Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkmercury.dtsi
diff -u /dev/null src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkmercury.dtsi:1.1.2.1
--- /dev/null Wed Dec 13 01:33:19 2017
+++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mtkmercury.dtsi Wed Dec 13 01:33:19 2017
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Eddie Huang <eddie.hu...@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Mercury";
+ compatible = "mediatek,mercury";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_on = <0x84000003>;
+ };
+
+ clocks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ topckgen: topckgen@10000000 {
+ compatible = "mediatek,mercury-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mercury-pinctrl";
+ reg = <0 0x10005000 0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eint: interrupt-controller@1000b000 {
+ compatible = "mediatek,mercury-eint";
+ reg = <0 0x1000b000 0 0x1000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ gic: interrupt-controller@10310000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+ <0 0x10320000 0 0x1000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mercury-pwrap";
+ reg = <0 0x1000f000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ uart0: uart0@11005000 {
+ compatible = "mediatek,mercury-uart";
+ reg = <0 0x11005000 0 0x1000>; /* UART base */
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; /* UART IRQ */
+ };
+
+ uart1: uart1@11006000 {
+ compatible = "mediatek,mercury-uart";
+ reg = <0 0x11006000 0 0x1000>; /* UART base */
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; /* UART IRQ */
+ };
+
+ uart2: uart2@11007000 {
+ compatible = "mediatek,mercury-uart";
+ reg = <0 0x11007000 0 0x1000>; /* UART base */
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_LOW>; /* UART IRQ */
+ };
+
+ pwm: pwm@11008000 {
+ compatible = "mediatek,mercury-pwm";
+ reg = <0 0x11008000 0 0x1000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ i2c0: i2c@11009000 {
+ compatible = "mediatek,mercury-i2c";
+ reg = <0 0x11009000 0 0x90>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@1100a000 {
+ compatible = "mediatek,mercury-i2c";
+ reg = <0 0x1100a000 0 0x90>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1100b000 {
+ compatible = "mediatek,mercury-i2c";
+ reg = <0 0x1100b000 0 0x90>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi: spi@1100c000 {
+ compatible = "mediatek,mercury-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100c000 0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ feth: feth@11180000 {
+ compatible = "mediatek,mercury-feth";
+ reg = <0 0x11180080 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11120000 {
+ compatible = "mediatek,mercury-mmc";
+ reg = <0 0x11120000 0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ mmc1: mmc@11130000 {
+ compatible = "mediatek,mercury-mmc";
+ reg = <0 0x11130000 0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ usb0: usb0@11100000 {
+ compatible = "mediatek,mercury-usb20";
+ reg = <0 0x11100000 0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-names = "usb0_in_72";
+ /* clocks = <&topckgen CLK_TOP_USB_PHY48M>, */
+ /* <&topckgen CLK_TOP_USBIF>, */
+ /* <&topckgen CLK_TOP_USB>, */
+ /* <&topckgen CLK_TOP_USB_1P>; */
+ /* clock-names = "usbpll", "usbmcu", "usb", "icusb"; */
+ phys = <&u2port0 0>;
+ phy-names = "usb0";
+ status = "disabled";
+ };
+
+ u2port0: usb-phy0@11110800 {
+ compatible = "mediatek,mercury-usb20-phy";
+ reg = <0 0x11110800 0 0x800>;
+ reg-names = "port0";
+ /* clocks = <&clk26m>; */
+ /* clock-names = "ref"; */
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ usb1: usb1@11190000 {
+ compatible = "mediatek,mercury-usb20";
+ reg = <0 0x11190000 0 0x1000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-names = "usb1_in_210";
+ /* clocks = <&topckgen CLK_TOP_USB_PHY48M>, */
+ /* <&topckgen CLK_TOP_USBIF>, */
+ /* <&topckgen CLK_TOP_USB>, */
+ /* <&topckgen CLK_TOP_USB_1P>; */
+ /* clock-names = "usbpll", "usbmcu", "usb", "icusb"; */
+ phys = <&u2port1 0>;
+ phy-names = "usb1";
+ status = "disabled";
+ };
+
+ u2port1: usb-phy1@11110900 {
+ compatible = "mediatek,mercury-usb20-phy";
+ reg = <0 0x11110900 0 0x800>;
+ reg-names = "port1";
+ /* clocks = <&clk26m>; */
+ /* clock-names = "ref"; */
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
+};
