CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Wed Aug 5 18:26:17 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-8]: specialreg.h Log Message: Accidently not commited for ticket #1595: sys/arch/x86/include/specialreg.h 1.129 via patch Add six errata for AMD Family 17h (Ryzen etc). To generate a diff of this commit: cvs rdiff -u -r1.98.2.20 -r1.98.2.21 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.20 src/sys/arch/x86/include/specialreg.h:1.98.2.21 --- src/sys/arch/x86/include/specialreg.h:1.98.2.20 Wed Aug 5 16:02:53 2020 +++ src/sys/arch/x86/include/specialreg.h Wed Aug 5 18:26:17 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98.2.20 2020/08/05 16:02:53 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.98.2.21 2020/08/05 18:26:17 martin Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -1055,6 +1055,9 @@ #define NB_CFG_INITAPICCPUIDLO (1ULL << 54) #define MSR_LS_CFG 0xc0011020 +#define LS_CFG_ERRATA_1033 __BIT(4) +#define LS_CFG_ERRATA_793 __BIT(15) +#define LS_CFG_ERRATA_1095 __BIT(57) #define LS_CFG_DIS_LS2_SQUISH 0x0200 #define LS_CFG_DIS_SSB_F15H 0x0040ULL #define LS_CFG_DIS_SSB_F16H 0x0002ULL @@ -1063,6 +1066,7 @@ #define MSR_IC_CFG 0xc0011021 #define IC_CFG_DIS_SEQ_PREFETCH 0x0800 #define IC_CFG_DIS_IND 0x4000 +#define IC_CFG_ERRATA_776 __BIT(26) #define MSR_DC_CFG 0xc0011022 #define DC_CFG_DIS_CNV_WC_SSO 0x0008 @@ -1077,9 +1081,16 @@ #define BU_CFG_WBPFSMCCHKDIS 0x2000ULL #define BU_CFG_WBENHWSBDIS 0x0001ULL +#define MSR_FP_CFG 0xc0011028 +#define FP_CFG_ERRATA_1049 __BIT(4) + #define MSR_DE_CFG 0xc0011029 #define DE_CFG_ERRATA_721 0x0001 #define DE_CFG_LFENCE_SERIALIZE __BIT(1) +#define DE_CFG_ERRATA_1021 __BIT(13) + +#define MSR_LS_CFG2 0xc001102d +#define LS_CFG2_ERRATA_1091 __BIT(34) /* AMD Family10h MSRs */ #define MSR_OSVW_ID_LENGTH 0xc0010140
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Wed Aug 5 16:02:53 UTC 2020 Modified Files: src/sys/arch/x86/include [netbsd-8]: specialreg.h Log Message: Pull up the following revisions, requested by msaitoh in ticket #1588: sys/arch/x86/include/specialreg.h 1.162-1.168 via patch - AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL". - Add some bit definitions of AMD's CPUID Fn8000_001f Encrypted Memory features. - Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit. - Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE. - Add some definitions for Intel: - Add CPUID leaf 6 %eax bit 19 for HW_FEEDBACK* and IA32_PACKAGE_TERM* MSRs. - Add CPUID leaf 7 %ecx bit 31 for Protection Keys. - Add definition of Load only TLB and Store only TLB. - Add IF_PSCHANGE_MC_NO bit of IA32_ARCH_CAPABILITIES - Fix HWP_IGNIDL. - Add CPUID 7 %edx bit 9 "SRBDS_CTRL" - Modify comment. Style and fix typo. To generate a diff of this commit: cvs rdiff -u -r1.98.2.19 -r1.98.2.20 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.19 src/sys/arch/x86/include/specialreg.h:1.98.2.20 --- src/sys/arch/x86/include/specialreg.h:1.98.2.19 Wed Apr 15 14:25:09 2020 +++ src/sys/arch/x86/include/specialreg.h Wed Aug 5 16:02:53 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98.2.19 2020/04/15 14:25:09 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.98.2.20 2020/08/05 16:02:53 martin Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -247,10 +247,10 @@ ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4))) /* CPUID Fn0001 %ebx */ -#define CPUID_BRAND_INDEX __BITS(7,0) -#define CPUID_CLFLUSH_SIZE __BITS(15,8) -#define CPUID_HTT_CORES __BITS(23,16) -#define CPUID_LOCAL_APIC_ID __BITS(31,24) +#define CPUID_BRAND_INDEX __BITS(7,0) +#define CPUID_CLFLUSH_SIZE __BITS(15,8) +#define CPUID_HTT_CORES __BITS(23,16) +#define CPUID_LOCAL_APIC_ID __BITS(31,24) /* * Intel Deterministic Cache Parameter Leaf @@ -320,6 +320,7 @@ #define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ #define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ #define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HW_FEEDBACK __BIT(19) /* HW_FEEDBACK*, IA32_PACKAGE_TERM* */ #define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ @@ -327,8 +328,8 @@ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ - "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ - "25" "HWP_IGNIDL" + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HW_FEEDBACK" \ + "\25" "HWP_IGNIDL" /* * Intel/AMD Digital Thermal Sensor and @@ -341,7 +342,7 @@ /* * Intel/AMD Structured Extended Feature leaf Fn_0007 - * %eax == 0: Subleaf 0 + * %ecx == 0: Subleaf 0 * %eax: The Maximum input value for supported subleaf. * %ebx: Feature bits. * %ecx: Feature bits. @@ -413,6 +414,7 @@ #define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */ #define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ +#define CPUID_SEF_PKS __BIT(31) /* Protection Keys */ #define CPUID_SEF_FLAGS1 "\177\20" \ "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \ @@ -422,13 +424,14 @@ "f\21\5MAWAU\0" \ "b\26RDPID\0" \ "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \ - "b\34MOVDIR64B\0" "b\36SGXLC\0" + "b\34MOVDIR64B\0" "b\36SGXLC\0" "b\37PKS\0" /* %edx */ #define CPUID_SEF_AVX512_4VNNIW __BIT(2) #define CPUID_SEF_AVX512_4FMAPS __BIT(3) #define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */ #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) +#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */ #define CPUID_SEF_MD_CLEAR __BIT(10) #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */ #define CPUID_SEF_SERIALIZE __BIT(14) @@ -445,7 +448,7 @@ #define CPUID_SEF_FLAGS2 "\20" \ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \ "\5" "FSREP_MOV" \ - "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \ + "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \ "\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \ "\21" "TSXLDTRK" \ "\25" "CET_IBT" \ @@ -561,6 +564,8 @@ #define CPUID_DATP_TCTYPE_D 1 /* Data TLB */ #define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */ #define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */ +#define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */ +#define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */ #define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */ #define
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Tue Feb 12 09:27:17 UTC 2019 Modified Files: src/sys/arch/x86/include [netbsd-8]: specialreg.h Log Message: Actually pull up rev 1.139 (as claimed, but not done in previous), requested by msaitoh in ticket #1187: Fix bitstring format of Intel CPUID Architectural Performance Monitoring Fn000a %ebx. To generate a diff of this commit: cvs rdiff -u -r1.98.2.10 -r1.98.2.11 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.10 src/sys/arch/x86/include/specialreg.h:1.98.2.11 --- src/sys/arch/x86/include/specialreg.h:1.98.2.10 Mon Feb 11 13:23:03 2019 +++ src/sys/arch/x86/include/specialreg.h Tue Feb 12 09:27:17 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98.2.10 2019/02/11 13:23:03 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.98.2.11 2019/02/12 09:27:17 martin Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -464,8 +464,8 @@ #define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */ #define CPUID_PERF_FLAGS1 "\177\20" \ - "b\0\1CORECYCL\0" "b\1\1INSTRETRY\0" "b\2\1REFCYCL\0" "b\3\1LLCREF\0" \ - "b\4\1LLCMISS\0" "b\5\1BRINSRETR\0" "b\6\1BRMISPRRETR\0" + "b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \ + "b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0" /* %edx */ #define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Wed Apr 18 14:14:17 UTC 2018 Modified Files: src/sys/arch/x86/include [netbsd-8]: specialreg.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #778): sys/arch/x86/include/specialreg.h: revision 1.118,1.119 From the latest Intel SDM: - Add Intel Fn_0006 %eax new bit 14-20 (HWP stuff). - Intel Fn_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX. Add Some bit definitions of AMD Fn8001 %edx: - MMX - FXSR To generate a diff of this commit: cvs rdiff -u -r1.98.2.3 -r1.98.2.4 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.3 src/sys/arch/x86/include/specialreg.h:1.98.2.4 --- src/sys/arch/x86/include/specialreg.h:1.98.2.3 Sat Mar 31 10:51:05 2018 +++ src/sys/arch/x86/include/specialreg.h Wed Apr 18 14:14:17 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98.2.3 2018/03/31 10:51:05 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.98.2.4 2018/04/18 14:14:17 martin Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -300,12 +300,19 @@ #define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */ #define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */ #define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */ +#define CPUID_DSPM_HWP_CAP__BIT(15) /* HWP Capabilities */ +#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */ +#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */ +#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */ +#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */ #define CPUID_DSPM_FLAGS "\20" \ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \ "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \ "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \ - "\16" "HDC" "\17" "TBM3" + "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \ + "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \ + "25" "HWP_IGNIDL" /* * Intel Digital Thermal Sensor and @@ -381,7 +388,7 @@ #define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */ #define CPUID_SEF_AVX512_BITALG __BIT(12) #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) -#define CPUID_SEF_RDPID __BIT(22) /* ReaD Processor ID */ +#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */ #define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */ #define CPUID_SEF_FLAGS1 "\20" \ @@ -491,6 +498,8 @@ #define CPUID_MPC 0x0008 /* Multiprocessing Capable */ #define CPUID_NOX 0x0010 /* No Execute Page Protection */ #define CPUID_MMXX 0x0040 /* AMD MMX Extensions */ +/* CPUID_MMX MMX supported */ +/* CPUID_FXSR fast FP/MMX save/restore */ #define CPUID_FFXSR 0x0200 /* FXSAVE/FXSTOR Extensions */ /* CPUID_P1GB 1GB Large Page Support */ /* CPUID_RDTSCP Read TSC Pair Instruction */ @@ -499,9 +508,11 @@ #define CPUID_3DNOW 0x8000 /* 3DNow! Instructions */ #define CPUID_EXT_FLAGS "\20" \ - "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \ - "\27" "MMXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ - "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" + "\14" "SYSCALL/SYSRET" \ + "\24" "MPC" \ + "\25" "NOX" "\27" "MMXX" "\30" "MMX" \ + "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \ + "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW" /* AMD Fn8001 extended features - %ecx */ /* CPUID_LAHF LAHF/SAHF instruction */
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src
Committed By: martin
Date: Sat Apr 14 10:41:15 UTC 2018
Modified Files:
src/sys/arch/x86/include [netbsd-8]: bootinfo.h
Log Message:
Pull up following revision(s) (requested by nonaka in ticket #753):
sys/arch/x86/include/bootinfo.h: revision 1.29
x86: Increase BOOTINFO_MAXSIZE to 8Kib.
Proposed on port-i386 and port-amd64 with no objections:
http://mail-index.netbsd.org/port-i386/2018/04/11/msg003692.html
http://mail-index.netbsd.org/port-amd64/2018/04/11/msg002697.html
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.26.6.1 src/sys/arch/x86/include/bootinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/bootinfo.h
diff -u src/sys/arch/x86/include/bootinfo.h:1.26 src/sys/arch/x86/include/bootinfo.h:1.26.6.1
--- src/sys/arch/x86/include/bootinfo.h:1.26 Tue Feb 14 13:25:22 2017
+++ src/sys/arch/x86/include/bootinfo.h Sat Apr 14 10:41:15 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: bootinfo.h,v 1.26 2017/02/14 13:25:22 nonaka Exp $ */
+/* $NetBSD: bootinfo.h,v 1.26.6.1 2018/04/14 10:41:15 martin Exp $ */
/*
* Copyright (c) 1997
@@ -244,7 +244,7 @@ struct btinfo_efimemmap {
#ifdef _KERNEL
-#define BOOTINFO_MAXSIZE 4096
+#define BOOTINFO_MAXSIZE 8192
#ifndef _LOCORE
/*
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Sat Mar 31 10:51:05 UTC 2018 Modified Files: src/sys/arch/x86/include [netbsd-8]: specialreg.h Log Message: Pull up following revision(s) (requested by maxv in ticket #678): sys/arch/x86/include/specialreg.h: revision 1.115-1.117,1.120 Add IC_CFG.DIS_IND: "Disable Indirect Branch Predictor". Available (at least) on AMD Families 10h, 12h and 16h. Add the IBRS and STIBP MSRs. ... and also add IBPB ... Add RDCL_NO and IBRS_ALL. To generate a diff of this commit: cvs rdiff -u -r1.98.2.2 -r1.98.2.3 src/sys/arch/x86/include/specialreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/specialreg.h diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.2 src/sys/arch/x86/include/specialreg.h:1.98.2.3 --- src/sys/arch/x86/include/specialreg.h:1.98.2.2 Fri Mar 16 13:05:31 2018 +++ src/sys/arch/x86/include/specialreg.h Sat Mar 31 10:51:05 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.98.2.2 2018/03/16 13:05:31 martin Exp $ */ +/* $NetBSD: specialreg.h,v 1.98.2.3 2018/03/31 10:51:05 martin Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -630,7 +630,10 @@ #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */ #define MSR_TEST_CTL 0x033 #define MSR_IA32_SPEC_CTRL 0x048 +#define IA32_SPEC_CTRL_IBRS 0x01 +#define IA32_SPEC_CTRL_STIBP 0x02 #define MSR_IA32_PRED_CMD 0x049 +#define IA32_PRED_CMD_IBPB 0x01 #define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ #define MSR_BBL_CR_D1 0x089 /* PII+ only */ @@ -644,6 +647,8 @@ #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ #define MSR_MTRRcap 0x0fe #define MSR_IA32_ARCH_CAPABILITIES 0x10a +#define IA32_ARCH_RDCL_NO 0x01 +#define IA32_ARCH_IBRS_ALL 0x02 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ @@ -842,6 +847,7 @@ #define MSR_IC_CFG 0xc0011021 #define IC_CFG_DIS_SEQ_PREFETCH 0x0800 +#define IC_CFG_DIS_IND 0x4000 #define MSR_DC_CFG 0xc0011022 #define DC_CFG_DIS_CNV_WC_SSO 0x0008
CVS commit: [netbsd-8] src/sys/arch/x86/include
Module Name:src Committed By: martin Date: Thu Mar 1 19:07:31 UTC 2018 Modified Files: src/sys/arch/x86/include [netbsd-8]: Makefile Log Message: Pull up following revision(s) (requested by kamil in ticket #599): sys/arch/x86/include/Makefile: revision 1.22 Stop installing dbregs.h This is now kernel-only header. The behavior is well specified by the CPU= documents and we don't introduce changes to it. Noted by To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.21.8.1 src/sys/arch/x86/include/Makefile Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/x86/include/Makefile diff -u src/sys/arch/x86/include/Makefile:1.21 src/sys/arch/x86/include/Makefile:1.21.8.1 --- src/sys/arch/x86/include/Makefile:1.21 Thu Dec 15 12:04:18 2016 +++ src/sys/arch/x86/include/Makefile Thu Mar 1 19:07:31 2018 @@ -1,4 +1,4 @@ -# $NetBSD: Makefile,v 1.21 2016/12/15 12:04:18 kamil Exp $ +# $NetBSD: Makefile,v 1.21.8.1 2018/03/01 19:07:31 martin Exp $ INCSDIR=/usr/include/x86 @@ -11,7 +11,6 @@ INCS= aout_machdep.h \ cpu_ucode.h \ cputypes.h \ cpuvar.h \ - dbregs.h \ float.h \ fpu.h \ ieee.h ieeefp.h \
