CVS commit: src/sys/arch/riscv/conf

[Nick Hudson]

Module Name:src
Committed By:   skrll
Date:   Sat May  1 07:13:21 UTC 2021

Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv kern.ldscript

Log Message:
Fixup kernel linking and provide a linker script with standard sections
and symbols


To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/Makefile.riscv
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/kern.ldscript

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.6 src/sys/arch/riscv/conf/Makefile.riscv:1.7
--- src/sys/arch/riscv/conf/Makefile.riscv:1.6	Sat Mar 14 16:12:15 2020
+++ src/sys/arch/riscv/conf/Makefile.riscv	Sat May  1 07:13:21 2021
@@ -1,4 +1,4 @@
-#	$NetBSD: Makefile.riscv,v 1.6 2020/03/14 16:12:15 skrll Exp $
+#	$NetBSD: Makefile.riscv,v 1.7 2021/05/01 07:13:21 skrll Exp $
 
 # Makefile for NetBSD
 #
@@ -74,11 +74,17 @@ TEXTADDR?=		0xFFC0
 TEXTADDR?=		0xC0001000
 .endif
 KERNLDSCRIPT?=		${RISCV}/conf/kern.ldscript
-LINKFORMAT+=		-T ${KERNLDSCRIPT}
 EXTRA_LINKFLAGS=	${LDOPTS} --relax
 LINKFLAGS_NORMAL=	-X
 STRIPFLAGS=		-g -X
 
+# Set the physical load address (aka LMA) to the address that OpenSBI's
+# fw_jump jumps to.  This allows us to load the kernel with the -kernel flag
+# in QEMU without having to embed it inside BBL or OpenSBI's fw_payload first.
+#
+KERNEL_PHYS?=		0x8020
+EXTRA_LINKFLAGS+=	--defsym='KERNEL_PHYS=${KERNEL_PHYS}'
+
 ##
 ## (6) port specific target dependencies
 ##

Index: src/sys/arch/riscv/conf/kern.ldscript
diff -u src/sys/arch/riscv/conf/kern.ldscript:1.7 src/sys/arch/riscv/conf/kern.ldscript:1.8
--- src/sys/arch/riscv/conf/kern.ldscript:1.7	Wed Nov  4 07:09:45 2020
+++ src/sys/arch/riscv/conf/kern.ldscript	Sat May  1 07:13:21 2021
@@ -1,4 +1,6 @@
-/*	$NetBSD: kern.ldscript,v 1.7 2020/11/04 07:09:45 skrll Exp $	*/
+/*	$NetBSD: kern.ldscript,v 1.8 2021/05/01 07:13:21 skrll Exp $	*/
+
+#include "assym.h"
 
 OUTPUT_ARCH(riscv)
 ENTRY(start)
@@ -8,8 +10,10 @@ __LARGE_PAGE_SIZE = 0x20 ;
 
 SECTIONS
 {
-	.text : AT (ADDR(.text) & 0x0fff)
+
+	.text : AT (KERNEL_PHYS)
 	{
+		PROVIDE(__kernel_text = .);
 		*(.text)
 		*(.text.*)
 		*(.stub)
@@ -19,7 +23,7 @@ SECTIONS
 
 	. = ALIGN(__LARGE_PAGE_SIZE);
 
-	__rodata_start = . ;
+	PROVIDE(__rodata_start = .);
 	.rodata :
 	{
 		*(.rodata)
@@ -28,17 +32,36 @@ SECTIONS
 		*(.srodata.*)
 	}
 
+	PROVIDE(_etext = .);
+	PROVIDE(etext = .);
 	. = ALIGN(__LARGE_PAGE_SIZE);
 
-	__data_start = . ;
 	.data :
 	{
+		PROVIDE(__data_start = .);
 		*(.data)
+	}
+
+	. = ALIGN(COHERENCY_UNIT);
+	.data.cacheline_aligned :
+	{
+		*(.data.cacheline_aligned)
+	}
+	. = ALIGN(COHERENCY_UNIT);
+	.data.read_mostly :
+	{
+		*(.data.read_mostly)
+	}
+	. = ALIGN(COHERENCY_UNIT);
+
+	.sdata :
+	{
+		__global_pointer$ = . + 0x800;
 		*(.sdata)
 		*(.sdata.*)
 	}
-	_edata = . ;
-	PROVIDE (edata = .) ;
+	_edata = .;
+	PROVIDE (edata = .);
 
 	__bss_start = .;
 	.bss :
@@ -50,14 +73,13 @@ SECTIONS
 		*(COMMON)
 		. = ALIGN(__LARGE_PAGE_SIZE);
 	}
-
+	_bss_end__ = . ;
+	__bss_end__ = . ;
 	. = ALIGN(__PAGE_SIZE);
 
-	/* End of the kernel image */
-	__kernel_end = . ;
-
-	_end = . ;
-	PROVIDE (end = .) ;
+	__end__ = . ;
+	_end = .;
+	PROVIDE(end = .);
 	.note.netbsd.ident :
 	{
 		KEEP(*(.note.netbsd.ident));

CVS commit: src/sys/arch/riscv/conf

[David A. Holland]

Module Name:src
Committed By:   dholland
Date:   Sun Jan 27 18:00:06 UTC 2019

Modified Files:
src/sys/arch/riscv/conf: majors.riscv

Log Message:
This may have been cutpasted from evbmips, but we don't need to say so.


To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/majors.riscv

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/riscv/conf/majors.riscv
diff -u src/sys/arch/riscv/conf/majors.riscv:1.5 src/sys/arch/riscv/conf/majors.riscv:1.6
--- src/sys/arch/riscv/conf/majors.riscv:1.5	Sun Jan 27 17:59:23 2019
+++ src/sys/arch/riscv/conf/majors.riscv	Sun Jan 27 18:00:06 2019
@@ -1,6 +1,6 @@
-#	$NetBSD: majors.riscv,v 1.5 2019/01/27 17:59:23 dholland Exp $
+#	$NetBSD: majors.riscv,v 1.6 2019/01/27 18:00:06 dholland Exp $
 #
-# Device majors for evbmips
+# Device majors for riscv
 #
 
 device-major	tun		char 7			tun

CVS commit: src/sys/arch/riscv/conf

[Matt Thomas]

Module Name:src
Committed By:   matt
Date:   Tue Mar 31 01:05:52 UTC 2015

Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv

Log Message:
Use -mcmodel=medany to get PICish code.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/Makefile.riscv

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.1 src/sys/arch/riscv/conf/Makefile.riscv:1.2
--- src/sys/arch/riscv/conf/Makefile.riscv:1.1	Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/conf/Makefile.riscv	Tue Mar 31 01:05:52 2015
@@ -1,4 +1,4 @@
-#	$NetBSD: Makefile.riscv,v 1.1 2015/03/28 16:13:56 matt Exp $
+#	$NetBSD: Makefile.riscv,v 1.2 2015/03/31 01:05:52 matt Exp $
 
 # Makefile for NetBSD
 #
@@ -38,7 +38,8 @@ GENASSYM_CONF=	${RISCV}/riscv/genassym.c
 ## Note: -ffixed-?? must be kept in sync with cpu.h.
 ##
 CPPFLAGS+=	-D${MACHINE}
-CFLAGS+=	-fPIC -Wa,-fno-pic -msoft-float
+CFLAGS+=	-mcmodel=medany
+CFLAGS+=	-msoft-float
 .if !defined(LP64) || ${LP64} == "no"
 CFLAGS+=	-m32
 AFLAGS+=	-m32