CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: knakahara Date: Fri Apr 17 03:15:51 UTC 2020 Modified Files: src/usr.sbin/tprof/arch: tprof_x86.c Log Message: Fix typo in a comment. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/usr.sbin/tprof/arch/tprof_x86.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/tprof/arch/tprof_x86.c diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.9 src/usr.sbin/tprof/arch/tprof_x86.c:1.10 --- src/usr.sbin/tprof/arch/tprof_x86.c:1.9 Fri Oct 11 18:05:52 2019 +++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Apr 17 03:15:50 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: tprof_x86.c,v 1.9 2019/10/11 18:05:52 jmcneill Exp $ */ +/* $NetBSD: tprof_x86.c,v 1.10 2020/04/17 03:15:50 knakahara Exp $ */ /* * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. @@ -550,7 +550,7 @@ init_intel_generic(void) table->next = init_intel_silvermont_airmont(); break; case 0x5C: /* Goldmont (Apollo Lake) */ - case 0x5F: /* Goldmont (Denvertion) */ + case 0x5F: /* Goldmont (Denverton) */ table->next = init_intel_goldmont(); break; case 0x7A: /* Goldmont Plus (Gemini Lake) */
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: knakahara
Date: Thu Nov 15 07:20:31 UTC 2018
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
tprof: Add silvermont, airmont support.
I tested on Atom C2758 (Rangeley).
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.4 src/usr.sbin/tprof/arch/tprof_x86.c:1.5
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.4 Sat Jul 14 07:54:04 2018
+++ src/usr.sbin/tprof/arch/tprof_x86.c Thu Nov 15 07:20:31 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.4 2018/07/14 07:54:04 maxv Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.5 2018/11/15 07:20:31 knakahara Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -119,6 +119,93 @@ init_intel_arch1(void)
}
/*
+ * Intel Silvermont/Airmont.
+ */
+static struct name_to_event intel_silvermont_airmont_names[] = {
+ { "REHABQ.LD_BLOCK_ST_FORWARD", 0x03, 0x01, true },
+ { "REHABQ.LD_BLOCK_STD_NOTREADY", 0x03, 0x02, true },
+ { "REHABQ.ST_SPLITS", 0x03, 0x04, true },
+ { "REHABQ.LD_SPLITS", 0x03, 0x08, true },
+ { "REHABQ.LOCK", 0x03, 0x10, true },
+ { "REHABQ.STA_FULL", 0x03, 0x20, true },
+ { "REHABQ.ANY_LD", 0x03, 0x40, true },
+ { "REHABQ.ANY_ST", 0x03, 0x80, true },
+ { "MEM_UOPS_RETIRED.L1_MISS_LOADS", 0x04, 0x01, true },
+ { "MEM_UOPS_RETIRED.L2_HIT_LOADS", 0x04, 0x02, true },
+ { "MEM_UOPS_RETIRED.L2_MISS_LOADS", 0x04, 0x04, true },
+ { "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0x04, 0x08, true },
+ { "MEM_UOPS_RETIRED.UTLB_MISS", 0x04, 0x10, true },
+ { "MEM_UOPS_RETIRED.HITM", 0x04, 0x20, true },
+ { "MEM_UOPS_RETIRED.ALL_LOADS", 0x04, 0x40, true },
+ { "MEM_UOP_RETIRED.ALL_STORES", 0x04, 0x80, true },
+ { "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
+ { "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
+ { "PAGE_WALKS.WALKS", 0x05, 0x03, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
+ { "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
+ { "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
+ { "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
+ { "CPU_CLK_UNHALTED.REF_P", 0x3C, 0x01, true },
+ { "ICACHE.HIT",0x80, 0x01, true },
+ { "ICACHE.MISSES", 0x80, 0x02, true },
+ { "ICACHE.ACCESSES", 0x80, 0x03, true },
+ { "OFFCORE_RESPONSE_0", 0xB7, 0x01, true },
+ { "OFFCORE_RESPONSE_1", 0xB7, 0x02, true },
+ { "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
+ { "UOPS_RETIRED.MS", 0xC2, 0x01, true },
+ { "UOPS_RETIRED.ALL", 0xC2, 0x10, true },
+ { "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
+ { "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
+ { "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
+ { "MACHINE_CLEARS.ALL", 0xC3, 0x08, true },
+ { "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
+ { "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
+ { "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
+ { "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
+ { "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
+ { "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
+ { "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
+ { "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
+ { "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
+ { "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
+ { "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
+ { "BR_MISP_RETIRED.FAR", 0xC5, 0xBF, true },
+ { "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
+ { "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
+ { "BR_MISP_RETIRED.CALL", 0xC5, 0xF9, true },
+ { "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
+ { "BR_MISP_RETIRED.REL_CALL", 0xC5, 0xFD, true },
+ { "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
+ { "NO_ALLOC_CYCLES.ROB_FULL", 0xCA, 0x01, true },
+ { "NO_ALLOC_CYCLES.RAT_STALL", 0xCA, 0x20, true },
+ { "NO_ALLOC_CYCLES.ALL", 0xCA, 0x3F, true },
+ { "NO_ALLOC_CYCLES.NOT_DELIVERED", 0xCA, 0x50, true },
+ { "RS_FULL_STALL.MEC", 0xCB, 0x01, true },
+ { "RS_FULL_STALL.ALL", 0xCB, 0x1F, true },
+ { "CYCLES_DIV_BUSY.ANY", 0xCD, 0x01, true },
+ { "BACLEARS.ALL", 0xE6, 0x01, true },
+ { "BACLEARS.RETURN", 0xE6, 0x08, true },
+ { "BACLEARS.COND", 0xE6, 0x10, true },
+ { "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
+};
+
+static struct event_table intel_silvermont_airmont = {
+ .tablename = "Intel Silvermont/Airmont",
+ .names = intel_silvermont_airmont_names,
+ .nevents = sizeof(intel_silvermont_airmont_names) /
+ sizeof(struct name_to_event),
+ .next = NULL
+};
+
+static struct event_table *
+init_intel_silvermont_airmont(void)
+{
+
+ return _silvermont_airmont;
+}
+
+/*
* Intel Skylake/Kabylake.
*
* The events that are not listed, because they are of little interest or
@@ -309,6 +396,14 @@ init_intel_generic(void)
if (CPUID_TO_FAMILY(eax) == 6) {
switch
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: jmcneill
Date: Sat Jul 14 15:38:59 UTC 2018
Modified Files:
src/usr.sbin/tprof/arch: tprof_noarch.c
Log Message:
Mark tprof_event_init, tprof_event_list, tprof_event_lookup as dead
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/usr.sbin/tprof/arch/tprof_noarch.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_noarch.c
diff -u src/usr.sbin/tprof/arch/tprof_noarch.c:1.2 src/usr.sbin/tprof/arch/tprof_noarch.c:1.3
--- src/usr.sbin/tprof/arch/tprof_noarch.c:1.2 Sat Jul 14 07:54:37 2018
+++ src/usr.sbin/tprof/arch/tprof_noarch.c Sat Jul 14 15:38:59 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_noarch.c,v 1.2 2018/07/14 07:54:37 maxv Exp $ */
+/* $NetBSD: tprof_noarch.c,v 1.3 2018/07/14 15:38:59 jmcneill Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -43,19 +43,19 @@ int tprof_event_init(uint32_t);
void tprof_event_list(void);
void tprof_event_lookup(const char *, struct tprof_param *);
-int
+__dead int
tprof_event_init(uint32_t ident)
{
errx(EXIT_FAILURE, "architecture not supported");
}
-void
+__dead void
tprof_event_list(void)
{
errx(EXIT_FAILURE, "architecture not supported");
}
-void
+__dead void
tprof_event_lookup(const char *name, struct tprof_param *param)
{
errx(EXIT_FAILURE, "architecture not supported");
CVS commit: src/usr.sbin/tprof/arch
Module Name:src Committed By: maxv Date: Sat Jul 14 07:54:38 UTC 2018 Modified Files: src/usr.sbin/tprof/arch: tprof_noarch.c Log Message: specialreg.h is x86-specific, don't include it To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/usr.sbin/tprof/arch/tprof_noarch.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/usr.sbin/tprof/arch/tprof_noarch.c diff -u src/usr.sbin/tprof/arch/tprof_noarch.c:1.1 src/usr.sbin/tprof/arch/tprof_noarch.c:1.2 --- src/usr.sbin/tprof/arch/tprof_noarch.c:1.1 Fri Jul 13 07:56:29 2018 +++ src/usr.sbin/tprof/arch/tprof_noarch.c Sat Jul 14 07:54:37 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: tprof_noarch.c,v 1.1 2018/07/13 07:56:29 maxv Exp $ */ +/* $NetBSD: tprof_noarch.c,v 1.2 2018/07/14 07:54:37 maxv Exp $ */ /* * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -36,7 +36,6 @@ #include #include #include -#include #include #include "../tprof.h"
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: maxv
Date: Fri Jul 13 09:53:42 UTC 2018
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Skylake/Kabylake are family 6, so add a check for that. While here improve
the layout of "tprof list".
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.2 src/usr.sbin/tprof/arch/tprof_x86.c:1.3
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.2 Fri Jul 13 08:09:21 2018
+++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Jul 13 09:53:42 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.2 2018/07/13 08:09:21 maxv Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.3 2018/07/13 09:53:42 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -162,13 +162,15 @@ init_intel_generic(void)
edx = 0;
x86_cpuid(, , , );
- switch (CPUID_TO_MODEL(eax)) {
- case 0x4E: /* Skylake */
- case 0x5E: /* Skylake */
- case 0x8E: /* Kabylake */
- case 0x9E: /* Kabylake */
- table->next = init_intel_skylake_kabylake();
- break;
+ if (CPUID_TO_FAMILY(eax) == 6) {
+ switch (CPUID_TO_MODEL(eax)) {
+ case 0x4E: /* Skylake */
+ case 0x5E: /* Skylake */
+ case 0x8E: /* Kabylake */
+ case 0x9E: /* Kabylake */
+ table->next = init_intel_skylake_kabylake();
+ break;
+ }
}
return table;
@@ -314,7 +316,6 @@ recursive_event_list(struct event_table
continue;
printf("\t%s\n", table->names[i].name);
}
- printf("\n");
if (table->next != NULL) {
recursive_event_list(table->next);
CVS commit: src/usr.sbin/tprof/arch
Module Name:src
Committed By: maxv
Date: Fri Jul 13 08:09:21 UTC 2018
Modified Files:
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
Inline the values in amd_f10h_names[], we're not going to use defines for
each CPU model found in the wild.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.1 src/usr.sbin/tprof/arch/tprof_x86.c:1.2
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.1 Fri Jul 13 07:56:29 2018
+++ src/usr.sbin/tprof/arch/tprof_x86.c Fri Jul 13 08:09:21 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.1 2018/07/13 07:56:29 maxv Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.2 2018/07/13 08:09:21 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -180,77 +180,76 @@ init_intel_generic(void)
* AMD Family 10h
*/
static struct name_to_event amd_f10h_names[] = {
- { "seg-load-all", F10H_SEGMENT_REG_LOADS, 0x7f, true },
- { "seg-load-es", F10H_SEGMENT_REG_LOADS, 0x01, true },
- { "seg-load-cs", F10H_SEGMENT_REG_LOADS, 0x02, true },
- { "seg-load-ss", F10H_SEGMENT_REG_LOADS, 0x04, true },
- { "seg-load-ds", F10H_SEGMENT_REG_LOADS, 0x08, true },
- { "seg-load-fs", F10H_SEGMENT_REG_LOADS, 0x10, true },
- { "seg-load-gs", F10H_SEGMENT_REG_LOADS, 0x20, true },
- { "seg-load-hs", F10H_SEGMENT_REG_LOADS, 0x40, true },
- { "l1cache-access", F10H_DATA_CACHE_ACCESS, 0, true },
- { "l1cache-miss", F10H_DATA_CACHE_MISS, 0, true },
- { "l1cache-refill", F10H_DATA_CACHE_REFILL_FROM_L2, 0x1f, true },
- { "l1cache-refill-invalid", F10H_DATA_CACHE_REFILL_FROM_L2, 0x01, true },
- { "l1cache-refill-shared", F10H_DATA_CACHE_REFILL_FROM_L2, 0x02, true },
- { "l1cache-refill-exclusive", F10H_DATA_CACHE_REFILL_FROM_L2, 0x04, true },
- { "l1cache-refill-owner", F10H_DATA_CACHE_REFILL_FROM_L2, 0x08, true },
- { "l1cache-refill-modified", F10H_DATA_CACHE_REFILL_FROM_L2, 0x10, true },
- { "l1cache-load", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x1f, true },
- { "l1cache-load-invalid", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x01, true },
- { "l1cache-load-shared", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x02, true },
- { "l1cache-load-exclusive", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x04, true },
- { "l1cache-load-owner", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x08, true },
- { "l1cache-load-modified", F10H_DATA_CACHE_REFILL_FROM_NORTHBRIDGE,0x10, true },
- { "l1cache-writeback", F10H_CACHE_LINES_EVICTED, 0x1f, true },
- { "l1cache-writeback-invalid", F10H_CACHE_LINES_EVICTED, 0x01, true },
- { "l1cache-writeback-shared", F10H_CACHE_LINES_EVICTED, 0x02, true },
- { "l1cache-writeback-exclusive",F10H_CACHE_LINES_EVICTED, 0x04, true },
- { "l1cache-writeback-owner", F10H_CACHE_LINES_EVICTED, 0x08, true },
- { "l1cache-writeback-modified", F10H_CACHE_LINES_EVICTED, 0x10, true },
- { "l1DTLB-hit-all", F10H_L1_DTLB_HIT, 0x07, true },
- { "l1DTLB-hit-4Kpage", F10H_L1_DTLB_HIT, 0x01, true },
- { "l1DTLB-hit-2Mpage", F10H_L1_DTLB_HIT, 0x02, true },
- { "l1DTLB-hit-1Gpage", F10H_L1_DTLB_HIT, 0x04, true },
- { "l1DTLB-miss-all", F10H_L1_DTLB_MISS, 0x07, true },
- { "l1DTLB-miss-4Kpage", F10H_L1_DTLB_MISS, 0x01, true },
- { "l1DTLB-miss-2Mpage", F10H_L1_DTLB_MISS, 0x02, true },
- { "l1DTLB-miss-1Gpage", F10H_L1_DTLB_MISS, 0x04, true },
- { "l2DTLB-miss-all", F10H_L2_DTLB_MISS, 0x03, true },
- { "l2DTLB-miss-4Kpage", F10H_L2_DTLB_MISS, 0x01, true },
- { "l2DTLB-miss-2Mpage", F10H_L2_DTLB_MISS, 0x02, true },
+ { "seg-load-all", 0x20, 0x7f, true },
+ { "seg-load-es", 0x20, 0x01, true },
+ { "seg-load-cs", 0x20, 0x02, true },
+ { "seg-load-ss", 0x20, 0x04, true },
+ { "seg-load-ds", 0x20, 0x08, true },
+ { "seg-load-fs", 0x20, 0x10, true },
+ { "seg-load-gs", 0x20, 0x20, true },
+ { "seg-load-hs", 0x20, 0x40, true },
+ { "l1cache-access", 0x40, 0x00, true },
+ { "l1cache-miss", 0x41, 0x00, true },
+ { "l1cache-refill", 0x42, 0x1f, true },
+ { "l1cache-refill-invalid", 0x42, 0x01, true },
+ { "l1cache-refill-shared", 0x42, 0x02, true },
+ { "l1cache-refill-exclusive", 0x42, 0x04, true },
+ { "l1cache-refill-owner", 0x42, 0x08, true },
+ { "l1cache-refill-modified", 0x42, 0x10, true },
+ { "l1cache-load", 0x43, 0x1f, true },
+ { "l1cache-load-invalid", 0x43, 0x01, true },
+ { "l1cache-load-shared", 0x43, 0x02, true },
+ { "l1cache-load-exclusive", 0x43, 0x04, true },
+ { "l1cache-load-owner", 0x43, 0x08, true },
+ { "l1cache-load-modified", 0x43, 0x10, true },
+ { "l1cache-writeback", 0x44, 0x1f, true },
+ { "l1cache-writeback-invalid", 0x44, 0x01, true },
+ { "l1cache-writeback-shared", 0x44, 0x02, true },
+ { "l1cache-writeback-exclusive",0x44, 0x04, true },
+ { "l1cache-writeback-owner", 0x44, 0x08, true },
+ { "l1cache-writeback-modified", 0x44, 0x10, true },
+ {
