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Re: [PATCH] SPI: SSP SPI Controller driver
On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote:
This patch is to implement SSP SPI controller driver, which has been
applied and
validated on intel Moorestown Medfield platform. The patch are
originated by
Ken Mills ken.k.mi...@intel.com and Sylvain Centelles
sylvain.centel...@intel.com,
and to be further developed by Channing chao...@intel.com and Chen Jun
jun.d.c...@intel.com according to their integration validation on
Medfield platform.
Signed-off-by: Ken Mills ken.k.mi...@intel.com
Signed-off-by: Sylvain Centelles sylvain.centel...@intel.com
Signed-off-by: channing chao...@intel.com
Signed-off-by: Chen Jun jun.d.c...@intel.com
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile |1 +
drivers/spi/spi-intel-mid-ssp.c | 1407
+
include/linux/spi/spi-intel-mid-ssp.h | 326
4 files changed, 1743 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi-intel-mid-ssp.c
create mode 100644 include/linux/spi/spi-intel-mid-ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1acae35..8b4461b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -179,6 +179,15 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
+ depends on SPI_MASTER INTEL_MID_DMAC
+ help
+ This is the unified SSP SPI master controller driver for
+ the Intel MID platforms, handling Moorestown Medfield,
+ master clock mode.
+ It supports Bulverde SSP core.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c48df47..83f06d0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_SPI_FSL_ESPI)+= spi-fsl-espi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
obj-$(CONFIG_SPI_IMX) += spi-imx.o
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
diff --git a/drivers/spi/spi-intel-mid-ssp.c
b/drivers/spi/spi-intel-mid-ssp.c
new file mode 100644
index 000..8fca48f
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.c
@@ -0,0 +1,1407 @@
+/*
+ * spi-intel-mid-ssp.c
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports SSP of Moorestown Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos.h
+#include linux/module.h
+
+#include linux/spi/spi.h
+#include linux/spi/spi-intel-mid-ssp.h
+
+#define DRIVER_NAME intel_mid_ssp_spi_unified
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len,
int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+
Re: [PATCH] SPI: SSP SPI Controller driver
On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote: + /* Create the PM_QOS request */ + if (drv_context-quirks QUIRKS_USE_PM_QOS) + pm_qos_add_request(drv_context-pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); What happens if the flag is not set if it is absolutely necessary for the driver it should not be a configurable option? -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH] SPI: SSP SPI Controller driver
On Wed, 21 Nov 2012 17:44:21 +0530 Shubhrajyoti Datta omaplinuxker...@gmail.com wrote: On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote: + /* Create the PM_QOS request */ + if (drv_context-quirks QUIRKS_USE_PM_QOS) + pm_qos_add_request(drv_context-pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); What happens if the flag is not set if it is absolutely necessary for the driver it should not be a configurable option If you read through the code it's set only when the device is Moorestown/Oaktrail based and only in slave mode. It is not necessary in other configurations. Alan -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1 v2] of_spi: add generic binding support to specify cs gpio
On Thu, 15 Nov 2012 20:19:57 +0100, Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com wrote: This will allow to use gpio for chip select with no modification in the driver binding When use the cs-gpios, the gpio number will be passed via the cs_gpio field and the number of chip select will automatically increased with max(hw cs, gpio cs). So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = gpio1 0 0 0 gpio1 1 0 gpio1 2 0; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : gpio1 0 0 cs1 : native cs2 : gpio1 1 0 cs3 : gpio1 2 0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com Cc: devicetree-disc...@lists.ozlabs.org Cc: spi-devel-general@lists.sourceforge.net Signed-off-by: Richard Genoud richard.gen...@gmail.com Applied, thanks. g. -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [linux-keystone] Re: [linux-keystone] [PATCH] spi: davinci: add OF support for the spi controller
On Fri, 16 Nov 2012 11:32:46 -0500, Murali Karicheri m-kariche...@ti.com wrote: On 11/15/2012 11:20 AM, Grant Likely wrote: On Mon, 12 Nov 2012 16:28:22 -0500, Murali Karicheri m-kariche...@ti.com wrote: This adds OF support to DaVinci SPI controller to configure platform data through device bindings. Signed-off-by: Murali Karicheri m-kariche...@ti.com Hi Murali, Comments below... --- .../devicetree/bindings/spi/spi-davinci.txt| 50 drivers/spi/spi-davinci.c | 80 +++- 2 files changed, 126 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/spi-davinci.txt diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt new file mode 100644 index 000..0369369 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt @@ -0,0 +1,50 @@ +Davinci SPI controller device bindings + +Required properties: +- #address-cells: number of cells required to define a chip select + address on the SPI bus. Will this *ever* be something other than '1'? Will add should be set to 1 as only once cell is used for this. +- #size-cells: should be zero. +- compatible: + - ti,davinci-spi Please use the actual model of the chip here. Don't try to be generic with the compatible string. A driver can bind against more than one compatible value and new devices can claim compatiblity with old by including the old compatible string in this list. +- reg: Offset and length of SPI controller register space +- ti,davinci-spi-version: SPI version :- 1.0 or 2.0 Usually this is determined from the compatible value directly (which is why compatible strings shouldn't be generic). Don't use a separate property for it. Ok. Based on the ablve two comments, I think I will remove davinci-spi-version property. So driver will add two compatibility strings ti,davinci-spi1 and ti,davinci-spi2 amd match data for ti,davinci-spi2 will have the version set to 2 so that driver can use it to behave differently. This way DTS file for a board can set the compatibility string to use different version of the IP for the driver. Do you think I got you right? Mostly, but what would be better is something like: ti,davinci(model)-spi and ti,keystone(model)-spi replacing (model) with the actual chip part number. It is always better to use real part names than to make up meaninless '1', '2' numbers. Newer devices can include the older compatible part in the compatible property. For example: compatible = ti,keystone-gen2-spi, ti,keystone-original-spi; (I'm making up part names here, but you get the idea). So a driver that binds against ti,keystone-original-spi will work with a newer keystone gen2. +- ti,davinci-spi-num-cs: Number of chip selects +- ti,davinci-spi-intr-line: interrupt line used to connect the SPI + IP to the ARM interrupt controller withn the SoC. Possible values + are 0 and 1. ? Isn't that what the interrupts property is for? I don't understand why this is needed from the description. Based on the IP manual, there are two interrupt lines coming from the IP and only one of them is tied to the interrupt controller in a specific SoC. There is a register to program which interrupt line is used based on the SoC configuration. So this is different from interrupts. Okay. g. -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH] ARM: Kirkwood: Add SPI_CHPA and SPI_CPOL support to spi-orion
Support these transfer modes from the SPI layer by setting
the appropriate register bits before doing the transfer.
This was tested on the Marvell kirkwood SOC that uses this driver.
Reviewed-by: Jason Gunthorpe jguntho...@obsidianresearch.com
Signed-off-by: Rolf Manderscheid r...@obsidianresearch.com
---
drivers/spi/spi-orion.c | 25 -
1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index b17c09c..011186d 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -32,8 +32,12 @@
#define ORION_SPI_DATA_IN_REG 0x0c
#define ORION_SPI_INT_CAUSE_REG0x10
+#define ORION_SPI_MODE_CPOL(1 11)
+#define ORION_SPI_MODE_CPHA(1 12)
#define ORION_SPI_IF_8_16_BIT_MODE (1 5)
#define ORION_SPI_CLK_PRESCALE_MASK0x1F
+#define ORION_SPI_MODE_MASK(ORION_SPI_MODE_CPOL | \
+ORION_SPI_MODE_CPHA)
struct orion_spi {
struct spi_master *master;
@@ -123,6 +127,23 @@ static int orion_spi_baudrate_set(struct spi_device *spi,
unsigned int speed)
return 0;
}
+static void
+orion_spi_mode_set(struct spi_device *spi)
+{
+ u32 reg;
+ struct orion_spi *orion_spi;
+
+ orion_spi = spi_master_get_devdata(spi-master);
+
+ reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
+ reg = ~ORION_SPI_MODE_MASK;
+ if (spi-mode SPI_CPOL)
+ reg |= ORION_SPI_MODE_CPOL;
+ if (spi-mode SPI_CPHA)
+ reg |= ORION_SPI_MODE_CPHA;
+ writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
+}
+
/*
* called only when no transfer is active on the bus
*/
@@ -142,6 +163,8 @@ orion_spi_setup_transfer(struct spi_device *spi, struct
spi_transfer *t)
if ((t != NULL) t-bits_per_word)
bits_per_word = t-bits_per_word;
+ orion_spi_mode_set(spi);
+
rc = orion_spi_baudrate_set(spi, speed);
if (rc)
return rc;
@@ -399,7 +422,7 @@ static int __init orion_spi_probe(struct platform_device
*pdev)
}
/* we support only mode 0, and no options */
- master-mode_bits = 0;
+ master-mode_bits = SPI_CPHA | SPI_CPOL;
master-setup = orion_spi_setup;
master-transfer_one_message = orion_spi_transfer_one_message;
--
1.7.5.4
--
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Re: [PATCH] ARM: Kirkwood: Add SPI_CHPA and SPI_CPOL support to spi-orion
On Wed, Nov 21, 2012 at 12:23:35PM -0700, Jason Gunthorpe wrote:
Support these transfer modes from the SPI layer by setting
the appropriate register bits before doing the transfer.
This was tested on the Marvell kirkwood SOC that uses this driver.
Reviewed-by: Jason Gunthorpe jguntho...@obsidianresearch.com
Signed-off-by: Rolf Manderscheid r...@obsidianresearch.com
---
drivers/spi/spi-orion.c | 25 -
1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index b17c09c..011186d 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -32,8 +32,12 @@
#define ORION_SPI_DATA_IN_REG0x0c
#define ORION_SPI_INT_CAUSE_REG 0x10
+#define ORION_SPI_MODE_CPOL (1 11)
+#define ORION_SPI_MODE_CPHA (1 12)
#define ORION_SPI_IF_8_16_BIT_MODE (1 5)
#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
+#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
+ ORION_SPI_MODE_CPHA)
struct orion_spi {
struct spi_master *master;
@@ -123,6 +127,23 @@ static int orion_spi_baudrate_set(struct spi_device
*spi, unsigned int speed)
return 0;
}
+static void
+orion_spi_mode_set(struct spi_device *spi)
+{
+ u32 reg;
+ struct orion_spi *orion_spi;
+
+ orion_spi = spi_master_get_devdata(spi-master);
+
+ reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
+ reg = ~ORION_SPI_MODE_MASK;
+ if (spi-mode SPI_CPOL)
+ reg |= ORION_SPI_MODE_CPOL;
+ if (spi-mode SPI_CPHA)
+ reg |= ORION_SPI_MODE_CPHA;
+ writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
+}
+
/*
* called only when no transfer is active on the bus
*/
@@ -142,6 +163,8 @@ orion_spi_setup_transfer(struct spi_device *spi, struct
spi_transfer *t)
if ((t != NULL) t-bits_per_word)
bits_per_word = t-bits_per_word;
+ orion_spi_mode_set(spi);
+
rc = orion_spi_baudrate_set(spi, speed);
if (rc)
return rc;
@@ -399,7 +422,7 @@ static int __init orion_spi_probe(struct platform_device
*pdev)
}
/* we support only mode 0, and no options */
- master-mode_bits = 0;
+ master-mode_bits = SPI_CPHA | SPI_CPOL;
The comment no longer seems valid. ;-) Also, you are unconditionally
enabling these modes. Do all users of this driver support this?
thx,
Jason.
master-setup = orion_spi_setup;
master-transfer_one_message = orion_spi_transfer_one_message;
--
1.7.5.4
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Re: [PATCH] ARM: Kirkwood: Add SPI_CHPA and SPI_CPOL support to spi-orion
On Wed, Nov 21, 2012 at 02:35:52PM -0500, Jason Cooper wrote: /* we support only mode 0, and no options */ - master-mode_bits = 0; + master-mode_bits = SPI_CPHA | SPI_CPOL; The comment no longer seems valid. ;-) Also, you are unconditionally enabling these modes. Do all users of this driver support this? Right on the comment.. Not sure about your second query? * @mode_bits: flags understood by this controller driver The mode_bits need to be set so the mid layer will allow consumers to pass them down through spi-mode when it calls into orion_spi_setup_transfer. So that looks correct.. Now, it seems a fair question what mode the driver will run in by default now.. Previously, the driver didn't change the CPOL and CPHA bits, so whatever the boot firmware left them at will be the mode it uses. If SPI consumers are not properly requesting the proper CPOL/CPHA operation and instead relying on the boot firmware to leave the proper bit settings then things will break for those users (they will need to update their board's DT file, or otherwise) - but I don't see any way to address that and implement proper programmable support? This could affect at least dove, dreamplug, ts219 and lsxl. Jason -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
RE: [PATCH] SPI: SSP SPI Controller driver
+ if (chip_info-enable_loopback) + chip-cr1 |= SSCR1_LBM; Who sets the enable_loopback? [Chao] 'enable_loopback' could be configured by SPI Protocol driver before it setup SPI controller. Generally it is not set by default because it's used for test and validation. Thanks From: Shubhrajyoti Datta [mailto:omaplinuxker...@gmail.com] Sent: Wednesday, November 21, 2012 8:08 PM To: Bi, Chao Cc: grant.lik...@secretlab.ca; Chen, Jun D; spi-devel-general@lists.sourceforge.net; a...@linux.intel.com; Mills, Ken K; Centelles, Sylvain Subject: Re: [PATCH] SPI: SSP SPI Controller driver On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.commailto:chao...@intel.com wrote: This patch is to implement SSP SPI controller driver, which has been applied and validated on intel Moorestown Medfield platform. The patch are originated by Ken Mills ken.k.mi...@intel.commailto:ken.k.mi...@intel.com and Sylvain Centelles sylvain.centel...@intel.commailto:sylvain.centel...@intel.com, and to be further developed by Channing chao...@intel.commailto:chao...@intel.com and Chen Jun jun.d.c...@intel.commailto:jun.d.c...@intel.com according to their integration validation on Medfield platform. Signed-off-by: Ken Mills ken.k.mi...@intel.commailto:ken.k.mi...@intel.com Signed-off-by: Sylvain Centelles sylvain.centel...@intel.commailto:sylvain.centel...@intel.com Signed-off-by: channing chao...@intel.commailto:chao...@intel.com Signed-off-by: Chen Jun jun.d.c...@intel.commailto:jun.d.c...@intel.com --- drivers/spi/Kconfig |9 + drivers/spi/Makefile |1 + drivers/spi/spi-intel-mid-ssp.c | 1407 + include/linux/spi/spi-intel-mid-ssp.h | 326 4 files changed, 1743 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-intel-mid-ssp.c create mode 100644 include/linux/spi/spi-intel-mid-ssp.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1acae35..8b4461b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -179,6 +179,15 @@ config SPI_IMX This enables using the Freescale i.MX SPI controllers in master mode. +config SPI_INTEL_MID_SSP + tristate SSP SPI controller driver for Intel MID platforms + depends on SPI_MASTER INTEL_MID_DMAC + help + This is the unified SSP SPI master controller driver for + the Intel MID platforms, handling Moorestown Medfield, + master clock mode. + It supports Bulverde SSP core. + config SPI_LM70_LLP tristate Parallel port adapter for LM70 eval board (DEVELOPMENT) depends on PARPORT EXPERIMENTAL diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c48df47..83f06d0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_SPI_FSL_ESPI)+= spi-fsl-espi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o obj-$(CONFIG_SPI_GPIO) += spi-gpio.o obj-$(CONFIG_SPI_IMX) += spi-imx.o +obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c new file mode 100644 index 000..8fca48f --- /dev/null +++ b/drivers/spi/spi-intel-mid-ssp.c @@ -0,0 +1,1407 @@ +/* + * spi-intel-mid-ssp.c + * This driver supports Bulverde SSP core used on Intel MID platforms + * It supports SSP of Moorestown Medfield platforms and handles clock + * slave master modes. + * + * Copyright (c) 2010, Intel Corporation. + * Ken Mills ken.k.mi...@intel.commailto:ken.k.mi...@intel.com + * Sylvain Centelles sylvain.centel...@intel.commailto:sylvain.centel...@intel.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +/* + * Note: + * + * Supports DMA and non-interrupt polled transfers. + * + */ + +#include linux/delay.h +#include linux/interrupt.h +#include linux/highmem.h +#include linux/pci.h +#include linux/init.h +#include linux/interrupt.h +#include linux/dma-mapping.h +#include linux/intel_mid_dma.h +#include linux/pm_qos.h +#include linux/module.h + +#include linux/spi/spi.h +#include
Re: [PATCH] SPI: SSP SPI Controller driver
On Wed, Nov 21, 2012 at 5:56 PM, Alan Cox a...@linux.intel.com wrote: On Wed, 21 Nov 2012 17:44:21 +0530 Shubhrajyoti Datta omaplinuxker...@gmail.com wrote: On Wed, Nov 21, 2012 at 7:46 AM, chao bi chao...@intel.com wrote: + /* Create the PM_QOS request */ + if (drv_context-quirks QUIRKS_USE_PM_QOS) + pm_qos_add_request(drv_context-pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); What happens if the flag is not set if it is absolutely necessary for the driver it should not be a configurable option If you read through the code it's set only when the device is Moorestown/Oaktrail based and only in slave mode. It is not necessary in other configurations. Thats what I was trying to understand. If I am not wrong the latency is time related. Why only some platforms / modes need it also the value is not speed dependent. My doubt is that the time taken for the dma will be more in lower speed so the latency constraint could be relaxed. Also the spi core today doesnt have slave mode support thats a different discussion altogether may be we can leave it for now. Alan -- Monitor your physical, virtual and cloud infrastructure from a single web console. Get in-depth insight into apps, servers, databases, vmware, SAP, cloud infrastructure, etc. Download 30-day Free Trial. Pricing starts from $795 for 25 servers or applications! http://p.sf.net/sfu/zoho_dev2dev_nov ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
