Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Thu, Feb 03, 2011 at 03:04:32PM +, Alan Cox wrote: > Mark Brown wrote: > > I've got the same question here as I had with Russ' patch: it looks like > > there's some overlap with the SSP ports used for audio (it's just a > > generic programmable serial port so even if it's not normally used for > > audio that's a possiblity), how is that handled? > The SSP has PCI configuration indicating how it is being assigned, which > is in vendor capability byte 6. The low 3 bits indicte the mode, where > mode 1 is an SPI master/slave, and in that case bit 6 is set for a slave. OK, cool - just checking as it's a common issue for these generic serial ports. -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Thu, 3 Feb 2011 13:28:00 + Mark Brown wrote: > On Wed, Feb 02, 2011 at 10:40:54PM +, Alan Cox wrote: > > > And this is the unified one that handles all the devices, but I gather > > may need some fixing/test work on Medfield. > > I've got the same question here as I had with Russ' patch: it looks like > there's some overlap with the SSP ports used for audio (it's just a > generic programmable serial port so even if it's not normally used for > audio that's a possiblity), how is that handled? The SSP has PCI configuration indicating how it is being assigned, which is in vendor capability byte 6. The low 3 bits indicte the mode, where mode 1 is an SPI master/slave, and in that case bit 6 is set for a slave. The SSP/SPI driver will only grab ports that have been assigned to that purpose as part of the system design. I'm just putting the other bits from the generic driver back into the more featured/tested specific driver that Russ posted. Alan -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Wed, Feb 02, 2011 at 10:40:54PM +, Alan Cox wrote: > And this is the unified one that handles all the devices, but I gather > may need some fixing/test work on Medfield. I've got the same question here as I had with Russ' patch: it looks like there's some overlap with the SSP ports used for audio (it's just a generic programmable serial port so even if it's not normally used for audio that's a possiblity), how is that handled? -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Wed, 2 Feb 2011 13:01:52 -0800 Russ Gorby wrote: > SPI master controller driver for the Intel MID platform Medfield > This driver uses the Penwell SSP controller and configures it to > be a SPI device (spibus 3). This bus supports a single device - > the 3G SPI modem that can operate up to 25Mhz. NAK this. We have an existing development driver that covers 0x0815, 0x0816, 0x0825, 0x0832 in a single driver which needs tidying up and double checking on all the relevant Medfield and Moorestown devices and is based on work done by Mathieu Soulard. All these devices can be handled by a single driver, and should be. Alan -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Wed, 2 Feb 2011 13:01:52 -0800
Russ Gorby wrote:
> SPI master controller driver for the Intel MID platform Medfield
> This driver uses the Penwell SSP controller and configures it to
> be a SPI device (spibus 3). This bus supports a single device -
> the 3G SPI modem that can operate up to 25Mhz.
And this is the unified one that handles all the devices, but I gather
may need some fixing/test work on Medfield.
(and the only reason you haven't seen this submitted yet is I was
asked to wait until it had been tested on those platforms. So I'm
very surprised to see the other submission)
Alan
--
From: Mathieu SOULARD
intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD
[Ported to the -next tree DMA engine]
Signed-off-by: Alan Cox
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9..6d1a41f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -178,6 +178,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate "SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)"
+ depends on SPI_MASTER && INTEL_MID_DMAC && EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown & Medfield, master & slave
+ clock mode.
+
config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 86d1b5f..6e052b5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
obj-$(CONFIG_SPI_IMX) += spi_imx.o
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= intel_mid_ssp_spi.o
obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
obj-$(CONFIG_SPI_PXA2XX_PCI) += pxa2xx_spi_pci.o
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
new file mode 100644
index 000..2d6d881
--- /dev/null
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -0,0 +1,1403 @@
+/*
+ * intel_mid_ssp_spi.c
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports SSP of Moorestown & Medfield platforms and handles clock
+ * slave & master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills
+ * Sylvain Centelles
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "intel_mid_ssp_spi.h"
+
+#define DRIVER_NAME "intel_mid_ssp_spi_unified"
+
+MODULE_AUTHOR("Ken Mills");
+MODULE_DESCRIPTION("Bulverde SSP core SPI contoller");
+MODULE_LICENSE("GPL");
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len < sz ? len : sz);
+ int tlen2 = ((len - sz) > sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p < buf + tlen1)
+ sprintf(msg, "%s%02x", msg, (unsigned int)*p++);
+
+ if (tlen2 > 0) {
+ sprintf(msg, "%s .", msg);
+ p = (buf+len) - tlen2;
+ while (p < buf + len)
+ sprintf(msg, "%s%02x", msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, "DUMP: %p[0:%d ... %d:%d]:%s", buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context->ioaddr);
+ if ((sssr & SSSR_TFL_MASK) || (sssr & SSSR_TNF) == 0)
+ return 0;
+ else
+ ret
Re: [PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
On Wed, Feb 02, 2011 at 01:01:52PM -0800, Russ Gorby wrote: > SPI master controller driver for the Intel MID platform Medfield > This driver uses the Penwell SSP controller and configures it to > be a SPI device (spibus 3). This bus supports a single device - > the 3G SPI modem that can operate up to 25Mhz. The same hardware is also used for audio I believe - how do the two drivers share the hardware? > +#define SSCR0_DSS (0x000f) /* Data Size Select (mask) */ > +#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ > +#define SSCR0_FRF (0x0030) /* FRame Format (mask) */ > +#define SSCR0_Motorola (0x0 << 4) /* Motorola's SPI mode > */ > +#define SSCR0_ECS (1 << 6) /* External clock select */ > +#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ There certainly looks to be overlap with the register definitions. -- Special Offer-- Download ArcSight Logger for FREE (a $49 USD value)! Finally, a world-class log management solution at an even better price-free! Download using promo code Free_Logger_4_Dev2Dev. Offer expires February 28th, so secure your free ArcSight Logger TODAY! http://p.sf.net/sfu/arcsight-sfd2d ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH 1/1] spi: intel_mid_ssp_spi: new SPI driver for intel Medfield platform
SPI master controller driver for the Intel MID platform Medfield
This driver uses the Penwell SSP controller and configures it to
be a SPI device (spibus 3). This bus supports a single device -
the 3G SPI modem that can operate up to 25Mhz.
Signed-off-by: Russ Gorby
---
drivers/spi/Kconfig |7 +
drivers/spi/Makefile|1 +
drivers/spi/intel_mid_ssp_spi.c | 1507 +++
drivers/spi/intel_mid_ssp_spi_def.h | 139
4 files changed, 1654 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/intel_mid_ssp_spi.c
create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9..60ba339 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -178,6 +178,13 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate "SSP SPI controller driver for Intel Medfield platform"
+ depends on SPI_MASTER && INTEL_MID_DMAC
+ help
+ This is the SPI master controller driver for the Intel
+ Medfield MID platform.
+
config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 86d1b5f..c64deb9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
+obj-$(CONFIG_SPI_INTEL_MID_SSP) += intel_mid_ssp_spi.o
# special build for s3c24xx spi driver with fiq support
spi_s3c24xx_hw-y := spi_s3c24xx.o
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
new file mode 100644
index 000..19c62bc
--- /dev/null
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -0,0 +1,1507 @@
+/*
+ * intel_mid_ssp_spi.c - Penwell SPI master controller driver
+ * based on pxa2xx.c
+ *
+ * Copyright (C) Intel 2010
+ * Ken Mills
+ * Russ Gorby
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
+ * USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_mid_ssp_spi_def.h"
+
+#define DRIVER_NAME"intel_mid_ssp_spi"
+#define PCI_DMAC_MAXDI 2047
+#define PCI_DMAC_ID0x0827
+/* PM QoS define */
+#define MIN_EXIT_LATENCY 20
+
+#define TESTMODE_COMMON_MASK 0x00ff
+#define TESTMODE_PRIV_MASK 0xff00
+#define TESTMODE_ENABLE_DMA0x01
+#define TESTMODE_ENABLE_POLL 0x02
+#define TESTMODE_ENABLE_LOOPBACK 0x04
+#define TESTMODE_ENABLE_INTR 0x08
+#define TESTMODE(x)(testmode & x)
+static unsigned int testmode = (TESTMODE_ENABLE_DMA | TESTMODE_ENABLE_POLL);
+
+module_param(testmode, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(testmode, "supply test mode bits");
+
+MODULE_AUTHOR("Intel");
+MODULE_DESCRIPTION("Penwell SPI3 Master Contoller");
+MODULE_LICENSE("GPL");
+
+#define RX_THRESH_DFLT 8
+#define TX_THRESH_DFLT 8
+#define TIMOUT_DFLT1000
+
+/*
+ * For testing SSCR1 changes that require SSP restart, basically
+ * everything except the service and interrupt enables
+ */
+
+#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
+ | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
+ | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
+ | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
+ | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
+ | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
+
+#define PNWL_SSPSP (SSPSP_FSRT | SSPSP_SFRMWDTH(1) | SSPSP_SFRMP | \
+ SSPSP_SCMODE(3))
+
+/*
+ * clock divider
+ * 8 bpw
+ * TUR/ROR do not generate interrupt
+ * SPI mode operation
+ * SSP enabled
+ */
+#define PNWL_CR0(clk, bits, spi, chip) \
+ ((SSCR0_SerClkDiv(clk) & SSCR0_SCR) | \
+SSCR0_Motorola | \
+SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | \
+SSCR0_SSE |
