Re: [PATCH 1/8] Intel SPI master controller driver for the Medfield platform
On Wed, Feb 09, 2011 at 10:07:02AM +, Alan Cox wrote:
> From: Russ Gorby
>
> SPI master controller driver for the Intel MID platform Medfield
> This driver uses the Penwell SSP controller and configures it to
> be a SPI device (spibus 3). This bus supports a single device -
> the 3G SPI modem that can operate up to 25Mhz.
>
> Signed-off-by: Russ Gorby
> Signed-off-by: Alan Cox
Heh, I think I should have replied to this one instead of my earlier
patch, but I'll reply here too for completeness. On brief glance it
looks like some of my comments no longer apply in this version. Also,
I'm not being as thorough, so most of the comments now will probably
be pretty surface issues.
g.
> ---
>
> drivers/spi/Kconfig |7
> drivers/spi/Makefile|1
> drivers/spi/intel_mid_ssp_spi.c | 1507
> +++
> drivers/spi/intel_mid_ssp_spi_def.h | 139 +++
Please rename to spi_intel_mid_ssp.c. I'm asking for all new spi
drivers to use spi_ as a prefix.
> 4 files changed, 1654 insertions(+), 0 deletions(-)
> create mode 100644 drivers/spi/intel_mid_ssp_spi.c
> create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h
>
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index bb233a9..60ba339 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -178,6 +178,13 @@ config SPI_IMX
> This enables using the Freescale i.MX SPI controllers in master
> mode.
>
> +config SPI_INTEL_MID_SSP
> + tristate "SSP SPI controller driver for Intel Medfield platform"
> + depends on SPI_MASTER && INTEL_MID_DMAC
> + help
> + This is the SPI master controller driver for the Intel
> + Medfield MID platform.
> +
> config SPI_LM70_LLP
> tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
> depends on PARPORT && EXPERIMENTAL
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 86d1b5f..c64deb9 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI)+= spi_sh_sci.o
> obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
> obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
> obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
> +obj-$(CONFIG_SPI_INTEL_MID_SSP) += intel_mid_ssp_spi.o
>
> # special build for s3c24xx spi driver with fiq support
> spi_s3c24xx_hw-y := spi_s3c24xx.o
> diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
> new file mode 100644
> index 000..19c62bc
> --- /dev/null
> +++ b/drivers/spi/intel_mid_ssp_spi.c
> @@ -0,0 +1,1507 @@
> +/*
> + * intel_mid_ssp_spi.c - Penwell SPI master controller driver
> + * based on pxa2xx.c
> + *
> + * Copyright (C) Intel 2010
> + * Ken Mills
> + * Russ Gorby
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> + * USA
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "intel_mid_ssp_spi_def.h"
No need for the separate include since there are no other users. Just
roll the contents of the header into the .c file.
> +
> +#define DRIVER_NAME "intel_mid_ssp_spi"
> +#define PCI_DMAC_MAXDI 2047
> +#define PCI_DMAC_ID 0x0827
> +/* PM QoS define */
> +#define MIN_EXIT_LATENCY 20
> +
> +#define TESTMODE_COMMON_MASK 0x00ff
> +#define TESTMODE_PRIV_MASK 0xff00
> +#define TESTMODE_ENABLE_DMA 0x01
> +#define TESTMODE_ENABLE_POLL 0x02
> +#define TESTMODE_ENABLE_LOOPBACK 0x04
> +#define TESTMODE_ENABLE_INTR 0x08
> +#define TESTMODE(x) (testmode & x)
> +static unsigned int testmode = (TESTMODE_ENABLE_DMA | TESTMODE_ENABLE_POLL);
> +
> +module_param(testmode, uint, S_IRUGO|S_IWUSR);
> +MODULE_PARM_DESC(testmode, "supply test mode bits");
> +
> +MODULE_AUTHOR("Intel");
> +MODULE_DESCRIPTION("Penwell SPI3 Master Contoller");
> +MODULE_LICENSE("GPL");
> +
> +#define RX_THRESH_DFLT 8
> +#define TX_THRESH_DFLT 8
> +#define TIMOUT_DFLT 1000
> +
> +/*
> + * For testing SSCR1 changes that require SSP restart, basically
> + * everything except the service and interrupt enables
> + */
> +
> +#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
> +
[PATCH 1/8] Intel SPI master controller driver for the Medfield platform
From: Russ Gorby
SPI master controller driver for the Intel MID platform Medfield
This driver uses the Penwell SSP controller and configures it to
be a SPI device (spibus 3). This bus supports a single device -
the 3G SPI modem that can operate up to 25Mhz.
Signed-off-by: Russ Gorby
Signed-off-by: Alan Cox
---
drivers/spi/Kconfig |7
drivers/spi/Makefile|1
drivers/spi/intel_mid_ssp_spi.c | 1507 +++
drivers/spi/intel_mid_ssp_spi_def.h | 139 +++
4 files changed, 1654 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/intel_mid_ssp_spi.c
create mode 100644 drivers/spi/intel_mid_ssp_spi_def.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bb233a9..60ba339 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -178,6 +178,13 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate "SSP SPI controller driver for Intel Medfield platform"
+ depends on SPI_MASTER && INTEL_MID_DMAC
+ help
+ This is the SPI master controller driver for the Intel
+ Medfield MID platform.
+
config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 86d1b5f..c64deb9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
+obj-$(CONFIG_SPI_INTEL_MID_SSP) += intel_mid_ssp_spi.o
# special build for s3c24xx spi driver with fiq support
spi_s3c24xx_hw-y := spi_s3c24xx.o
diff --git a/drivers/spi/intel_mid_ssp_spi.c b/drivers/spi/intel_mid_ssp_spi.c
new file mode 100644
index 000..19c62bc
--- /dev/null
+++ b/drivers/spi/intel_mid_ssp_spi.c
@@ -0,0 +1,1507 @@
+/*
+ * intel_mid_ssp_spi.c - Penwell SPI master controller driver
+ * based on pxa2xx.c
+ *
+ * Copyright (C) Intel 2010
+ * Ken Mills
+ * Russ Gorby
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
+ * USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "intel_mid_ssp_spi_def.h"
+
+#define DRIVER_NAME"intel_mid_ssp_spi"
+#define PCI_DMAC_MAXDI 2047
+#define PCI_DMAC_ID0x0827
+/* PM QoS define */
+#define MIN_EXIT_LATENCY 20
+
+#define TESTMODE_COMMON_MASK 0x00ff
+#define TESTMODE_PRIV_MASK 0xff00
+#define TESTMODE_ENABLE_DMA0x01
+#define TESTMODE_ENABLE_POLL 0x02
+#define TESTMODE_ENABLE_LOOPBACK 0x04
+#define TESTMODE_ENABLE_INTR 0x08
+#define TESTMODE(x)(testmode & x)
+static unsigned int testmode = (TESTMODE_ENABLE_DMA | TESTMODE_ENABLE_POLL);
+
+module_param(testmode, uint, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(testmode, "supply test mode bits");
+
+MODULE_AUTHOR("Intel");
+MODULE_DESCRIPTION("Penwell SPI3 Master Contoller");
+MODULE_LICENSE("GPL");
+
+#define RX_THRESH_DFLT 8
+#define TX_THRESH_DFLT 8
+#define TIMOUT_DFLT1000
+
+/*
+ * For testing SSCR1 changes that require SSP restart, basically
+ * everything except the service and interrupt enables
+ */
+
+#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
+ | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
+ | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
+ | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
+ | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
+ | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
+
+#define PNWL_SSPSP (SSPSP_FSRT | SSPSP_SFRMWDTH(1) | SSPSP_SFRMP | \
+ SSPSP_SCMODE(3))
+
+/*
+ * clock divider
+ * 8 bpw
+ * TUR/ROR do not generate interrupt
+ * SPI mode operation
+ * SSP enabled
+ */
+#define PNWL_CR0(clk, bits, spi, chip) \
+ ((SSCR0_SerClkDiv(clk) & SSCR0_SCR) | \
+SSCR0_Motorola | \
+SSCR0_DataSize(bits > 16 ? bits - 16 : bits) |
