Re: [PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
On Wed, Feb 08, 2012 at 10:41:10AM +, Alan Cox wrote:
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Queueing and runtime pm added]
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
[Ported to the -next tree DMA engine]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|2
drivers/spi/spi-intel-mid-ssp.c | 1426
+++
drivers/spi/spi-intel-mid-ssp.h | 308
If this is merging several of the drivers, what is the plan for the existing
SPI_DESIGNWARE and SPI_TOPCLIFF_PCH drivers? Or are those for different
devices?
...
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..e81757a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
-
+obj-$(CONFIG_SPI_INTEL_MID_SSP) += spi-intel-mid-ssp.o
I'm trying to keep this list alphabetized.
...
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int
sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+len-tlen2, len - 1, msg);
+}
+#endif
Yet another hex dump debug utility function? What about lib/hexdump.c?
...
diff --git a/drivers/spi/spi-intel-mid-ssp.h b/drivers/spi/spi-intel-mid-ssp.h
new file mode 100644
index 000..11fad57
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.h
How much of this stuff is actually needed in a .h file? If it is only used
by the .c file, then I want it moved there.
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) Intel 2009
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ *
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * ~~
+ *
+ */
+#ifndef SPI_INTEL_MID_SSP_H_
+#define SPI_INTEL_MID_SSP_H_
+
+#define PCI_MRST_DMAC1_ID0x0814
+#define PCI_MDFL_DMAC1_ID0x0827
+
+#define SSP_NOT_SYNC 0x40
+#define MAX_SPI_TRANSFER_SIZE 8192
+#define MAX_BITBANGING_LOOP 1
+#define SPI_FIFO_SIZE 16
+
+/* PM QoS define */
+#define MIN_EXIT_LATENCY 20
+
+/* SSP assignement configuration from PCI config */
+#define SSP_CFG_GET_MODE(ssp_cfg)((ssp_cfg) 0x07)
+#define SSP_CFG_GET_SPI_BUS_NB(ssp_cfg) (((ssp_cfg) 3) 0x07)
+#define SSP_CFG_IS_SPI_SLAVE(ssp_cfg)((ssp_cfg) 0x40)
+#define SSP_CFG_SPI_MODE_ID 1
+/* adid field offset is 6 inside the vendor specific capability */
+#define VNDR_CAPABILITY_ADID_OFFSET 6
+
+/* Driver's quirk flags */
+/* This workarround bufferizes data in the audio fabric SDRAM from */
+/* where the DMA transfers will operate. Should be enabled only for */
+/* SPI slave mode. */
+#define QUIRKS_DMA_USE_NO_TRAIL 2
+/* If set, the driver will use PM_QOS to reduce the latency */
+/* introduced by the deeper C-states which may produce over/under */
+/* run issues. Must be used in slave mode. In master mode, the */
+/* latency is not critical, but setting this workarround may */
+/* improve the SPI
Re: [PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
Hi Grant, On Thu, 9 Feb 2012 07:31:21 -0800 Grant Likely grant.lik...@secretlab.ca wrote: On Wed, Feb 08, 2012 at 10:41:10AM +, Alan Cox wrote: From: Mathieu SOULARD mathieux.soul...@intel.com This driver is a fusion of various internal drivers into a single driver for the SPI slave/master on the Intel Moorestown and Medfield SSP devices. Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com [Queueing and runtime pm added] Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com [Ported to the -next tree DMA engine] Signed-off-by: Alan Cox a...@linux.intel.com --- drivers/spi/Kconfig |8 drivers/spi/Makefile|2 drivers/spi/spi-intel-mid-ssp.c | 1426 +++ drivers/spi/spi-intel-mid-ssp.h | 308 If this is merging several of the drivers, what is the plan for the existing SPI_DESIGNWARE and SPI_TOPCLIFF_PCH drivers? Or are those for different devices? The DESIGNWARE controller has a different HW IP core, so the 2 drivers can't be merged. And for the TOPCLIFF one, seems it also use a different HW IP than this one, so I guess it can't be merged either. Thanks, Feng -- Virtualization Cloud Management Using Capacity Planning Cloud computing makes use of virtualization - but cloud computing also focuses on allowing computing to be delivered as a service. http://www.accelacomm.com/jaw/sfnl/114/51521223/ ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
[PATCH RESEND] intel_mid_ssp_spi: Moorestown and Medfield SPI for SSP devices
From: Mathieu SOULARD mathieux.soul...@intel.com
This driver is a fusion of various internal drivers into a single
driver for the SPI slave/master on the Intel Moorestown and Medfield
SSP devices.
Signed-off-by: Mathieu SOULARD mathieux.soul...@intel.com
[Queueing and runtime pm added]
Signed-off-by: Kristen Carlson Accardi kris...@linux.intel.com
[Ported to the -next tree DMA engine]
Signed-off-by: Alan Cox a...@linux.intel.com
---
drivers/spi/Kconfig |8
drivers/spi/Makefile|2
drivers/spi/spi-intel-mid-ssp.c | 1426 +++
drivers/spi/spi-intel-mid-ssp.h | 308
4 files changed, 1743 insertions(+), 1 deletions(-)
create mode 100644 drivers/spi/spi-intel-mid-ssp.c
create mode 100644 drivers/spi/spi-intel-mid-ssp.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8293658..90b7ef6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -163,6 +163,14 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_INTEL_MID_SSP
+ tristate SSP SPI controller driver for Intel MID platforms
(EXPERIMENTAL)
+ depends on SPI_MASTER INTEL_MID_DMAC EXPERIMENTAL
+ help
+ This is the unified SSP SPI slave controller driver for the Intel
+ MID platforms, handling Moorestown Medfield, master slave
+ clock mode.
+
config SPI_LM70_LLP
tristate Parallel port adapter for LM70 eval board (DEVELOPMENT)
depends on PARPORT EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 61c3261..e81757a 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -58,4 +58,4 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
-
+obj-$(CONFIG_SPI_INTEL_MID_SSP)+= spi-intel-mid-ssp.o
diff --git a/drivers/spi/spi-intel-mid-ssp.c b/drivers/spi/spi-intel-mid-ssp.c
new file mode 100644
index 000..77bff9f
--- /dev/null
+++ b/drivers/spi/spi-intel-mid-ssp.c
@@ -0,0 +1,1426 @@
+/*
+ * This driver supports Bulverde SSP core used on Intel MID platforms
+ * It supports the SSP of Medfield platforms and handles clock
+ * slave master modes.
+ *
+ * Copyright (c) 2010, Intel Corporation.
+ * Ken Mills ken.k.mi...@intel.com
+ * Sylvain Centelles sylvain.centel...@intel.com
+ * Mathieu SOULARD
+ * Kristen Carlson Accardi kris...@linux.intel.com
+ * Alan Cox a...@linux.intel.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+/*
+ * Note:
+ *
+ * Supports DMA and non-interrupt polled transfers.
+ *
+ */
+
+#include linux/module.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/highmem.h
+#include linux/pci.h
+#include linux/init.h
+#include linux/interrupt.h
+#include linux/dma-mapping.h
+#include linux/intel_mid_dma.h
+#include linux/pm_qos.h
+#include linux/pm_runtime.h
+
+#include linux/spi/spi.h
+#include spi-intel-mid-ssp.h
+
+#define DRIVER_NAME spi-intel-mid-ssp
+
+MODULE_AUTHOR(Ken Mills);
+MODULE_DESCRIPTION(Bulverde SSP core SPI contoller);
+MODULE_LICENSE(GPL);
+
+static const struct pci_device_id pci_ids[];
+
+#ifdef DUMP_RX
+static void dump_trailer(const struct device *dev, char *buf, int len, int sz)
+{
+ int tlen1 = (len sz ? len : sz);
+ int tlen2 = ((len - sz) sz) ? sz : (len - sz);
+ unsigned char *p;
+ static char msg[MAX_SPI_TRANSFER_SIZE];
+
+ memset(msg, '\0', sizeof(msg));
+ p = buf;
+ while (p buf + tlen1)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+
+ if (tlen2 0) {
+ sprintf(msg, %s ., msg);
+ p = (buf+len) - tlen2;
+ while (p buf + len)
+ sprintf(msg, %s%02x, msg, (unsigned int)*p++);
+ }
+
+ dev_info(dev, DUMP: %p[0:%d ... %d:%d]:%s, buf, tlen1 - 1,
+ len-tlen2, len - 1, msg);
+}
+#endif
+
+static inline u32 is_tx_fifo_empty(struct ssp_driver_context *drv_context)
+{
+ u32 sssr;
+ sssr = read_SSSR(drv_context-ioaddr);
+ if ((sssr SSSR_TFL_MASK) || (sssr SSSR_TNF) == 0)
+ return 0;
+ else
+ return 1;
+}
+
