Re: [PATCH] spi: tle620x: add missing device_remove_file()
On 11/05/11 13:39, Axel Lin wrote: This patch includes below fixes: 1. Add missing device_remove_file for dev_attr_status_show in tle62x0_remove. 2. Fix tle62x0_probe error handling: Currently, if the error happens when ptr 0, gpio_attrs[0] is not properly remove. Signed-off-by: Axel Linaxel@gmail.com Acked-by: Ben Dooks ben-li...@fluff.org --- drivers/spi/tle62x0.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/spi/tle62x0.c b/drivers/spi/tle62x0.c index a393895..32a4087 100644 --- a/drivers/spi/tle62x0.c +++ b/drivers/spi/tle62x0.c @@ -283,7 +283,7 @@ static int __devinit tle62x0_probe(struct spi_device *spi) return 0; err_gpios: - for (; ptr 0; ptr--) + while (--ptr= 0) device_remove_file(spi-dev, gpio_attrs[ptr]); device_remove_file(spi-dev,dev_attr_status_show); @@ -301,6 +301,7 @@ static int __devexit tle62x0_remove(struct spi_device *spi) for (ptr = 0; ptr st-nr_gpio; ptr++) device_remove_file(spi-dev, gpio_attrs[ptr]); + device_remove_file(spi-dev,dev_attr_status_show); kfree(st); return 0; } -- Achieve unprecedented app performance and reliability What every C/C++ and Fortran developer should know. Learn how Intel has extended the reach of its next-generation tools to help boost performance applications - inlcuding clusters. http://p.sf.net/sfu/intel-dev2devmay ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
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Re: [QUERY] Behavior of spi slave memories w.r.t chip select signal.
On 05/11/2011 09:37 AM, viresh kumar wrote: Hello, Following is what i understood after reading m25p80 driver and spi master drivers in drivers/spi folder. chip_select signal controls start and end of transfer. For ex: if we have to read status reg of spi memory, then we use write_and_then_read() routine. which writes 0x9F in one spi transfer and writes dummy bytes and reads rx reg in other transfer. And these two transfers are part of single spi_message. Now, it is controllable to handle cs, and if we send cs_change == 0, then chip select is activated at start of message and deactivated at end of message, instead at end of every transfer. Which means, even if there is a delay between command and dummy bytes received at spi memory, current transfer will not be terminated by memory as cs is low. Is this correct?? Actually i am seeing a different behavior by some of the spi memories, like m25p10. If there is a delay between read_sts_reg command and dummy bytes, then 0xFF is returned in response. If there is no delay then transfer always passes. Linus, Jamie, Have you ever seen this kind of issue? Which spi slave memories did you used for testing? I am using standard pl0022 and m25p80 driver. Tried in all modes: polling, interrupt, dma. -- viresh -- Achieve unprecedented app performance and reliability What every C/C++ and Fortran developer should know. Learn how Intel has extended the reach of its next-generation tools to help boost performance applications - inlcuding clusters. http://p.sf.net/sfu/intel-dev2devmay ___ spi-devel-general mailing list spi-devel-general@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/spi-devel-general
