Re: svn commit: r321633 - in head/sys/arm: arm include

[Zbigniew Bodek]

2017-07-29 18:06 GMT+02:00 Ian Lepore <i...@freebsd.org>:
> On Thu, 2017-07-27 at 23:14 +, Zbigniew Bodek wrote:
>> Author: zbb
>> Date: Thu Jul 27 23:14:17 2017
>> New Revision: 321633
>> URL: https://svnweb.freebsd.org/changeset/base/321633
>>
>> Log:
>>   Fix TEX index acquisition using L2 attributes
>>
>>   The TEX index is selected using (TEX0 C B) bits
>>   from the L2 descriptor. Use correct index by masking
>>   and shifting those bits accordingly.
>>
>>   Differential Revision:  https://reviews.freebsd.org/D11703
>
> How did you guys discover this bug, like what were the symptoms?

Hello Ian,

We had bug in usage of  pmap_remap_vm_attr() and fixing it didn't help
for the issue so the second bug has been found here.

>  Should we consider merging this to 11-stable?

As far as I know nobody besides Armada38x is using this function in
HEAD and nobody uses it in 11.
You may merge it to 11 though (just for the safety of this code in the future).

>
> -- Ian
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svn commit: r321633 - in head/sys/arm: arm include

[Zbigniew Bodek]

Author: zbb
Date: Thu Jul 27 23:14:17 2017
New Revision: 321633
URL: https://svnweb.freebsd.org/changeset/base/321633

Log:
  Fix TEX index acquisition using L2 attributes
  
  The TEX index is selected using (TEX0 C B) bits
  from the L2 descriptor. Use correct index by masking
  and shifting those bits accordingly.
  
  Differential Revision:https://reviews.freebsd.org/D11703

Modified:
  head/sys/arm/arm/pmap-v6.c
  head/sys/arm/include/pte-v6.h

Modified: head/sys/arm/arm/pmap-v6.c
==
--- head/sys/arm/arm/pmap-v6.c  Thu Jul 27 23:09:12 2017(r321632)
+++ head/sys/arm/arm/pmap-v6.c  Thu Jul 27 23:14:17 2017(r321633)
@@ -525,8 +525,8 @@ pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t
int old_idx, new_idx;
 
/* Map VM memattrs to indexes to tex_class table. */
-   old_idx = pte2_attr_tab[(int)old_attr];
-   new_idx = pte2_attr_tab[(int)new_attr];
+   old_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)old_attr]);
+   new_idx = PTE2_ATTR2IDX(pte2_attr_tab[(int)new_attr]);
 
/* Replace TEX attribute and apply it. */
tex_class[old_idx] = tex_class[new_idx];

Modified: head/sys/arm/include/pte-v6.h
==
--- head/sys/arm/include/pte-v6.h   Thu Jul 27 23:09:12 2017
(r321632)
+++ head/sys/arm/include/pte-v6.h   Thu Jul 27 23:14:17 2017
(r321633)
@@ -149,10 +149,12 @@
 #defineL2_NX   0x0001  /* Not executable */
 #defineL2_B0x0004  /* Bufferable page */
 #defineL2_C0x0008  /* Cacheable page */
+#defineL2_CB_SHIFT 2   /* C,B bit field shift */
 #defineL2_AP(x)((x) << 4)
 #defineL2_AP0  0x0010  /* access permissions bit 0*/
 #defineL2_AP1  0x0020  /* access permissions bit 1*/
-#defineL2_TEX(x)   ((x) << 6)  /* type extension */
+#defineL2_TEX_SHIFT6   /* type extension field shift */
+#defineL2_TEX(x)   ((x) << L2_TEX_SHIFT)   /* type extension */
 #defineL2_TEX0 0x0040  /* type extension bit 0 */
 #defineL2_TEX1 0x0080  /* type extension bit 1 */
 #defineL2_TEX2 0x0100  /* type extension bit 2 */
@@ -271,6 +273,10 @@
 #definePTE2_FRAME  L2_S_FRAME
 
 #definePTE2_ATTR_MASK  (L2_TEX0 | L2_C | L2_B)
+/* PTE2 attributes to TEX class index: (TEX0 C B)  */
+#definePTE2_ATTR2IDX(attr) \
+attr) & (L2_C | L2_B)) >> L2_CB_SHIFT) |   \
+(((attr) & L2_TEX0) >> (L2_TEX_SHIFT - L2_CB_SHIFT)))
 
 #definePTE2_AP_KR  (PTE2_RO | PTE2_NM)
 #definePTE2_AP_KRW 0
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svn commit: r320880 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Mon Jul 10 22:11:30 2017
New Revision: 320880
URL: https://svnweb.freebsd.org/changeset/base/320880

Log:
  Fix error check for Rx mbuf allocation in ENA driver
  
  ena_alloc_rx_mbuf() will return positive error code
  on failure. Act accordingly.
  
  Submitted by: Krishna Yenduri 

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Mon Jul 10 21:55:24 2017(r320879)
+++ head/sys/dev/ena/ena.c  Mon Jul 10 22:11:30 2017(r320880)
@@ -1032,7 +1032,7 @@ ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t 
_ring->rx_buffer_info[next_to_use];
 
rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info);
-   if (rc < 0) {
+   if (rc != 0) {
device_printf(adapter->pdev,
"failed to alloc buffer for rx queue\n");
break;
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svn commit: r320731 - in stable/11: share/man/man4 sys/conf sys/contrib/ena-com sys/dev/ena sys/modules sys/modules/ena

[Zbigniew Bodek]

Author: zbb
Date: Thu Jul  6 11:45:13 2017
New Revision: 320731
URL: https://svnweb.freebsd.org/changeset/base/320731

Log:
  MFC r317518, r318647, r319197, r319198, r319199, r319200, r320625, r320626,
  r320628, r319201, r320629, r320630, r320631, r320632.
  
  r317518:
  Import Amazon Elastic Network Adapter (ENA) HAL to sys/contrib/
  
  Import from vendor-sys/ena-com/1.1.4.1
  SVN rev.: 317516
  Version: 1.1.4.1
  
  r318647:
  Add support for Amazon Elastic Network Adapter (ENA) NIC
  
  ENA is a networking interface designed to make good use of modern CPU
  features and system architectures.
  
  The ENA device exposes a lightweight management interface with a
  minimal set of memory mapped registers and extendable command set
  through an Admin Queue.
  
  The driver supports a range of ENA devices, is link-speed independent
  (i.e., the same driver is used for 10GbE, 25GbE, 40GbE, etc.), and has
  a negotiated and extendable feature set.
  
  Some ENA devices support SR-IOV. This driver is used for both the
  SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
  
  ENA devices enable high speed and low overhead network traffic
  processing by providing multiple Tx/Rx queue pairs (the maximum number
  is advertised by the device via the Admin Queue), a dedicated MSI-X
  interrupt vector per Tx/Rx queue pair, and CPU cacheline optimized
  data placement.
  
  The ENA driver supports industry standard TCP/IP offload features such
  as checksum offload and TCP transmit segmentation offload (TSO).
  Receive-side scaling (RSS) is supported for multi-core scaling.
  
  The ENA driver and its corresponding devices implement health
  monitoring mechanisms such as watchdog, enabling the device and driver
  to recover in a manner transparent to the application, as well as
  debug logs.
  
  Some of the ENA devices support a working mode called Low-latency
  Queue (LLQ), which saves several more microseconds. This feature will
  be implemented for driver in future releases.
  
  r319197:
  Add mbuf defragmentation to the ENA driver
  
  When mbuf chain is too long and device cannot handle that number
  of segments in DMA transaction, mbuf chain will be defragmented.
  Initially, driver was dropping all mbuf chains that were exceeding
  supported number of segments.
  
  r319198:
  Add locks before each ena_up and ena_down
  
  Lock only ena_up and ena_down calls in ioctl handler, instead of whole
  ioctl. Locking ioctl with sx lock that is sleepable, is not allowed in
  some cases, e.g. when multicast options are being changed.
  Additional locking was added in deatch function to prevent race condition
  with ioctl function.
  
  r319199:
  Add error handling to the ENA driver if init of the reset task fails
  
  Also, to simplify cleaning routine, reset task is initialized before
  allocating statistics and other resources.
  
  r319200:
  Move ENA's hw stats updating routine to separate task
  
  Initially, stats were being updated each time OS was requesting for
  the first statistic.
  To read statistics from hw, condvar was used. cv_timedwait cannot be
  called when unsleepable lock is held, and this happens when FreeBSD
  is requesting statistic.
  Seperate task is reading statistics from NIC each 1 second.
  
  r319201:
  Introduce additional locks when releasing TX resources and buffers in ENA
  
  There could be race condition with TX cleaning routine when cleaning mbufs,
  when it was called directly from main sending thread (ena_mq_start).
  
  r320625:
  Add missing lock upon initialization of the interface
  
  Lack of this lock was causing crash if down was called in
  parallel with the initialization routine.
  
  r320626:
  Acquire locks before calling drbr_flush()
  
  It is required to hold lock that is associated with buffer ring before
  flushing drbr.
  
  r320628:
  Unmask all IO irqs after driver state is set as running
  
  If driver left MSI-x handlling routine because interface was put down,
  it is not unmasking IRQs, so any requesting interrupt will be awaiting
  for unmasking.
  
  On ena_up() routine all interrupts are being unmasked and any awaiting
  interrupt will be handled right away.
  
  If handler was executed before driver state was set as running, handling
  routine is being ended immediately, leaving IO irqs for given queue
  masked.
  
  r320629:
  Call drbr_advance() before leaving TX routine
  
  If drbr_advance() is not called before doing cleanup and packet is
  already enqueued for sending (tx_info is holding pointer to mbuf), then
  mbuf is cleaned both in drbr_flush() and in cleanup routine, when all
  mbufs hold by tx_buffer_info are being released.
  
  This causes panic, because mbuf is released twice.
  
  r320630:
  Remove RX mtx from ENA driver
  
  RX lock is no longer required. There can only be one RX cleanup task
  running at a time, RX cleanup cannot be executed if interface is not
  yet initialized and ena_down() will not free any RX 

svn commit: r320632 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:10:29 2017
New Revision: 320632
URL: https://svnweb.freebsd.org/changeset/base/320632

Log:
  Replace mbuf defragmentation with collapse
  
  Collapse should be more effective than defragmentation.
  Added missing declaration of ena_check_and_collapse_mbuf().
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c
  head/sys/dev/ena/ena.h
  head/sys/dev/ena/ena_sysctl.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue Jul  4 00:08:47 2017(r320631)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:10:29 2017(r320632)
@@ -156,6 +156,8 @@ static void ena_update_hwassist(struct ena_adapter *);
 static int ena_setup_ifnet(device_t, struct ena_adapter *,
 struct ena_com_dev_get_features_ctx *);
 static voidena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *);
+static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring,
+struct mbuf **mbuf);
 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **);
 static voidena_start_xmit(struct ena_ring *);
 static int ena_mq_start(if_t, struct mbuf *);
@@ -2623,10 +2625,10 @@ ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct 
 }
 
 static int
-ena_check_and_defragment_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf)
+ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf)
 {
struct ena_adapter *adapter;
-   struct mbuf *defrag_mbuf;
+   struct mbuf *collapsed_mbuf;
int num_frags;
 
adapter = tx_ring->adapter;
@@ -2635,16 +2637,17 @@ ena_check_and_defragment_mbuf(struct ena_ring *tx_ring
/* One segment must be reserved for configuration descriptor. */
if (num_frags < adapter->max_tx_sgl_size)
return (0);
-   counter_u64_add(tx_ring->tx_stats.defragment, 1);
+   counter_u64_add(tx_ring->tx_stats.collapse, 1);
 
-   defrag_mbuf = m_defrag(*mbuf, M_NOWAIT);
-   if (defrag_mbuf == NULL) {
-   counter_u64_add(tx_ring->tx_stats.defragment_err, 1);
+   collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT,
+   adapter->max_tx_sgl_size - 1);
+   if (collapsed_mbuf == NULL) {
+   counter_u64_add(tx_ring->tx_stats.collapse_err, 1);
return (ENOMEM);
}
 
-   /* If mbuf was defragmented succesfully, original mbuf is released. */
-   *mbuf = defrag_mbuf;
+   /* If mbuf was collapsed succesfully, original mbuf is released. */
+   *mbuf = collapsed_mbuf;
 
return (0);
 }
@@ -2675,10 +2678,10 @@ ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **
 
ENA_ASSERT(*mbuf, "mbuf is NULL\n");
 
-   rc = ena_check_and_defragment_mbuf(tx_ring, mbuf);
+   rc = ena_check_and_collapse_mbuf(tx_ring, mbuf);
if (rc) {
ena_trace(ENA_WARNING,
-   "Failed to defragment mbuf! err: %d", rc);
+   "Failed to collapse mbuf! err: %d", rc);
return (rc);
}
 

Modified: head/sys/dev/ena/ena.h
==
--- head/sys/dev/ena/ena.h  Tue Jul  4 00:08:47 2017(r320631)
+++ head/sys/dev/ena/ena.h  Tue Jul  4 00:10:29 2017(r320632)
@@ -226,8 +226,8 @@ struct ena_stats_tx {
counter_u64_t doorbells;
counter_u64_t missing_tx_comp;
counter_u64_t bad_req_id;
-   counter_u64_t defragment;
-   counter_u64_t defragment_err;
+   counter_u64_t collapse;
+   counter_u64_t collapse_err;
 };
 
 struct ena_stats_rx {

Modified: head/sys/dev/ena/ena_sysctl.c
==
--- head/sys/dev/ena/ena_sysctl.c   Tue Jul  4 00:08:47 2017
(r320631)
+++ head/sys/dev/ena/ena_sysctl.c   Tue Jul  4 00:10:29 2017
(r320632)
@@ -156,13 +156,13 @@ ena_sysctl_add_stats(struct ena_adapter *adapter)
"stops", CTLFLAG_RD,
_stats->queue_stop, "Queue stops");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
-   "defragmentations", CTLFLAG_RD,
-   _stats->defragment,
-   "Mbuf defragmentations");
+   "mbuf_collapses", CTLFLAG_RD,
+   _stats->collapse,
+   "Mbuf collapse count");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
-   "defragmentation_err", CTLFLAG_RD,
-   _stats->defragment_err,
-   "Mbuf defragmentation failures");
+   "mbuf_collapse_err", CTLFLAG_RD,
+   _stats->collapse_err,
+   "Mbuf collapse failures");
 
/* RX specific stats */
rx_node = 

svn commit: r320631 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:08:47 2017
New Revision: 320631
URL: https://svnweb.freebsd.org/changeset/base/320631

Log:
  Fix creation of dma tags and TSO settings
  
  TSO settings were not reflecting real HW capabilities.
  
  DMA tags were created with wrong window - high address was the same as
  low, so excluding window was not working.
  
  Capabilities of TX dma transaction were not set properly - TSO max size
  had been increased and size of one segment had been adjusted.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c
  head/sys/dev/ena/ena.h

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue Jul  4 00:06:56 2017(r320630)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:08:47 2017(r320631)
@@ -226,16 +226,16 @@ ena_dma_alloc(device_t dmadev, bus_size_t size,
if (dma_space_addr == 0)
dma_space_addr = BUS_SPACE_MAXADDR;
error = bus_dma_tag_create(bus_get_dma_tag(dmadev), /* parent */
-   8, 0, /* alignment, bounds */
-   dma_space_addr,   /* lowaddr */
-   dma_space_addr,   /* highaddr */
-   NULL, NULL,   /* filter, filterarg */
-   maxsize,  /* maxsize */
-   1,/* nsegments */
-   maxsize,  /* maxsegsize */
-   BUS_DMA_ALLOCNOW, /* flags */
-   NULL, /* lockfunc */
-   NULL, /* lockarg */
+   8, 0, /* alignment, bounds  */
+   dma_space_addr,   /* lowaddr of exclusion window*/
+   BUS_SPACE_MAXADDR,/* highaddr of exclusion window   */
+   NULL, NULL,   /* filter, filterarg  */
+   maxsize,  /* maxsize*/
+   1,/* nsegments  */
+   maxsize,  /* maxsegsize */
+   BUS_DMA_ALLOCNOW, /* flags  */
+   NULL, /* lockfunc   */
+   NULL, /* lockarg*/
>tag);
if (error) {
device_printf(dmadev,
@@ -530,16 +530,16 @@ ena_setup_tx_dma_tag(struct ena_adapter *adapter)
 
/* Create DMA tag for Tx buffers */
ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev),
-   1, 0, /* alignment, bounds  */
-   ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr*/
-   ENA_DMA_BIT_MASK(adapter->dma_width), /* highaddr   */
-   NULL, NULL,   /* filter, filterarg  */
-   ENA_TSO_MAXSIZE,  /* maxsize*/
-   adapter->max_tx_sgl_size, /* nsegments  */
-   ENA_TSO_MAXSIZE,  /* maxsegsize */
-   0,/* flags  */
-   NULL, /* lockfunc   */
-   NULL, /* lockfuncarg*/
+   1, 0, /* alignment, bounds   */
+   ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window  */
+   BUS_SPACE_MAXADDR,/* highaddr of excl window */
+   NULL, NULL,   /* filter, filterarg   */
+   ENA_TSO_MAXSIZE,  /* maxsize */
+   adapter->max_tx_sgl_size - 1, /* nsegments   */
+   ENA_TSO_MAXSIZE,  /* maxsegsize  */
+   0,/* flags   */
+   NULL, /* lockfunc*/
+   NULL, /* lockfuncarg */
>tx_buf_tag);
 
if (ret != 0)
@@ -567,17 +567,17 @@ ena_setup_rx_dma_tag(struct ena_adapter *adapter)
int ret;
 
/* Create DMA tag for Rx buffers*/
-   ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */
-   1, 0, /* alignment, bounds  */
-   ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr*/
-   ENA_DMA_BIT_MASK(adapter->dma_width), /* highaddr   */
-   NULL, NULL,   /* filter, filterarg  */
-   MJUM16BYTES,  /* maxsize*/
-   1,/* nsegments  */
-   MJUM16BYTES,  /* maxsegsize */
-   0,/* flags  */
-   NULL, 

svn commit: r320630 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:06:56 2017
New Revision: 320630
URL: https://svnweb.freebsd.org/changeset/base/320630

Log:
  Remove RX mtx from ENA driver
  
  RX lock is no longer required. There can only be one RX cleanup task
  running at a time, RX cleanup cannot be executed if interface is not
  yet initialized and ena_down() will not free any RX resources if any io
  interrupt is being handled - RX cleanup task is only called from an
  interrupt handler.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue Jul  4 00:04:31 2017(r320629)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:06:56 2017(r320630)
@@ -476,7 +476,6 @@ ena_init_io_rings(struct ena_adapter *adapter)
device_get_nameunit(adapter->pdev), i);
 
mtx_init(>ring_mtx, txr->mtx_name, NULL, MTX_DEF);
-   mtx_init(>ring_mtx, rxr->mtx_name, NULL, MTX_DEF);
 
que = >que[i];
que->adapter = adapter;
@@ -509,7 +508,6 @@ ena_free_io_ring_resources(struct ena_adapter *adapter
sizeof(rxr->rx_stats));
 
mtx_destroy(>ring_mtx);
-   mtx_destroy(>ring_mtx);
 
drbr_free(txr->br, M_DEVBUF);
 
@@ -947,10 +945,8 @@ ena_alloc_rx_mbuf(struct ena_adapter *adapter,
if (rx_info->mbuf != NULL)
return (0);
 
-   ENA_RING_MTX_LOCK(rx_ring);
/* Get mbuf using UMA allocator */
rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES);
-   ENA_RING_MTX_UNLOCK(rx_ring);
 
if (!rx_info->mbuf) {
counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1);
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svn commit: r320629 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:04:31 2017
New Revision: 320629
URL: https://svnweb.freebsd.org/changeset/base/320629

Log:
  Call drbr_advance() before leaving TX routine
  
  If drbr_advance() is not called before doing cleanup and packet is
  already enqueued for sending (tx_info is holding pointer to mbuf), then
  mbuf is cleaned both in drbr_flush() and in cleanup routine, when all
  mbufs hold by tx_buffer_info are being released.
  
  This causes panic, because mbuf is released twice.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue Jul  4 00:02:28 2017(r320628)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:04:31 2017(r320629)
@@ -2805,10 +2805,11 @@ ena_start_xmit(struct ena_ring *tx_ring)
break;
}
 
+   drbr_advance(adapter->ifp, tx_ring->br);
+
if ((adapter->ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
return;
 
-   drbr_advance(adapter->ifp, tx_ring->br);
acum_pkts++;
 
BPF_MTAP(adapter->ifp, mbuf);
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svn commit: r320628 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:02:28 2017
New Revision: 320628
URL: https://svnweb.freebsd.org/changeset/base/320628

Log:
  Unmask all IO irqs after driver state is set as running
  
  If driver left MSI-x handlling routine because interface was put down,
  it is not unmasking IRQs, so any requesting interrupt will be awaiting
  for unmasking.
  
  On ena_up() routine all interrupts are being unmasked and any awaiting
  interrupt will be handled right away.
  
  If handler was executed before driver state was set as running, handling
  routine is being ended immediately, leaving IO irqs for given queue
  masked.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue Jul  4 00:02:06 2017(r320627)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:02:28 2017(r320628)
@@ -2097,7 +2097,6 @@ ena_up_complete(struct ena_adapter *adapter)
 
ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu);
ena_refill_all_rx_bufs(adapter);
-   ena_unmask_all_io_irqs(adapter);
 
return (0);
 }
@@ -2170,6 +2169,8 @@ ena_up(struct ena_adapter *adapter)
taskqueue_enqueue(adapter->stats_tq, >stats_task);
 
adapter->up = true;
+
+   ena_unmask_all_io_irqs(adapter);
}
 
return (0);
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svn commit: r320626 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue Jul  4 00:00:42 2017
New Revision: 320626
URL: https://svnweb.freebsd.org/changeset/base/320626

Log:
  Acquire locks before calling drbr_flush()
  
  It is required to hold lock that is associated with buffer ring before
  flushing drbr.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Mon Jul  3 23:59:11 2017(r320625)
+++ head/sys/dev/ena/ena.c  Tue Jul  4 00:00:42 2017(r320626)
@@ -642,7 +642,9 @@ ena_setup_tx_resources(struct ena_adapter *adapter, in
tx_ring->next_to_clean = 0;
 
/* Make sure that drbr is empty */
+   ENA_RING_MTX_LOCK(tx_ring);
drbr_flush(adapter->ifp, tx_ring->br);
+   ENA_RING_MTX_UNLOCK(tx_ring);
 
/* ... and create the buffer DMA maps */
for (i = 0; i < tx_ring->ring_size; i++) {
@@ -709,11 +711,11 @@ ena_free_tx_resources(struct ena_adapter *adapter, int
 
taskqueue_free(tx_ring->enqueue_tq);
 
+   ENA_RING_MTX_LOCK(tx_ring);
/* Flush buffer ring, */
drbr_flush(adapter->ifp, tx_ring->br);
 
/* Free buffer DMA maps, */
-   ENA_RING_MTX_LOCK(tx_ring);
for (int i = 0; i < tx_ring->ring_size; i++) {
m_freem(tx_ring->tx_buffer_info[i].mbuf);
tx_ring->tx_buffer_info[i].mbuf = NULL;
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svn commit: r320625 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Mon Jul  3 23:59:11 2017
New Revision: 320625
URL: https://svnweb.freebsd.org/changeset/base/320625

Log:
  Add missing lock upon initialization of the interface
  
  Lack of this lock was causing crash if down was called in
  parallel with the initialization routine.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Mon Jul  3 23:54:39 2017(r320624)
+++ head/sys/dev/ena/ena.c  Mon Jul  3 23:59:11 2017(r320625)
@@ -2276,8 +2276,11 @@ ena_init(void *arg)
 {
struct ena_adapter *adapter = (struct ena_adapter *)arg;
 
-   if (adapter->up == false)
+   if (adapter->up == false) {
+   sx_xlock(>ioctl_sx);
ena_up(adapter);
+   sx_unlock(>ioctl_sx);
+   }
 
return;
 }
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svn commit: r320200 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Wed Jun 21 18:28:37 2017
New Revision: 320200
URL: https://svnweb.freebsd.org/changeset/base/320200

Log:
  Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms
  
  This patch disables outer cache sync in PL310 driver
  by adding "arm,io-coherent" property. In addition to
  the previous patches it was the last bit needed
  for enabling proper operation of Armada 38x SoCs
  with the IO cache coherency.
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: mmel
  Differential revision: https://reviews.freebsd.org/D11204

Modified:
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Wed Jun 21 18:27:05 2017
(r320199)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Wed Jun 21 18:28:37 2017
(r320200)
@@ -177,6 +177,7 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
+   arm,io-coherent;
};
 
scu@c000 {
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svn commit: r320199 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed Jun 21 18:27:05 2017
New Revision: 320199
URL: https://svnweb.freebsd.org/changeset/base/320199

Log:
  Create root DMA tag and fix MBUS windows on DMA coherent platforms
  
  Armada 38x SoCs, in order to work properly in IO-coherent mode,
  requires an update of the MBUS windows attributesd.
  
  This patch also configures nexus coherent dma tag, because all
  busses and children devices have to inherit this setting in runtime.
  The latter has to be executed as a sysinit (SI_SUB_DRIVERS type),
  so that bus_dma_tag_create() can be executed properly.
  
  Submitted by: Michal Mazur 
  Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: ian
  Differential revision: https://reviews.freebsd.org/D11203

Modified:
  head/sys/arm/mv/mv_common.c
  head/sys/arm/mv/mv_machdep.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Wed Jun 21 18:25:35 2017(r320198)
+++ head/sys/arm/mv/mv_common.c Wed Jun 21 18:27:05 2017(r320199)
@@ -128,6 +128,7 @@ static uint32_t dev_mask = 0;
 static int cpu_wins_no = 0;
 static int eth_port = 0;
 static int usb_port = 0;
+static boolean_t platform_io_coherent = false;
 
 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
 
@@ -1064,7 +1065,7 @@ ddr_size(int i)
 uint32_t
 ddr_attr(int i)
 {
-   uint32_t dev, rev;
+   uint32_t dev, rev, attr;
 
soc_id(, );
if (dev == MV_DEV_88RC8180)
@@ -1072,10 +1073,14 @@ ddr_attr(int i)
if (dev == MV_DEV_88F6781)
return (0);
 
-   return (i == 0 ? 0xe :
+   attr = (i == 0 ? 0xe :
(i == 1 ? 0xd :
(i == 2 ? 0xb :
(i == 3 ? 0x7 : 0xff;
+   if (platform_io_coherent)
+   attr |= 0x10;
+
+   return (attr);
 }
 
 uint32_t
@@ -2478,6 +2483,10 @@ fdt_win_setup(void)
node = OF_finddevice("/");
if (node == -1)
panic("fdt_win_setup: no root node");
+
+   /* Allow for coherent transactions on the A38x MBUS */
+   if (ofw_bus_node_is_compatible(node, "marvell,armada380"))
+   platform_io_coherent = true;
 
/*
 * Traverse through all children of root and simple-bus nodes.

Modified: head/sys/arm/mv/mv_machdep.c
==
--- head/sys/arm/mv/mv_machdep.cWed Jun 21 18:25:35 2017
(r320198)
+++ head/sys/arm/mv/mv_machdep.cWed Jun 21 18:27:05 2017
(r320199)
@@ -46,10 +46,13 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -86,6 +89,39 @@ int armada38x_mbus_optimization(void);
 #define MPP_PINS_PER_REG   8
 #define MPP_SEL(pin,func)  (((func) & 0xf) <<  \
 (((pin) % MPP_PINS_PER_REG) * 4))
+
+static void
+mv_busdma_tag_init(void *arg __unused)
+{
+   phandle_t node;
+   bus_dma_tag_t dmat;
+
+   /*
+* If this platform has coherent DMA, create the parent DMA tag to pass
+* down the coherent flag to all busses and devices on the platform,
+* otherwise return without doing anything. By default create tag
+* for all A38x-based platforms only.
+*/
+   if ((node = OF_finddevice("/")) == -1)
+   return;
+   if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0)
+   return;
+
+   bus_dma_tag_create(NULL,/* No parent tag */
+   1, 0,   /* alignment, bounds */
+   BUS_SPACE_MAXADDR,  /* lowaddr */
+   BUS_SPACE_MAXADDR,  /* highaddr */
+   NULL, NULL, /* filter, filterarg */
+   BUS_SPACE_MAXSIZE,  /* maxsize */
+   BUS_SPACE_UNRESTRICTED, /* nsegments */
+   BUS_SPACE_MAXSIZE,  /* maxsegsize */
+   BUS_DMA_COHERENT,   /* flags */
+   NULL, NULL, /* lockfunc, lockarg */
+   );
+
+   nexus_set_dma_tag(dmat);
+}
+SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL);
 
 static int
 platform_mpp_init(void)
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svn commit: r320198 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Wed Jun 21 18:25:35 2017
New Revision: 320198
URL: https://svnweb.freebsd.org/changeset/base/320198

Log:
  Enable setting the dma tag at the nexus level
  
  Allow to set the dma tag for nexus in the platform init code,
  so that all busses and devices would be able to inherit it.
  This change is useful e.g. for setting coherent dma tag for
  the platforms with hardware IO cache coherency.
  
  Submitted by: ian
  Michal Mazur 
  Reviewed by: ian
  Differential revision: https://reviews.freebsd.org/D11202

Added:
  head/sys/arm/arm/nexusvar.h   (contents, props changed)
Modified:
  head/sys/arm/arm/nexus.c

Modified: head/sys/arm/arm/nexus.c
==
--- head/sys/arm/arm/nexus.cWed Jun 21 18:23:28 2017(r320197)
+++ head/sys/arm/arm/nexus.cWed Jun 21 18:25:35 2017(r320198)
@@ -62,6 +62,8 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 
+#include 
+
 #ifdef FDT
 #include 
 #include 
@@ -87,6 +89,7 @@ staticstruct resource *nexus_alloc_resource(device_t,
 static int nexus_activate_resource(device_t, device_t, int, int,
 struct resource *);
 static bus_space_tag_t nexus_get_bus_tag(device_t, device_t);
+static bus_dma_tag_t nexus_get_dma_tag(device_t dev, device_t child);
 #ifdef INTRNG
 #ifdef SMP
 static int nexus_bind_intr(device_t, device_t, struct resource *, int);
@@ -112,6 +115,13 @@ static int nexus_ofw_map_intr(device_t dev, device_t c
 int icells, pcell_t *intr);
 #endif
 
+/*
+ * Normally NULL (which results in defaults which are handled in
+ * busdma_machdep), platform init code can use nexus_set_dma_tag() to set this
+ * to a tag that will be inherited by all busses and devices on the platform.
+ */
+static bus_dma_tag_t nexus_dma_tag;
+
 static device_method_t nexus_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, nexus_probe),
@@ -127,6 +137,7 @@ static device_method_t nexus_methods[] = {
DEVMETHOD(bus_setup_intr,   nexus_setup_intr),
DEVMETHOD(bus_teardown_intr,nexus_teardown_intr),
DEVMETHOD(bus_get_bus_tag,  nexus_get_bus_tag),
+   DEVMETHOD(bus_get_dma_tag,  nexus_get_dma_tag),
 #ifdef INTRNG
DEVMETHOD(bus_describe_intr,nexus_describe_intr),
 #ifdef SMP
@@ -273,6 +284,20 @@ nexus_get_bus_tag(device_t bus __unused, device_t chil
 #else
return((void *)1);
 #endif
+}
+
+static bus_dma_tag_t
+nexus_get_dma_tag(device_t dev, device_t child)
+{
+
+   return nexus_dma_tag;
+}
+
+void
+nexus_set_dma_tag(bus_dma_tag_t tag)
+{
+
+   nexus_dma_tag = tag;
 }
 
 static int

Added: head/sys/arm/arm/nexusvar.h
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/arm/arm/nexusvar.h Wed Jun 21 18:25:35 2017(r320198)
@@ -0,0 +1,36 @@
+/*-
+ * Copyright (c) 2017 Ian Lepore 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef_ARM_ARM_NEXUSVAR_H_
+#define_ARM_ARM_NEXUSVAR_H_
+
+/* Set a platform busdma tag to be inherited by all busses and devices. */
+void nexus_set_dma_tag(bus_dma_tag_t _tag);
+
+#endif
+
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svn commit: r320197 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Wed Jun 21 18:23:28 2017
New Revision: 320197
URL: https://svnweb.freebsd.org/changeset/base/320197

Log:
  Introduce support for DMA coherent ARM platforms
  
  - Inherit BUS_DMA_COHERENT flag from parent buses
  - Use cacheable memory attributes on dma coherent platform
  - Disable cache synchronization on coherent platform
  
  Changes are based on ARMv8 busdma code and commit r299683.
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: ian
  Differential revision: https://reviews.freebsd.org/D11201

Modified:
  head/sys/arm/arm/busdma_machdep-v6.c

Modified: head/sys/arm/arm/busdma_machdep-v6.c
==
--- head/sys/arm/arm/busdma_machdep-v6.cWed Jun 21 18:20:17 2017
(r320196)
+++ head/sys/arm/arm/busdma_machdep-v6.cWed Jun 21 18:23:28 2017
(r320197)
@@ -491,6 +491,7 @@ bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t al
newtag->highaddr = MAX(parent->highaddr, newtag->highaddr);
newtag->alignment = MAX(parent->alignment, newtag->alignment);
newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE;
+   newtag->flags |= parent->flags & BUS_DMA_COHERENT;
if (newtag->boundary == 0)
newtag->boundary = parent->boundary;
else if (parent->boundary != 0)
@@ -755,11 +756,19 @@ bus_dmamem_alloc(bus_dma_tag_t dmat, void **vaddr, int
}
map->flags = DMAMAP_DMAMEM_ALLOC;
 
-   /* Choose a busdma buffer allocator based on memory type flags. */
-   if (flags & BUS_DMA_COHERENT) {
+   /* For coherent memory, set the map flag that disables sync ops. */
+   if (flags & BUS_DMA_COHERENT)
+   map->flags |= DMAMAP_COHERENT;
+
+   /*
+* Choose a busdma buffer allocator based on memory type flags.
+* If the tag's COHERENT flag is set, that means normal memory
+* is already coherent, use the normal allocator.
+*/
+   if ((flags & BUS_DMA_COHERENT) &&
+   ((dmat->flags & BUS_DMA_COHERENT) == 0)) {
memattr = VM_MEMATTR_UNCACHEABLE;
ba = coherent_allocator;
-   map->flags |= DMAMAP_COHERENT;
} else {
memattr = VM_MEMATTR_DEFAULT;
ba = standard_allocator;
@@ -829,7 +838,8 @@ bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_d
struct busdma_bufzone *bufzone;
busdma_bufalloc_t ba;
 
-   if (map->flags & DMAMAP_COHERENT)
+   if ((map->flags & DMAMAP_COHERENT) &&
+   ((dmat->flags & BUS_DMA_COHERENT) == 0))
ba = coherent_allocator;
else
ba = standard_allocator;
@@ -1030,7 +1040,7 @@ _bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t
sgsize = MIN(sgsize, PAGE_SIZE - (curaddr & PAGE_MASK));
curaddr = add_bounce_page(dmat, map, 0, curaddr,
sgsize);
-   } else {
+   } else if ((dmat->flags & BUS_DMA_COHERENT) == 0) {
if (map->sync_count > 0)
sl_end = sl->paddr + sl->datacount;
 
@@ -1144,7 +1154,7 @@ _bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap
sgsize)) {
curaddr = add_bounce_page(dmat, map, kvaddr, curaddr,
sgsize);
-   } else {
+   } else if ((dmat->flags & BUS_DMA_COHERENT) == 0) {
if (map->sync_count > 0) {
sl_pend = sl->paddr + sl->datacount;
sl_vend = sl->vaddr + sl->datacount;
@@ -1353,8 +1363,9 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
bpage->datacount);
if (tempvaddr != 0)
pmap_quick_remove_page(tempvaddr);
-   dcache_wb_poc(bpage->vaddr, bpage->busaddr,
-   bpage->datacount);
+   if ((dmat->flags & BUS_DMA_COHERENT) == 0)
+   dcache_wb_poc(bpage->vaddr,
+   bpage->busaddr, bpage->datacount);
bpage = STAILQ_NEXT(bpage, links);
}
dmat->bounce_zone->total_bounced++;
@@ -1374,8 +1385,9 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) 
{
bpage = STAILQ_FIRST(>bpages);
while (bpage != NULL) {
-   dcache_inv_poc_dma(bpage->vaddr, bpage->busaddr,
-   bpage->datacount);
+

svn commit: r320142 - in head/sys/arm: arm include

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 20 11:11:42 2017
New Revision: 320142
URL: https://svnweb.freebsd.org/changeset/base/320142

Log:
  Disable PL310 outer cache sync for IO coherent platforms
  
  When a PL310 cache is used on a system that provides hardware
  coherency, the outer cache sync operation is useless, and can be
  skipped. Moreover, on some systems, it is harmful as it causes
  deadlocks between the Marvell coherency mechanism, the Marvell PCIe
  or Crypto controllers and the Cortex-A9.
  
  To avoid this, this commit introduces a new Device Tree property
  'arm,io-coherent' for the L2 cache controller node, valid only for the
  PL310 cache. It identifies the usage of the PL310 cache in an I/O
  coherent configuration. Internally, it makes the driver disable the
  outer cache sync operation.
  
  Note, that other outer-cache operations are not removed, as they may
  be needed for certain situations, such as booting secondary CPUs.
  Moreover, in order to enable IO coherent operation, the decision
  whether to use L2 cache maintenance callbacks is done in busdma
  layer, which was enabled in one of the previous commits.
  
  Submitted by: Michal Mazur 
  Marcin Wojtas 
  Reviewed by: mmel
  Obtained from: Semihalf
  Differential revision: https://reviews.freebsd.org/D11245

Modified:
  head/sys/arm/arm/pl310.c
  head/sys/arm/include/pl310.h

Modified: head/sys/arm/arm/pl310.c
==
--- head/sys/arm/arm/pl310.cTue Jun 20 11:09:38 2017(r320141)
+++ head/sys/arm/arm/pl310.cTue Jun 20 11:11:42 2017(r320142)
@@ -206,6 +206,10 @@ pl310_cache_sync(void)
if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
return;
 
+   /* Do not sync outer cache on IO coherent platform */
+   if (pl310_softc->sc_io_coherent)
+   return;
+
 #ifdef PL310_ERRATA_753970
if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0)
/* Write uncached PL310 register */
@@ -444,6 +448,7 @@ pl310_attach(device_t dev)
struct pl310_softc *sc = device_get_softc(dev);
int rid;
uint32_t cache_id, debug_ctrl;
+   phandle_t node;
 
sc->sc_dev = dev;
rid = 0;
@@ -469,6 +474,15 @@ pl310_attach(device_t dev)
device_printf(dev, "Part number: 0x%x, release: 0x%x\n",
(cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK,
(cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK);
+
+   /*
+* Test for "arm,io-coherent" property and disable sync operation if
+* platform is I/O coherent. Outer sync operations are not needed
+* on coherent platform and may be harmful in certain situations.
+*/
+   node = ofw_bus_get_node(dev);
+   if (OF_hasprop(node, "arm,io-coherent"))
+   sc->sc_io_coherent = true;
 
/*
 * If L2 cache is already enabled then something has violated the rules,

Modified: head/sys/arm/include/pl310.h
==
--- head/sys/arm/include/pl310.hTue Jun 20 11:09:38 2017
(r320141)
+++ head/sys/arm/include/pl310.hTue Jun 20 11:11:42 2017
(r320142)
@@ -148,6 +148,7 @@ struct pl310_softc {
struct mtx  sc_mtx;
u_int   sc_rtl_revision;
struct intr_config_hook *sc_ich;
+   boolean_t   sc_io_coherent;
 };
 
 /**
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svn commit: r320141 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 20 11:09:38 2017
New Revision: 320141
URL: https://svnweb.freebsd.org/changeset/base/320141

Log:
  Implement workaround for Armada 38X family HW issue between CPU and devices
  
  There is a hardware problem between Cortex-A9 CPUs and on-chip devices
  in Armada 38X SoCs that may cause hang on heavy load. This can be
  however worked around by mapping all registers and PCI IO
  as strongly ordered instead of device memory.
  
  Submitted by: Zbigniew Bodek <z...@semihalf.com>
  Reviewed by: mmel
  Tested by: mw_semihalf.com
  Obtained from: Semihalf
  Differential revision: https://reviews.freebsd.org/D10218

Modified:
  head/sys/arm/mv/mv_machdep.c

Modified: head/sys/arm/mv/mv_machdep.c
==
--- head/sys/arm/mv/mv_machdep.cTue Jun 20 08:44:03 2017
(r320140)
+++ head/sys/arm/mv/mv_machdep.cTue Jun 20 11:09:38 2017
(r320141)
@@ -59,6 +59,7 @@ __FBSDID("$FreeBSD$");
 #include 
 #else
 #include 
+#include 
 #endif
 
 #include   /* XXX */
@@ -257,6 +258,15 @@ platform_late_init(void)
 #endif
 
 #if defined(SOC_MV_ARMADA38X)
+   /*
+* Workaround for Marvell Armada38X family HW issue
+* between Cortex-A9 CPUs and on-chip devices that may
+* cause hang on heavy load.
+* To avoid that, map all registers including PCIe IO
+* as strongly ordered instead of device memory.
+*/
+   pmap_remap_vm_attr(PTE2_ATTR_DEVICE, PTE2_ATTR_SO);
+
/* Set IO Sync Barrier bit for all Mbus devices */
if (armada38x_win_set_iosync_barrier() != 0)
printf("WARNING: could not map CPU Subsystem registers\n");
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svn commit: r320006 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun 16 17:31:56 2017
New Revision: 320006
URL: https://svnweb.freebsd.org/changeset/base/320006

Log:
  Revert change to description introduced in r320002
  
  Currently some ARM platforms implement their own platform_probe_and_attach()
  function and other use common routine that calls platform's PLATFORM_ATTACH
  method.
  Keep the old description to match the preferred way of naming things.
  
  Pointed out by: andrew

Modified:
  head/sys/arm/arm/pmap-v6.c

Modified: head/sys/arm/arm/pmap-v6.c
==
--- head/sys/arm/arm/pmap-v6.c  Fri Jun 16 17:18:29 2017(r320005)
+++ head/sys/arm/arm/pmap-v6.c  Fri Jun 16 17:31:56 2017(r320006)
@@ -508,7 +508,7 @@ pmap_set_tex(void)
  * Usage rules:
  * - it shall be called after pmap_bootstrap_prepare() and before
  *   cpu_mp_start() (thus only on boot CPU). In practice, it's expected
- *   to be called from platform_probe_and_attach() or platform_late_init().
+ *   to be called from platform_attach() or platform_late_init().
  *
  * - if remapping doesn't change caching mode, or until uncached class
  *   is remapped to any kind of cached one, then no other restriction exists.
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svn commit: r320005 - in head/sys/arm/mv: . armada38x armadaxp discovery kirkwood orion

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun 16 17:18:29 2017
New Revision: 320005
URL: https://svnweb.freebsd.org/changeset/base/320005

Log:
  Enhance Armada 38x SoC identification string
  
  Add hw_clockrate and CPU frequency, basing on sample-at-reset
  configuration.
  
  Submitted by: Arnaud Ysmal 
Marcin Wojtas 
  Obtained from: Stormshield, Semihalf
  Sponsored by: Stormshield
  Reviewed by: andrew
  Differential revision: https://reviews.freebsd.org/D10899

Modified:
  head/sys/arm/mv/armada38x/armada38x.c
  head/sys/arm/mv/armadaxp/armadaxp.c
  head/sys/arm/mv/discovery/discovery.c
  head/sys/arm/mv/kirkwood/kirkwood.c
  head/sys/arm/mv/mv_common.c
  head/sys/arm/mv/mvreg.h
  head/sys/arm/mv/mvvar.h
  head/sys/arm/mv/orion/orion.c

Modified: head/sys/arm/mv/armada38x/armada38x.c
==
--- head/sys/arm/mv/armada38x/armada38x.c   Fri Jun 16 15:09:43 2017
(r320004)
+++ head/sys/arm/mv/armada38x/armada38x.c   Fri Jun 16 17:18:29 2017
(r320005)
@@ -29,6 +29,7 @@
 __FBSDID("$FreeBSD$");
 
 #include 
+#include 
 #include 
 #include 
 
@@ -43,6 +44,10 @@ int armada38x_scu_enable(void);
 int armada38x_win_set_iosync_barrier(void);
 int armada38x_mbus_optimization(void);
 
+static int hw_clockrate;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
+_clockrate, 0, "CPU instruction clock rate");
+
 uint32_t
 get_tclk(void)
 {
@@ -58,6 +63,29 @@ get_tclk(void)
return (TCLK_250MHZ);
else
return (TCLK_200MHZ);
+}
+
+uint32_t
+get_cpu_freq(void)
+{
+   uint32_t sar;
+
+   static const uint32_t cpu_frequencies[] = {
+   0, 0, 0, 0,
+   1066, 0, 0, 0,
+   1332, 0, 0, 0,
+   1600, 0, 0, 0,
+   1866, 0, 0, 2000
+   };
+
+   sar = (uint32_t)get_sar_value();
+   sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
+   if (sar >= nitems(cpu_frequencies))
+   return (0);
+
+   hw_clockrate = cpu_frequencies[sar];
+
+   return (hw_clockrate * 1000 * 1000);
 }
 
 int

Modified: head/sys/arm/mv/armadaxp/armadaxp.c
==
--- head/sys/arm/mv/armadaxp/armadaxp.c Fri Jun 16 15:09:43 2017
(r320004)
+++ head/sys/arm/mv/armadaxp/armadaxp.c Fri Jun 16 17:18:29 2017
(r320005)
@@ -136,6 +136,13 @@ get_tclk(void)
return (TCLK_200MHZ);
 }
 
+uint32_t
+get_cpu_freq(void)
+{
+
+   return (0);
+}
+
 static uint32_t
 count_l2clk(void)
 {

Modified: head/sys/arm/mv/discovery/discovery.c
==
--- head/sys/arm/mv/discovery/discovery.c   Fri Jun 16 15:09:43 2017
(r320004)
+++ head/sys/arm/mv/discovery/discovery.c   Fri Jun 16 17:18:29 2017
(r320005)
@@ -109,3 +109,10 @@ get_tclk(void)
panic("Unknown TCLK settings!");
}
 }
+
+uint32_t
+get_cpu_freq(void)
+{
+
+   return (0);
+}

Modified: head/sys/arm/mv/kirkwood/kirkwood.c
==
--- head/sys/arm/mv/kirkwood/kirkwood.c Fri Jun 16 15:09:43 2017
(r320004)
+++ head/sys/arm/mv/kirkwood/kirkwood.c Fri Jun 16 17:18:29 2017
(r320005)
@@ -79,3 +79,10 @@ get_tclk(void)
 
return (TCLK_166MHZ);
 }
+
+uint32_t
+get_cpu_freq(void)
+{
+
+   return (0);
+}

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Fri Jun 16 15:09:43 2017(r320004)
+++ head/sys/arm/mv/mv_common.c Fri Jun 16 17:18:29 2017(r320005)
@@ -419,7 +419,7 @@ soc_id(uint32_t *dev, uint32_t *rev)
 static void
 soc_identify(void)
 {
-   uint32_t d, r, size, mode;
+   uint32_t d, r, size, mode, freq;
const char *dev;
const char *rev;
 
@@ -512,7 +512,11 @@ soc_identify(void)
printf("%s", dev);
if (*rev != '\0')
printf(" rev %s", rev);
-   printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
+   printf(", TClock %dMHz", get_tclk() / 1000 / 1000);
+   freq = get_cpu_freq();
+   if (freq != 0)
+   printf(", Frequency %dMHz", freq / 1000 / 1000);
+   printf("\n");
 
mode = read_cpu_ctrl(CPU_CONFIG);
printf("  Instruction cache prefetch %s, data cache prefetch %s\n",

Modified: head/sys/arm/mv/mvreg.h
==
--- head/sys/arm/mv/mvreg.h Fri Jun 16 15:09:43 2017(r320004)
+++ head/sys/arm/mv/mvreg.h Fri Jun 16 17:18:29 2017(r320005)
@@ -355,6 +355,9 @@
 #define TCLK_300MHZ3
 #define TCLK_667MHZ66700
 
+#defineA38X_CPU_DDR_CLK_MASK   0x7c00
+#define

svn commit: r320002 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun 16 13:53:02 2017
New Revision: 320002
URL: https://svnweb.freebsd.org/changeset/base/320002

Log:
  Minor style improvements to pmap_remap_vm_attr()
  
  Use correct platform_ function name in the comment and remove
  redundant tabs.

Modified:
  head/sys/arm/arm/pmap-v6.c

Modified: head/sys/arm/arm/pmap-v6.c
==
--- head/sys/arm/arm/pmap-v6.c  Fri Jun 16 10:16:24 2017(r320001)
+++ head/sys/arm/arm/pmap-v6.c  Fri Jun 16 13:53:02 2017(r320002)
@@ -508,7 +508,7 @@ pmap_set_tex(void)
  * Usage rules:
  * - it shall be called after pmap_bootstrap_prepare() and before
  *   cpu_mp_start() (thus only on boot CPU). In practice, it's expected
- *   to be called from platform_attach() or platform_late_init().
+ *   to be called from platform_probe_and_attach() or platform_late_init().
  *
  * - if remapping doesn't change caching mode, or until uncached class
  *   is remapped to any kind of cached one, then no other restriction exists.
@@ -523,11 +523,11 @@ void
 pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
 {
int old_idx, new_idx;
-   
+
/* Map VM memattrs to indexes to tex_class table. */
old_idx = pte2_attr_tab[(int)old_attr];
new_idx = pte2_attr_tab[(int)new_attr];
-   
+
/* Replace TEX attribute and apply it. */
tex_class[old_idx] = tex_class[new_idx];
pmap_set_tex();
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svn commit: r320001 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun 16 10:16:24 2017
New Revision: 320001
URL: https://svnweb.freebsd.org/changeset/base/320001

Log:
  Fix typo in "Marvell" string
  
  Change Marwell to Marvell
  
  Pointed out by: Ravi Pokala 

Modified:
  head/sys/arm/arm/identcpu-v6.c

Modified: head/sys/arm/arm/identcpu-v6.c
==
--- head/sys/arm/arm/identcpu-v6.c  Fri Jun 16 06:34:26 2017
(r32)
+++ head/sys/arm/arm/identcpu-v6.c  Fri Jun 16 10:16:24 2017
(r320001)
@@ -94,9 +94,9 @@ static struct {
{CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
CPU_CLASS_CORTEXA},
 
-   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7",
+   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7",
CPU_CLASS_MARVELL},
-   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7",
+   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7",
CPU_CLASS_MARVELL},
 
{CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
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svn commit: r319914 - in head/sys: arm/mv boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:55:21 2017
New Revision: 319914
URL: https://svnweb.freebsd.org/changeset/base/319914

Log:
  Enable HWPMC overflow IRQ on both CPUs in MPIC
  
  This commit enables usage of HWPMC interrupts for the
  Marvell SoCs, which use MPIC (Armada38x and ArmadaXP).
  Those interrupts require extra unmasking, comparing to
  others. Also, in order to process counters per-CPU,
  they are masked/unmasked using separate registers' sets
  for each core.
  
  Submitted by: Michal Mazur 
  Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10913

Modified:
  head/sys/arm/mv/mpic.c
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Modified: head/sys/arm/mv/mpic.c
==
--- head/sys/arm/mv/mpic.c  Tue Jun 13 18:53:56 2017(r319913)
+++ head/sys/arm/mv/mpic.c  Tue Jun 13 18:55:21 2017(r319914)
@@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -70,6 +71,7 @@ __FBSDID("$FreeBSD$");
 #define debugf(fmt, args...)
 #endif
 
+#defineMPIC_INT_LOCAL  3
 #defineMPIC_INT_ERR4
 #defineMPIC_INT_MSI96
 
@@ -93,7 +95,9 @@ __FBSDID("$FreeBSD$");
 #defineMPIC_IIACK  0x44
 #defineMPIC_ISM0x48
 #defineMPIC_ICM0x4c
-#defineMPIC_ERR_MASK   0xe50
+#defineMPIC_ERR_MASK   0x50
+#defineMPIC_LOCAL_MASK 0x54
+#defineMPIC_CPU(n) (n) * 0x100
 
 #defineMPIC_PPI32
 
@@ -223,6 +227,7 @@ mv_mpic_attach(device_t dev)
struct mv_mpic_softc *sc;
int error;
uint32_t val;
+   int cpu;
 
sc = (struct mv_mpic_softc *)device_get_softc(dev);
 
@@ -283,6 +288,12 @@ mv_mpic_attach(device_t dev)
 
mpic_unmask_msi();
 
+   /* Unmask CPU performance counters overflow irq */
+   for (cpu = 0; cpu < mp_ncpus; cpu++)
+   MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
+   (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
+   MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
+
return (0);
 }
 
@@ -488,6 +499,16 @@ static void
 mpic_unmask_irq(uintptr_t nb)
 {
 
+#ifdef SMP
+   int cpu;
+
+   if (nb == MPIC_INT_LOCAL) {
+   for (cpu = 0; cpu < mp_ncpus; cpu++)
+   MPIC_CPU_WRITE(mv_mpic_sc,
+   MPIC_CPU(cpu) + MPIC_ICM, nb);
+   return;
+   }
+#endif
if (mpic_irq_is_percpu(nb))
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
else if (nb < ERR_IRQ)
@@ -503,6 +524,16 @@ static void
 mpic_mask_irq(uintptr_t nb)
 {
 
+#ifdef SMP
+   int cpu;
+
+   if (nb == MPIC_INT_LOCAL) {
+   for (cpu = 0; cpu < mp_ncpus; cpu++)
+   MPIC_CPU_WRITE(mv_mpic_sc,
+   MPIC_CPU(cpu) + MPIC_ISM, nb);
+   return;
+   }
+#endif
if (mpic_irq_is_percpu(nb))
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
else if (nb < ERR_IRQ)

Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Tue Jun 13 18:53:56 2017
(r319913)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Tue Jun 13 18:55:21 2017
(r319914)
@@ -419,7 +419,7 @@
 
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
-   reg = <0x20a00 0x2d0>, <0x21870 0x58>;
+   reg = <0x20a00 0x2d0>, <0x21870 0x300>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
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svn commit: r319913 - head/sys/dev/hwpmc

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:53:56 2017
New Revision: 319913
URL: https://svnweb.freebsd.org/changeset/base/319913

Log:
  Fix INVARIANTS debug code in HWPMC
  
  When HWPMC stops sampling, ps_pmc may be freed before samples
  are processed. In such situation treat PMC as stopped.
  Add "ifdef" to fix build without INVARIANTS code.
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10912

Modified:
  head/sys/dev/hwpmc/hwpmc_mod.c

Modified: head/sys/dev/hwpmc/hwpmc_mod.c
==
--- head/sys/dev/hwpmc/hwpmc_mod.c  Tue Jun 13 18:52:39 2017
(r319912)
+++ head/sys/dev/hwpmc/hwpmc_mod.c  Tue Jun 13 18:53:56 2017
(r319913)
@@ -4224,7 +4224,8 @@ pmc_capture_user_callchain(int cpu, int ring, struct t
ps_end = psb->ps_write;
do {
 #ifdef INVARIANTS
-   if (ps->ps_pmc->pm_state != PMC_STATE_RUNNING)
+   if ((ps->ps_pmc == NULL) ||
+   (ps->ps_pmc->pm_state != PMC_STATE_RUNNING))
nfree++;
 #endif
if (ps->ps_nsamples != PMC_SAMPLE_INUSE)
@@ -4262,9 +4263,11 @@ next:
ps = psb->ps_samples;
} while (ps != ps_end);
 
+#ifdef INVARIANTS
KASSERT(ncallchains > 0 || nfree > 0,
("[pmc,%d] cpu %d didn't find a sample to collect", __LINE__,
cpu));
+#endif
 
KASSERT(td->td_pinned == 1,
("[pmc,%d] invalid td_pinned value", __LINE__));
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svn commit: r319912 - head/sys/dev/hwpmc

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:52:39 2017
New Revision: 319912
URL: https://svnweb.freebsd.org/changeset/base/319912

Log:
  Fix event table for Cortex A9.
  
  Removed events 0x8 (INSTR_EXECUTED), 0xE (PC_PROC_RETURN) and
  0x13-0x1d not supported on Cortex A9.
  Add events 0x68 and 0x6E which replaced 0x8 and 0xE.
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10911

Modified:
  head/sys/dev/hwpmc/pmc_events.h

Modified: head/sys/dev/hwpmc/pmc_events.h
==
--- head/sys/dev/hwpmc/pmc_events.h Tue Jun 13 18:51:23 2017
(r319911)
+++ head/sys/dev/hwpmc/pmc_events.h Tue Jun 13 18:52:39 2017
(r319912)
@@ -5624,7 +5624,7 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_8
 #definePMC_EV_ARMV7_FIRST  PMC_EV_ARMV7_EVENT_00H
 #definePMC_EV_ARMV7_LAST   PMC_EV_ARMV7_EVENT_FFH
 
-#define__PMC_EV_ALIAS_ARMV7_COMMON_A8()
\
+#define__PMC_EV_ALIAS_ARMV7_COMMON()   
\
__PMC_EV_ALIAS("PMNC_SW_INCR",  ARMV7_EVENT_00H)\
__PMC_EV_ALIAS("L1_ICACHE_REFILL",  ARMV7_EVENT_01H)\
__PMC_EV_ALIAS("ITLB_REFILL",   ARMV7_EVENT_02H)\
@@ -5633,20 +5633,20 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_8
__PMC_EV_ALIAS("DTLB_REFILL",   ARMV7_EVENT_05H)\
__PMC_EV_ALIAS("MEM_READ",  ARMV7_EVENT_06H)\
__PMC_EV_ALIAS("MEM_WRITE", ARMV7_EVENT_07H)\
-   __PMC_EV_ALIAS("INSTR_EXECUTED",ARMV7_EVENT_08H)\
__PMC_EV_ALIAS("EXC_TAKEN", ARMV7_EVENT_09H)\
__PMC_EV_ALIAS("EXC_EXECUTED",  ARMV7_EVENT_0AH)\
__PMC_EV_ALIAS("CID_WRITE", ARMV7_EVENT_0BH)\
__PMC_EV_ALIAS("PC_WRITE",  ARMV7_EVENT_0CH)\
__PMC_EV_ALIAS("PC_IMM_BRANCH", ARMV7_EVENT_0DH)\
-   __PMC_EV_ALIAS("PC_PROC_RETURN",ARMV7_EVENT_0EH)\
__PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS",  ARMV7_EVENT_0FH)\
__PMC_EV_ALIAS("PC_BRANCH_MIS_PRED",ARMV7_EVENT_10H)\
__PMC_EV_ALIAS("CLOCK_CYCLES",  ARMV7_EVENT_11H)\
__PMC_EV_ALIAS("PC_BRANCH_PRED",ARMV7_EVENT_12H)
 
-#define__PMC_EV_ALIAS_ARMV7_COMMON()   
\
-   __PMC_EV_ALIAS_ARMV7_COMMON_A8()\
+#define__PMC_EV_ALIAS_ARMV7_COMMON_A8()
\
+   __PMC_EV_ALIAS_ARMV7_COMMON()   \
+   __PMC_EV_ALIAS("INSTR_EXECUTED",ARMV7_EVENT_08H)\
+   __PMC_EV_ALIAS("PC_PROC_RETURN",ARMV7_EVENT_0EH)\
__PMC_EV_ALIAS("MEM_ACCESS",ARMV7_EVENT_13H)\
__PMC_EV_ALIAS("L1_ICACHE_ACCESS",  ARMV7_EVENT_14H)\
__PMC_EV_ALIAS("L1_DCACHE_WB",  ARMV7_EVENT_15H)\
@@ -5710,6 +5710,8 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_8
__PMC_EV_ALIAS("DATA_EVICTION", ARMV7_EVENT_65H)
\
__PMC_EV_ALIAS("ISSUE_DNOT_DISPATCH_ANY_INSTR", ARMV7_EVENT_66H)
\
__PMC_EV_ALIAS("ISSUE_IS_EMPTY",ARMV7_EVENT_67H)
\
+   __PMC_EV_ALIAS("INSTR_RENAMED", ARMV7_EVENT_68H)
\
+   __PMC_EV_ALIAS("PREDICTABLE_FUNCTION_RETURN",   ARMV7_EVENT_6EH)
\
__PMC_EV_ALIAS("MAIN_EXECUTION_UNIT_PIPE",  ARMV7_EVENT_70H)
\
__PMC_EV_ALIAS("SECOND_EXECUTION_UNIT_PIPE",ARMV7_EVENT_71H)
\
__PMC_EV_ALIAS("LOAD_STORE_PIPE",   ARMV7_EVENT_72H)
\
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svn commit: r319911 - in head/sys: dev/hwpmc sys

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:51:23 2017
New Revision: 319911
URL: https://svnweb.freebsd.org/changeset/base/319911

Log:
  Fix HWPMC interrupt handling in Counting Mode
  
  Additionally:
   - Fix support for Cycle Counter (evsel == 0xFF)
   - Stop and mask interrupts from all counters on init and finish
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10910

Modified:
  head/sys/dev/hwpmc/hwpmc_armv7.c
  head/sys/sys/pmc.h

Modified: head/sys/dev/hwpmc/hwpmc_armv7.c
==
--- head/sys/dev/hwpmc/hwpmc_armv7.cTue Jun 13 18:50:08 2017
(r319910)
+++ head/sys/dev/hwpmc/hwpmc_armv7.cTue Jun 13 18:51:23 2017
(r319911)
@@ -46,6 +46,8 @@ struct armv7_event_code_map {
uint8_t pe_code;
 };
 
+#definePMC_EV_CPU_CYCLES   0xFF
+
 /*
  * Per-processor information.
  */
@@ -171,10 +173,11 @@ armv7_read_pmc(int cpu, int ri, pmc_value_t *v)
 
pm  = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
 
-   if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
-   tmp = cp15_pmccntr_get();
+   if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
+   tmp = (uint32_t)cp15_pmccntr_get();
else
tmp = armv7_pmcn_read(ri);
+   tmp += 0x1llu * pm->pm_overflowcnt;
 
PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp);
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
@@ -202,7 +205,7 @@ armv7_write_pmc(int cpu, int ri, pmc_value_t v)

PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 
-   if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
+   if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
cp15_pmccntr_set(v);
else
armv7_pmcn_write(ri, v);
@@ -244,11 +247,16 @@ armv7_start_pmc(int cpu, int ri)
pm = phw->phw_pmc;
config = pm->pm_md.pm_armv7.pm_armv7_evsel;
 
+   pm->pm_overflowcnt = 0;
+
/*
 * Configure the event selection.
 */
-   cp15_pmselr_set(ri);
-   cp15_pmxevtyper_set(config);
+   if (config != PMC_EV_CPU_CYCLES) {
+   cp15_pmselr_set(ri);
+   cp15_pmxevtyper_set(config);
+   } else
+   ri = 31;
 
/*
 * Enable the PMC.
@@ -264,9 +272,13 @@ armv7_stop_pmc(int cpu, int ri)
 {
struct pmc_hw *phw;
struct pmc *pm;
+   uint32_t config;
 
phw= _pcpu[cpu]->pc_armv7pmcs[ri];
pm = phw->phw_pmc;
+   config = pm->pm_md.pm_armv7.pm_armv7_evsel;
+   if (config == PMC_EV_CPU_CYCLES)
+   ri = 31;
 
/*
 * Disable the PMCs.
@@ -313,11 +325,9 @@ armv7_intr(int cpu, struct trapframe *tf)
pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
if (pm == NULL)
continue;
-   if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
-   continue;
 
/* Check if counter has overflowed */
-   if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
+   if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
reg = (1 << 31);
else
reg = (1 << ri);
@@ -330,6 +340,11 @@ armv7_intr(int cpu, struct trapframe *tf)
cp15_pmovsr_set(reg);
 
retval = 1; /* Found an interrupting PMC. */
+
+   if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
+   pm->pm_overflowcnt += 1;
+   continue;
+   }
if (pm->pm_state != PMC_STATE_RUNNING)
continue;
 
@@ -430,6 +445,11 @@ armv7_pcpu_init(struct pmc_mdep *md, int cpu)
pc->pc_hwpmcs[i + first_ri] = phw;
}
 
+   pmnc = 0x;
+   cp15_pmcnten_clr(pmnc);
+   cp15_pminten_clr(pmnc);
+   cp15_pmovsr_set(pmnc);
+
/* Enable unit */
pmnc = cp15_pmcr_get();
pmnc |= ARMV7_PMNC_ENABLE;
@@ -446,6 +466,11 @@ armv7_pcpu_fini(struct pmc_mdep *md, int cpu)
pmnc = cp15_pmcr_get();
pmnc &= ~ARMV7_PMNC_ENABLE;
cp15_pmcr_set(pmnc);
+
+   pmnc = 0x;
+   cp15_pmcnten_clr(pmnc);
+   cp15_pminten_clr(pmnc);
+   cp15_pmovsr_set(pmnc);
 
return 0;
 }

Modified: head/sys/sys/pmc.h
==
--- head/sys/sys/pmc.h  Tue Jun 13 18:50:08 2017(r319910)
+++ head/sys/sys/pmc.h  Tue Jun 13 18:51:23 2017(r319911)
@@ -741,6 +741,7 @@ struct pmc {
struct pmc_owner *pm_owner; /* owner thread state */
int pm_runcount;/* #cpus currently on */
enum pmc_state  pm_state;   /* current PMC state */
+   uint32_t

svn commit: r319910 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:50:08 2017
New Revision: 319910
URL: https://svnweb.freebsd.org/changeset/base/319910

Log:
  Add detection of CPU class for ARMv6/v7
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: andrew
  Differential revision: https://reviews.freebsd.org/D10909

Modified:
  head/sys/arm/arm/identcpu-v6.c

Modified: head/sys/arm/arm/identcpu-v6.c
==
--- head/sys/arm/arm/identcpu-v6.c  Tue Jun 13 18:48:51 2017
(r319909)
+++ head/sys/arm/arm/identcpu-v6.c  Tue Jun 13 18:50:08 2017
(r319910)
@@ -60,29 +60,47 @@ static char hw_buf[81];
 static int hw_buf_idx;
 static bool hw_buf_newline;
 
+enum cpu_class cpu_class = CPU_CLASS_NONE;
+
 static struct {
int implementer;
int part_number;
char*impl_name;
char*core_name;
+   enumcpu_class cpu_class;
 } cpu_names[] =  {
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176,"ARM", "ARM1176"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"},
-   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176,"ARM", "ARM1176",
+   CPU_CLASS_ARM11J},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72",
+   CPU_CLASS_CORTEXA},
+   {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
+   CPU_CLASS_CORTEXA},
 
-   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"},
-   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"},
+   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7",
+   CPU_CLASS_MARVELL},
+   {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7",
+   CPU_CLASS_MARVELL},
 
-   {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"},
+   {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
+   CPU_CLASS_KRAIT},
 };
 
 
@@ -266,6 +284,7 @@ identify_arm_cpu(void)
for(i = 0; i < nitems(cpu_names); i++) {
if (cpu_names[i].implementer == cpuinfo.implementer &&
cpu_names[i].part_number == cpuinfo.part_number) {
+   cpu_class = cpu_names[i].cpu_class;
printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n",
cpu_names[i].impl_name, cpu_names[i].core_name,
cpuinfo.revision, cpuinfo.patch,
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svn commit: r319909 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:48:51 2017
New Revision: 319909
URL: https://svnweb.freebsd.org/changeset/base/319909

Log:
  Enable in-band link management on A388-Clearfog board
  
  This patch adds in-band link management over SGMII of the
  SFP transceiver on Armada-388-Clearfog board.
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Netgate
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10708

Modified:
  head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts

Modified: head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts
==
--- head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts   Tue Jun 13 18:47:42 
2017(r319908)
+++ head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts   Tue Jun 13 18:48:51 
2017(r319909)
@@ -97,11 +97,7 @@
bm,pool-long = <3>;
bm,pool-short = <1>;
status = "okay";
-
-   fixed-link {
-   speed = <1000>;
-   full-duplex;
-   };
+   managed = "in-band-status";
};
 
i2c@11000 {
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svn commit: r319908 - head/sys/arm/conf

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:47:42 2017
New Revision: 319908
URL: https://svnweb.freebsd.org/changeset/base/319908

Log:
  Enable neta controller support in ARMADA38X
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10707

Modified:
  head/sys/arm/conf/ARMADA38X

Modified: head/sys/arm/conf/ARMADA38X
==
--- head/sys/arm/conf/ARMADA38X Tue Jun 13 18:46:29 2017(r319907)
+++ head/sys/arm/conf/ARMADA38X Tue Jun 13 18:47:42 2017(r319908)
@@ -43,6 +43,7 @@ devicere
 device mdio
 device etherswitch
 device e6000sw
+device neta
 
 # PCI
 device pci
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svn commit: r319907 - in head/sys: arm/mv conf dev/neta

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:46:29 2017
New Revision: 319907
URL: https://svnweb.freebsd.org/changeset/base/319907

Log:
  Introduce Armada 38x/XP network controller support
  
  This patch contains a new driver for the network unit of Marvell
  Armada 38x/XP SoCs, called NETA. This support was thoroughly tested
  and optimised in terms of stability and performance. Additional
  hardware features, like Buffer Management (BM) or Parser and Classifier
  (PnC) will be progressively supported as needed.
  
  Submitted by: Fabien Thomas <fabien.tho...@stormshield.eu>
  Arnaud Ysmal <arnaud.ys...@stormshield.eu>
      Zbigniew Bodek <z...@semihalf.com>
  Michal Mazur <m...@semihalf.com>
  Bartosz Szczepanek <b...@semihalf.com>
  Marcin Wojtas <m...@semihalf.com>
  
  Obtained from:Semihalf
  Sponsored by: Stormshield (main development)
Netgate (cleanup and upstreaming)
  Differential revision: https://reviews.freebsd.org/D10706

Added:
  head/sys/dev/neta/
  head/sys/dev/neta/if_mvneta.c   (contents, props changed)
  head/sys/dev/neta/if_mvneta_fdt.c   (contents, props changed)
  head/sys/dev/neta/if_mvnetareg.h   (contents, props changed)
  head/sys/dev/neta/if_mvnetavar.h   (contents, props changed)
Modified:
  head/sys/arm/mv/files.mv
  head/sys/arm/mv/mv_common.c
  head/sys/arm/mv/mvwin.h
  head/sys/conf/options

Modified: head/sys/arm/mv/files.mv
==
--- head/sys/arm/mv/files.mvTue Jun 13 18:35:14 2017(r319906)
+++ head/sys/arm/mv/files.mvTue Jun 13 18:46:29 2017(r319907)
@@ -24,6 +24,8 @@ arm/mv/timer.coptional
!soc_mv_armada38x
 dev/cesa/cesa.coptionalcesa
 dev/iicbus/twsi/mv_twsi.c  optionaltwsi
 dev/mge/if_mge.c   optionalmge
+dev/neta/if_mvneta_fdt.c   optionalneta fdt
+dev/neta/if_mvneta.c   optionalneta mdio mii
 dev/nand/nfc_mv.c  optionalnand
 dev/mvs/mvs_soc.c  optionalmvs
 dev/uart/uart_dev_ns8250.c optionaluart

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Tue Jun 13 18:35:14 2017(r319906)
+++ head/sys/arm/mv/mv_common.c Tue Jun 13 18:46:29 2017(r319907)
@@ -96,6 +96,7 @@ static void decode_win_cesa_setup(u_long);
 static void decode_win_usb_setup(u_long);
 static void decode_win_usb3_setup(u_long);
 static void decode_win_eth_setup(u_long);
+static void decode_win_neta_setup(u_long);
 static void decode_win_sata_setup(u_long);
 static void decode_win_ahci_setup(u_long);
 static void decode_win_sdhci_setup(u_long);
@@ -107,6 +108,7 @@ static void decode_win_cesa_dump(u_long);
 static void decode_win_usb_dump(u_long);
 static void decode_win_usb3_dump(u_long);
 static void decode_win_eth_dump(u_long base);
+static void decode_win_neta_dump(u_long base);
 static void decode_win_idma_dump(u_long base);
 static void decode_win_xor_dump(u_long base);
 static void decode_win_ahci_dump(u_long base);
@@ -152,6 +154,7 @@ struct soc_node_spec {
 
 static struct soc_node_spec soc_nodes[] = {
{ "mrvl,ge", _win_eth_setup, _win_eth_dump },
+   { "marvell,armada-370-neta", _win_neta_setup, 
_win_neta_dump },
{ "mrvl,usb-ehci", _win_usb_setup, _win_usb_dump },
{ "marvell,orion-ehci", _win_usb_setup, _win_usb_dump },
{ "marvell,armada-380-xhci", _win_usb3_setup, 
_win_usb3_dump },
@@ -1431,6 +1434,20 @@ decode_win_eth_setup(u_long base)
break;
}
}
+}
+
+static void
+decode_win_neta_dump(u_long base)
+{
+
+   decode_win_eth_dump(base + MV_WIN_NETA_OFFSET);
+}
+
+static void
+decode_win_neta_setup(u_long base)
+{
+
+   decode_win_eth_setup(base + MV_WIN_NETA_OFFSET);
 }
 
 static int

Modified: head/sys/arm/mv/mvwin.h
==
--- head/sys/arm/mv/mvwin.h Tue Jun 13 18:35:14 2017(r319906)
+++ head/sys/arm/mv/mvwin.h Tue Jun 13 18:46:29 2017(r319907)
@@ -229,6 +229,9 @@
 #defineMV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
 #defineMV_WIN_USB3_MAX 8
 
+#defineMV_WIN_NETA_OFFSET  0x2000
+#defineMV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + 
MV_WIN_NETA_OFFSET
+
 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
 #define MV_WIN_ETH_REMAP(n)(0x4 * (n) + 0x280)
@@ -325,6 +328,7 @@
 /* IO Window Control Register fields */
 #defineIO_WIN_SIZE_SHIFT   16
 #defineIO_WIN_SIZE_MASK0x

svn commit: r319906 - head/sys/dev/etherswitch/e6000sw

[Zbigniew Bodek]

Author: zbb
Date: Tue Jun 13 18:35:14 2017
New Revision: 319906
URL: https://svnweb.freebsd.org/changeset/base/319906

Log:
  Prevent multiple lock initialization in e6000sw probe
  
  r319886 ("Add the initial support for the Marvell 88E6141
  and 88E6341 switches.") unveiled a problem with possible
  multiple lock creation. Move its initialization
  to the driver attach and for obtaining the switch ID
  create a temprorary one, which is immediately destroyed
  after the check.
  
  Submitted by: Zbigniew Bodek <z...@semihalf.com>
  Marcin Wojtas <m...@semihalf.com>
  Obtained from: Semihalf

Modified:
  head/sys/dev/etherswitch/e6000sw/e6000sw.c

Modified: head/sys/dev/etherswitch/e6000sw/e6000sw.c
==
--- head/sys/dev/etherswitch/e6000sw/e6000sw.c  Tue Jun 13 17:49:49 2017
(r319905)
+++ head/sys/dev/etherswitch/e6000sw/e6000sw.c  Tue Jun 13 18:35:14 2017
(r319906)
@@ -217,11 +217,15 @@ e6000sw_probe(device_t dev)
if (sc->sw_addr != 0 && (sc->sw_addr % 2) == 0)
sc->multi_chip = true;
 
-   /* Lock is necessary due to assertions. */
-   sx_init(>sx, "e6000sw");
+   /*
+* Create temporary lock, just to satisfy assertions,
+* when obtaining the switch ID. Destroy immediately afterwards.
+*/
+   sx_init(>sx, "e6000sw_tmp");
E6000SW_LOCK(sc);
id = e6000sw_readreg(sc, REG_PORT(0), SWITCH_ID);
E6000SW_UNLOCK(sc);
+   sx_destroy(>sx);
 
switch (id & 0xfff0) {
case 0x3400:
@@ -247,7 +251,6 @@ e6000sw_probe(device_t dev)
sc->num_ports = 7;
break;
default:
-   sx_destroy(>sx);
device_printf(dev, "Unrecognized device, id 0x%x.\n", id);
return (ENXIO);
}
@@ -354,6 +357,8 @@ e6000sw_attach(device_t dev)
device_printf(dev, "multi-chip addressing mode\n");
else
device_printf(dev, "single-chip addressing mode\n");
+
+   sx_init(>sx, "e6000sw");
 
E6000SW_LOCK(sc);
e6000sw_setup(dev, sc);
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svn commit: r319708 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:57:06 2017
New Revision: 319708
URL: https://svnweb.freebsd.org/changeset/base/319708

Log:
  Add function to dump PCIE MBUS decoding windows and bars
  
  This commit allows to dump PCIE MBUS and bars configuration
  for Marvell platforms.
  
  Submitted by:   Michal Mazur 
  Obtained from:  Semihalf
  Sponsored by:   Netgate
  Differential revision: https://reviews.freebsd.org/D10908

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu Jun  8 16:55:58 2017(r319707)
+++ head/sys/arm/mv/mv_common.c Thu Jun  8 16:57:06 2017(r319708)
@@ -111,6 +111,7 @@ static void decode_win_idma_dump(u_long base);
 static void decode_win_xor_dump(u_long base);
 static void decode_win_ahci_dump(u_long base);
 static void decode_win_sdhci_dump(u_long);
+static void decode_win_pcie_dump(u_long);
 
 static int fdt_get_ranges(const char *, void *, int, int *, int *);
 #ifdef SOC_MV_ARMADA38X
@@ -160,7 +161,7 @@ static struct soc_node_spec soc_nodes[] = {
{ "mrvl,xor", _win_xor_setup, _win_xor_dump },
{ "mrvl,idma", _win_idma_setup, _win_idma_dump },
{ "mrvl,cesa", _win_cesa_setup, _win_cesa_dump },
-   { "mrvl,pcie", _win_pcie_setup, NULL },
+   { "mrvl,pcie", _win_pcie_setup, _win_pcie_dump },
{ NULL, NULL, NULL },
 };
 
@@ -660,6 +661,8 @@ WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
+WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
+WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL);
 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
@@ -1440,6 +1443,22 @@ decode_win_eth_valid(void)
 /**
  * PCIE windows routines
  **/
+static void
+decode_win_pcie_dump(u_long base)
+{
+   int i;
+
+   printf("PCIE windows base 0x%08lx\n", base);
+   for (i = 0; i < MV_WIN_PCIE_MAX; i++)
+   printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n",
+   i, win_pcie_cr_read(base, i),
+   win_pcie_br_read(base, i), win_pcie_remap_read(base, i));
+
+   for (i = 0; i < MV_PCIE_BAR_MAX; i++)
+   printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n",
+   i, pcie_bar_cr_read(base, i),
+   pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i));
+}
 
 void
 decode_win_pcie_setup(u_long base)
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svn commit: r319707 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:55:58 2017
New Revision: 319707
URL: https://svnweb.freebsd.org/changeset/base/319707

Log:
  Restore DTS node of PCIe controller for A38X boards
  
  Add pcie-controller node as a bus-parent of pcie nodes for Armada38x
  boards. This reduces diff between Linux and FreeBSD PCIe device tree
  representation to the minimum. This commit also allows for using multiple
  PCIe ports, thanks to the recent driver updates, which support such
  hierarchy. Restore original PCIe nodes in armada-385.dtsi and
  apply necessary changes in hitherto unused armada-380.dtsi.
  
  Submitted by: Michal Mazur 
Marcin Wojtas 
  Obtained from:Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10907

Modified:
  head/sys/boot/fdt/dts/arm/armada-380.dtsi
  head/sys/boot/fdt/dts/arm/armada-385.dtsi
  head/sys/boot/fdt/dts/arm/armada-388-gp.dts
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Modified: head/sys/boot/fdt/dts/arm/armada-380.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-380.dtsi   Thu Jun  8 16:54:02 2017
(r319706)
+++ head/sys/boot/fdt/dts/arm/armada-380.dtsi   Thu Jun  8 16:55:58 2017
(r319707)
@@ -88,26 +88,29 @@
   <0x8200 0 0x8 MBUS_ID(0xf0, 0x01) 
0x8 0 0x2000
0x8200 0 0x4 MBUS_ID(0xf0, 0x01) 
0x4 0 0x2000
0x8200 0 0x44000 MBUS_ID(0xf0, 0x01) 
0x44000 0 0x2000
-   0x8200 0 0x48000 MBUS_ID(0xf0, 0x01) 
0x48000 0 0x2000
-   0x8200 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 
/* Port 0 MEM */
-   0x8100 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 
/* Port 0 IO  */
-   0x8200 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 
/* Port 1 MEM */
-   0x8100 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 
/* Port 1 IO  */
-   0x8200 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 
/* Port 2 MEM */
-   0x8100 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 
/* Port 2 IO  */>;
+   0x8200 0x0 0xf120 MBUS_ID(0x08, 0xe8) 
0xf120 0 0x0010 /* Port 0 MEM */
+   0x8100 0x0 0xf130 MBUS_ID(0x08, 0xe0) 
0xf130 0 0x0010 /* Port 0 IO  */
+   0x8200 0x0 0xf140 MBUS_ID(0x04, 0xe8) 
0xf140 0 0x0010 /* Port 1 MEM */
+   0x8100 0x0 0xf150 MBUS_ID(0x04, 0xe0) 
0xf150 0 0x0010 /* Port 1 IO  */
+   0x8200 0x0 0xf160 MBUS_ID(0x04, 0xd8) 
0xf160 0 0x0010 /* Port 2 MEM */
+   0x8100 0x0 0xf170 MBUS_ID(0x04, 0xd0) 
0xf170 0 0x0010 /* Port 2 IO  */
+   >;
 
/* x1 port */
pcie@1,0 {
+   compatible = "mrvl,pcie";
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8 0 
0x2000>;
-   reg = <0x0800 0 0 0 0>;
+   reg = <0x0 0x0 0x8 0x0 0x2000>;
#address-cells = <3>;
#size-cells = <2>;
-   #interrupt-cells = <1>;
-   ranges = <0x8200 0 0 0x8200 0x1 0 1 0
- 0x8100 0 0 0x8100 0x1 0 1 0>;
+   #interrupt-cells = <3>;
+   bus-range = <0 255>;
+   ranges = <0x8200 0x0 0x0 0x8200 0x0 
0xf120 0x0 0x0010
+ 0x8100 0x0 0x0 0x8100 0x0 
0xf130 0x0 0x0010>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0  GIC_SPI 29 
IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-parent = <>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = < 8>;
@@ -116,16 +119,19 @@
 
/* x1 port */
pcie@2,0 {
+   compatible = "mrvl,pcie";
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4 0 
0x2000>;
-   reg = <0x1000 0 0 0 0>;
+   reg = <0x0 0x0 0x4 0x0 0x2000>;
#address-cells = <3>;
#size-cells = <2>;

svn commit: r319706 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:54:02 2017
New Revision: 319706
URL: https://svnweb.freebsd.org/changeset/base/319706

Log:
  Support multi-port PCIe hierarchy in Marvell boards DTS
  
  This commit is another part of preparation for PCIe multi-port
  support for Marvell SoCs. Some device trees include pcie-controller
  node as a bus-parent of pcie nodes. This patch adds support for
  new bus, collects and configures device informations and finally
  adds PCIB devices as a childs of pcie-controller in Newbus hierarchy.
  
  Submitted by: Marcin Mazurek 
  Obtained form:Semihalf
  Sponsored by: Stormshield
  Reviewed by:https://reviews.freebsd.org/D10906

Added:
  head/sys/arm/mv/mv_pci_ctrl.c   (contents, props changed)
Modified:
  head/sys/arm/mv/files.mv
  head/sys/arm/mv/mv_pci.c

Modified: head/sys/arm/mv/files.mv
==
--- head/sys/arm/mv/files.mvThu Jun  8 16:51:46 2017(r319705)
+++ head/sys/arm/mv/files.mvThu Jun  8 16:54:02 2017(r319706)
@@ -16,6 +16,7 @@ arm/mv/gpio.c optionalgpio
 arm/mv/mv_common.c standard
 arm/mv/mv_localbus.c   standard
 arm/mv/mv_machdep.cstandard
+arm/mv/mv_pci_ctrl.c   optionalpci | fdt
 arm/mv/mv_pci.coptionalpci
 arm/mv/mv_ts.c standard
 arm/mv/timer.c optional!soc_mv_armada38x

Modified: head/sys/arm/mv/mv_pci.c
==
--- head/sys/arm/mv/mv_pci.cThu Jun  8 16:51:46 2017(r319705)
+++ head/sys/arm/mv/mv_pci.cThu Jun  8 16:54:02 2017(r319706)
@@ -394,6 +394,7 @@ static driver_t mv_pcib_driver = {
 devclass_t pcib_devclass;
 
 DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
+DRIVER_MODULE(pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
 
 static struct mtx pcicfg_mtx;
 
@@ -419,21 +420,29 @@ mv_pcib_attach(device_t self)
 {
struct mv_pcib_softc *sc;
phandle_t node, parnode;
-   uint32_t val, unit;
-   int err;
+   uint32_t val, reg0;
+   int err, bus, devfn, port_id;
 
sc = device_get_softc(self);
sc->sc_dev = self;
-   unit = fdt_get_unit(self);
 
-
node = ofw_bus_get_node(self);
parnode = OF_parent(node);
+
+   if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
+   sizeof(port_id)) <= 0) {
+   /* If port ID does not exist in the FDT set value to 0 */
+   if (!OF_hasprop(node, "marvell,pcie-port"))
+   port_id = 0;
+   else
+   return(ENXIO);
+   }
+
if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
sc->sc_type = MV_TYPE_PCIE;
-   sc->sc_win_target = MV_WIN_PCIE_TARGET(unit);
-   sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit);
-   sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit);
+   sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
+   sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
+   sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
} else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
sc->sc_type = MV_TYPE_PCI;
sc->sc_win_target = MV_WIN_PCI_TARGET;
@@ -476,7 +485,7 @@ mv_pcib_attach(device_t self)
/*
 * Enable PCIE device.
 */
-   mv_pcib_enable(sc, unit);
+   mv_pcib_enable(sc, port_id);
 
/*
 * Memory management.
@@ -484,6 +493,22 @@ mv_pcib_attach(device_t self)
err = mv_pcib_mem_init(sc);
if (err)
return (err);
+
+   /*
+* Preliminary bus enumeration to find first linked devices and set
+* appropriate bus number from which should start the actual enumeration
+*/
+   for (bus = 0; bus < PCI_BUSMAX; bus++) {
+   for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
+   reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 
0x7, 0x0, 4);
+   if (reg0 == (~0U))
+   continue; /* no device */
+   else {
+   sc->sc_busnr = bus; /* update bus number */
+   break;
+   }
+   }
+   }
 
if (sc->sc_mode == MV_MODE_ROOT) {
err = mv_pcib_init(sc, sc->sc_busnr,

Added: head/sys/arm/mv/mv_pci_ctrl.c
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/arm/mv/mv_pci_ctrl.c   Thu Jun  8 16:54:02 2017
(r319706)
@@ -0,0 +1,333 @@
+/*-
+ * Copyright (c) 2016 Stormshield
+ * Copyright (c) 2016 Semihalf
+ * All rights reserved.
+ *
+ * Developed 

svn commit: r319705 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:51:46 2017
New Revision: 319705
URL: https://svnweb.freebsd.org/changeset/base/319705

Log:
  Fix PCIe window decoding on Armada 38x
  
  Original PCIe nodes for Marvell SoCs consists of ports' nodes
  under main controller node. In order to properly parse
  this kind of representation in DT a mechanism for traversing
  through the tree required an update. Moreover, processing FDT
  data consisting of more than 2 cells had to be fixed,
  because the 'reg' property of mrvl,pcie node have additional
  parameter in front of 64-bit address. It should be skipped
  by default. This commit works properly with old mrvl,pcie
  representation for Kirkwood and ArmadaXP SoCs.
  
  Submitted by: Wojciech Macek 
Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Stormshield, Netgate
  Differential revision: https://reviews.freebsd.org/D10905

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu Jun  8 16:48:09 2017(r319704)
+++ head/sys/arm/mv/mv_common.c Thu Jun  8 16:51:46 2017(r319705)
@@ -2380,13 +2380,60 @@ moveon:
 }
 
 static int
-fdt_win_setup(void)
+fdt_win_process(phandle_t child)
 {
-   phandle_t node, child, sb;
+   int i;
struct soc_node_spec *soc_node;
+   int addr_cells, size_cells;
+   pcell_t reg[8];
u_long size, base;
-   int err, i;
 
+   for (i = 0; soc_nodes[i].compat != NULL; i++) {
+
+   soc_node = _nodes[i];
+
+   /* Setup only for enabled devices */
+   if (ofw_bus_node_status_okay(child) == 0)
+   continue;
+
+   if (!ofw_bus_node_is_compatible(child, soc_node->compat))
+   continue;
+
+   if (fdt_addrsize_cells(OF_parent(child), _cells,
+   _cells))
+   return (ENXIO);
+
+   if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))
+   return (ENOMEM);
+
+   if (OF_getprop(child, "reg", , sizeof(reg)) <= 0)
+   return (EINVAL);
+
+   if (addr_cells <= 2)
+   base = fdt_data_get([0], addr_cells);
+   else
+   base = fdt_data_get([addr_cells - 2], 2);
+   size = fdt_data_get([addr_cells], size_cells);
+
+   base = (base & 0x000f) | fdt_immr_va;
+   if (soc_node->decode_handler != NULL)
+   soc_node->decode_handler(base);
+   else
+   return (ENXIO);
+
+   if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
+   soc_node->dump_handler(base);
+   }
+
+   return (0);
+}
+static int
+fdt_win_setup(void)
+{
+   phandle_t node, child, sb;
+   phandle_t child_pci;
+   int err;
+
sb = 0;
node = OF_finddevice("/");
if (node == -1)
@@ -2398,29 +2445,21 @@ fdt_win_setup(void)
 */
child = OF_child(node);
while (child != 0) {
-   for (i = 0; soc_nodes[i].compat != NULL; i++) {
+   /* Lookup for callback and run */
+   err = fdt_win_process(child);
+   if (err != 0)
+   return (err);
 
-   soc_node = _nodes[i];
+   /* Process Marvell Armada-XP/38x PCIe controllers */
+   if (ofw_bus_node_is_compatible(child, 
"marvell,armada-370-pcie")) {
+   child_pci = OF_child(child);
+   while (child_pci != 0) {
+   err = fdt_win_process(child_pci);
+   if (err != 0)
+   return (err);
 
-   /* Setup only for enabled devices */
-   if (ofw_bus_node_status_okay(child) == 0)
-   continue;
-
-   if (!ofw_bus_node_is_compatible(child,soc_node->compat))
-   continue;
-
-   err = fdt_regsize(child, , );
-   if (err != 0)
-   return (err);
-
-   base = (base & 0x000f) | fdt_immr_va;
-   if (soc_node->decode_handler != NULL)
-   soc_node->decode_handler(base);
-   else
-   return (ENXIO);
-
-   if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
-   soc_node->dump_handler(base);
+   child_pci = OF_peer(child_pci);
+   }
}
 
/*
___
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svn commit: r319704 - head/sys/arm/mv/armada38x

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:48:09 2017
New Revision: 319704
URL: https://svnweb.freebsd.org/changeset/base/319704

Log:
  Enable MBUS bridge configuration in mv_rtc driver
  
  This patch fixes sporadic problems with updating time
  with mv_rtc driver by configuring access to it via MBUS.
  For this purpose already existing second set of resources
  in rtc@3800 node of Armada 38x DT is used.
  
  Submitted by: Dominik Ermel 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10901

Modified:
  head/sys/arm/mv/armada38x/rtc.c

Modified: head/sys/arm/mv/armada38x/rtc.c
==
--- head/sys/arm/mv/armada38x/rtc.c Thu Jun  8 16:46:38 2017
(r319703)
+++ head/sys/arm/mv/armada38x/rtc.c Thu Jun  8 16:48:09 2017
(r319704)
@@ -69,17 +69,30 @@ __FBSDID("$FreeBSD$");
 #defineRTC_STATUS_ALARM1_MASK  0x1
 #defineRTC_STATUS_ALARM2_MASK  0x2
 
-#defineMV_RTC_LOCK(sc) mtx_lock(&(sc)->mutex)
-#defineMV_RTC_UNLOCK(sc)   mtx_unlock(&(sc)->mutex)
+#defineMV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex)
+#defineMV_RTC_UNLOCK(sc)   mtx_unlock_spin(&(sc)->mutex)
 
+#defineRTC_BRIDGE_TIMING_CTRL  0x0
+#defineRTC_WRCLK_PERIOD_SHIFT  0
+#defineRTC_WRCLK_PERIOD_MASK   0x0003FF
+#defineRTC_WRCLK_PERIOD_MAX0x3FF
+#defineRTC_READ_OUTPUT_DELAY_SHIFT 26
+#defineRTC_READ_OUTPUT_DELAY_MASK  0x007C00
+#defineRTC_READ_OUTPUT_DELAY_MAX   0x1F
+
+#defineRTC_RES 0
+#defineRTC_SOC_RES 1
+
+
 static struct resource_spec res_spec[] = {
{ SYS_RES_MEMORY,   0,  RF_ACTIVE },
+   { SYS_RES_MEMORY,   1,  RF_ACTIVE },
{ -1, 0 }
 };
 
 struct mv_rtc_softc {
device_tdev;
-   struct resource *res;
+   struct resource *res[2];
struct mtx  mutex;
 };
 
@@ -90,9 +103,11 @@ static int mv_rtc_detach(device_t dev);
 static int mv_rtc_gettime(device_t dev, struct timespec *ts);
 static int mv_rtc_settime(device_t dev, struct timespec *ts);
 
-static uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off);
-static int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off,
+static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc,
+bus_size_t off);
+static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off,
 uint32_t val);
+static inline void mv_rtc_configure_bus(struct mv_rtc_softc *sc);
 
 static device_method_t mv_rtc_methods[] = {
DEVMETHOD(device_probe, mv_rtc_probe),
@@ -180,14 +195,16 @@ mv_rtc_attach(device_t dev)
 
clock_register(dev, RTC_RES_US);
 
-   mtx_init(>mutex, device_get_nameunit(dev), NULL, MTX_DEF);
+   mtx_init(>mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
 
-   ret = bus_alloc_resources(dev, res_spec, >res);
+   ret = bus_alloc_resources(dev, res_spec, sc->res);
+
if (ret != 0) {
device_printf(dev, "could not allocate resources\n");
mtx_destroy(>mutex);
return (ENXIO);
}
+   mv_rtc_configure_bus(sc);
 
return (0);
 }
@@ -201,7 +218,7 @@ mv_rtc_detach(device_t dev)
 
mtx_destroy(>mutex);
 
-   bus_release_resources(dev, res_spec, >res);
+   bus_release_resources(dev, res_spec, sc->res);
 
return (0);
 }
@@ -267,11 +284,11 @@ mv_rtc_settime(device_t dev, struct timespec *ts)
return (0);
 }
 
-static uint32_t
+static inline uint32_t
 mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off)
 {
 
-   return (bus_read_4(sc->res, off));
+   return (bus_read_4(sc->res[RTC_RES], off));
 }
 
 /*
@@ -279,12 +296,24 @@ mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t of
  * register write to the RTC hard macro so that the required update
  * can occur without holding off the system bus
  */
-static int
+static inline int
 mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val)
 {
 
-   bus_write_4(sc->res, off, val);
+   bus_write_4(sc->res[RTC_RES], off, val);
DELAY(5);
 
return (0);
+}
+
+static inline void
+mv_rtc_configure_bus(struct mv_rtc_softc *sc)
+{
+   int val;
+
+   val = bus_read_4(sc->res[RTC_SOC_RES], RTC_BRIDGE_TIMING_CTRL);
+   val &= ~(RTC_WRCLK_PERIOD_MASK | RTC_READ_OUTPUT_DELAY_MASK);
+   val |= RTC_WRCLK_PERIOD_MAX << RTC_WRCLK_PERIOD_SHIFT;
+   val |= RTC_READ_OUTPUT_DELAY_MAX << RTC_READ_OUTPUT_DELAY_SHIFT;
+   bus_write_4(sc->res[RTC_SOC_RES], RTC_BRIDGE_TIMING_CTRL, val);
 }
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svn commit: r319703 - head/sys/arm/mv/armada38x

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  8 16:46:38 2017
New Revision: 319703
URL: https://svnweb.freebsd.org/changeset/base/319703

Log:
  Add reset capability to mv_rtc driver
  
  This commit enables optional reset of the RTC, in case
  its registers' contents did not sustain the reboot or power-off/on
  sequence. Without it, further usage of RTC is impossible
  (e.g. writing values to RTC_TIME register will not succeed).
  
  The reset is performed only if Clock Correction register
  does not comprise RTC_NOMINAL_TIMING, what helps to distinguish,
  whether the software configured RTC before or it comprises
  the default value.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10900

Modified:
  head/sys/arm/mv/armada38x/rtc.c

Modified: head/sys/arm/mv/armada38x/rtc.c
==
--- head/sys/arm/mv/armada38x/rtc.c Thu Jun  8 16:18:41 2017
(r319702)
+++ head/sys/arm/mv/armada38x/rtc.c Thu Jun  8 16:46:38 2017
(r319703)
@@ -56,7 +56,19 @@ __FBSDID("$FreeBSD$");
 
 #defineRTC_STATUS  0x0
 #defineRTC_TIME0xC
+#defineRTC_TEST_CONFIG 0x1C
+#defineRTC_IRQ_1_CONFIG0x4
+#defineRTC_IRQ_2_CONFIG0x8
+#defineRTC_ALARM_1 0x10
+#defineRTC_ALARM_2 0x14
+#defineRTC_CLOCK_CORR  0x18
 
+#defineRTC_NOMINAL_TIMING  0x2000
+#defineRTC_NOMINAL_TIMING_MASK 0x7fff
+
+#defineRTC_STATUS_ALARM1_MASK  0x1
+#defineRTC_STATUS_ALARM2_MASK  0x2
+
 #defineMV_RTC_LOCK(sc) mtx_lock(&(sc)->mutex)
 #defineMV_RTC_UNLOCK(sc)   mtx_unlock(&(sc)->mutex)
 
@@ -103,6 +115,43 @@ static devclass_t mv_rtc_devclass;
 
 DRIVER_MODULE(mv_rtc, simplebus, mv_rtc_driver, mv_rtc_devclass, 0, 0);
 
+static void
+mv_rtc_reset(device_t dev)
+{
+   struct mv_rtc_softc *sc;
+
+   sc = device_get_softc(dev);
+
+   /* Reset Test register */
+   mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0);
+   DELAY(50);
+
+   /* Reset Time register */
+   mv_rtc_reg_write(sc, RTC_TIME, 0);
+   DELAY(62);
+
+   /* Reset Status register */
+   mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | 
RTC_STATUS_ALARM2_MASK));
+   DELAY(62);
+
+   /* Turn off Int1 and Int2 sources & clear the Alarm count */
+   mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0);
+   mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0);
+   mv_rtc_reg_write(sc, RTC_ALARM_1, 0);
+   mv_rtc_reg_write(sc, RTC_ALARM_2, 0);
+
+   /* Setup nominal register access timing */
+   mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING);
+
+   /* Reset Time register */
+   mv_rtc_reg_write(sc, RTC_TIME, 0);
+   DELAY(10);
+
+   /* Reset Status register */
+   mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | 
RTC_STATUS_ALARM2_MASK));
+   DELAY(50);
+}
+
 static int
 mv_rtc_probe(device_t dev)
 {
@@ -197,6 +246,12 @@ mv_rtc_settime(device_t dev, struct timespec *ts)
ts->tv_nsec = 0;
 
MV_RTC_LOCK(sc);
+
+   if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) !=
+   RTC_NOMINAL_TIMING) {
+   /* RTC was not resetted yet */
+   mv_rtc_reset(dev);
+   }
 
/*
 * According to errata FE-3124064, Write to RTC TIME register
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svn commit: r319201 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue May 30 12:00:56 2017
New Revision: 319201
URL: https://svnweb.freebsd.org/changeset/base/319201

Log:
  Introduce additional locks when releasing TX resources and buffers in ENA
  
  There could be race condition with TX cleaning routine when cleaning mbufs,
  when it was called directly from main sending thread (ena_mq_start).
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.
  Differential revision: https://reviews.freebsd.org/D10927

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue May 30 11:58:51 2017(r319200)
+++ head/sys/dev/ena/ena.c  Tue May 30 12:00:56 2017(r319201)
@@ -713,6 +713,7 @@ ena_free_tx_resources(struct ena_adapter *adapter, int
drbr_flush(adapter->ifp, tx_ring->br);
 
/* Free buffer DMA maps, */
+   ENA_RING_MTX_LOCK(tx_ring);
for (int i = 0; i < tx_ring->ring_size; i++) {
m_freem(tx_ring->tx_buffer_info[i].mbuf);
tx_ring->tx_buffer_info[i].mbuf = NULL;
@@ -721,6 +722,7 @@ ena_free_tx_resources(struct ena_adapter *adapter, int
bus_dmamap_destroy(adapter->tx_buf_tag,
tx_ring->tx_buffer_info[i].map);
}
+   ENA_RING_MTX_UNLOCK(tx_ring);
 
/* And free allocated memory. */
ENA_MEM_FREE(adapter->ena_dev->dmadev, tx_ring->tx_buffer_info);
@@ -1121,6 +1123,7 @@ ena_free_tx_bufs(struct ena_adapter *adapter, unsigned
 {
struct ena_ring *tx_ring = >tx_ring[qid];
 
+   ENA_RING_MTX_LOCK(tx_ring);
for (int i = 0; i < tx_ring->ring_size; i++) {
struct ena_tx_buffer *tx_info = _ring->tx_buffer_info[i];
 
@@ -1134,6 +1137,7 @@ ena_free_tx_bufs(struct ena_adapter *adapter, unsigned
m_free(tx_info->mbuf);
tx_info->mbuf = NULL;
}
+   ENA_RING_MTX_UNLOCK(tx_ring);
 
return;
 }
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svn commit: r319200 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue May 30 11:58:51 2017
New Revision: 319200
URL: https://svnweb.freebsd.org/changeset/base/319200

Log:
  Move ENA's hw stats updating routine to separate task
  
  Initially, stats were being updated each time OS was requesting for
  the first statistic.
  To read statistics from hw, condvar was used. cv_timedwait cannot be
  called when unsleepable lock is held, and this happens when FreeBSD
  is requesting statistic.
  Seperate task is reading statistics from NIC each 1 second.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.
  Differential revision: https://reviews.freebsd.org/D10926

Modified:
  head/sys/dev/ena/ena.c
  head/sys/dev/ena/ena.h

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue May 30 11:56:54 2017(r319199)
+++ head/sys/dev/ena/ena.c  Tue May 30 11:58:51 2017(r319200)
@@ -141,6 +141,7 @@ static void ena_free_irqs(struct ena_adapter*);
 static voidena_disable_msix(struct ena_adapter *);
 static voidena_unmask_all_io_irqs(struct ena_adapter *);
 static int ena_rss_configure(struct ena_adapter *);
+static voidena_update_hw_stats(void *, int);
 static int ena_up_complete(struct ena_adapter *);
 static int ena_up(struct ena_adapter *);
 static voidena_down(struct ena_adapter *);
@@ -2058,6 +2059,25 @@ static int ena_rss_configure(struct ena_adapter *adapt
return 0;
 }
 
+static void
+ena_update_hw_stats(void *arg, int pending)
+{
+   struct ena_adapter *adapter = arg;
+   int rc;
+
+   for (;;) {
+   if (!adapter->up)
+   return;
+
+   rc = ena_update_stats_counters(adapter);
+   if (rc)
+   ena_trace(ENA_WARNING,
+   "Error updating stats counters, rc = %d", rc);
+
+   pause("ena update hw stats", hz);
+   }
+}
+
 static int
 ena_up_complete(struct ena_adapter *adapter)
 {
@@ -2141,6 +2161,8 @@ ena_up(struct ena_adapter *adapter)
callout_reset_sbt(>timer_service, SBT_1S, SBT_1S,
ena_timer_service, (void *)adapter, 0);
 
+   taskqueue_enqueue(adapter->stats_tq, >stats_task);
+
adapter->up = true;
}
 
@@ -2193,24 +2215,8 @@ ena_get_counter(if_t ifp, ift_counter cnt)
 {
struct ena_adapter *adapter;
struct ena_hw_stats *stats;
-   int rc;
 
adapter = if_getsoftc(ifp);
-
-   /*
-* Update only when asking for first counter and interface is up.
-* Usually asks for all statistics in sequence.
-*/
-   if (adapter->up) {
-   if (cnt == 0) {
-   rc = ena_update_stats_counters(adapter);
-   if (rc) {
-   ena_trace(ENA_WARNING,
-   "Error updating stats counters, rc = %d",
-   rc);
-   }
-   }
-   }
stats = >hw_stats;
 
switch (cnt) {
@@ -2501,6 +2507,10 @@ ena_down(struct ena_adapter *adapter)
if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE,
IFF_DRV_RUNNING);
 
+   /* Drain task responsible for updating hw stats */
+   while (taskqueue_cancel(adapter->stats_tq, 
>stats_task, NULL))
+   taskqueue_drain(adapter->stats_tq, 
>stats_task);
+
ena_free_io_irq(adapter);
 
ena_destroy_all_io_queues(adapter);
@@ -3616,6 +3626,18 @@ ena_attach(device_t pdev)
taskqueue_start_threads(>reset_tq, 1, PI_NET,
"%s rstq", device_get_nameunit(adapter->pdev));
 
+   /* Initialize task queue responsible for updating hw stats */
+   TASK_INIT(>stats_task, 0, ena_update_hw_stats, adapter);
+   adapter->stats_tq = taskqueue_create_fast("ena_stats_update",
+   M_WAITOK | M_ZERO, taskqueue_thread_enqueue, >stats_tq);
+   if (adapter->stats_tq == NULL) {
+   device_printf(adapter->pdev,
+   "Unable to create taskqueue for updating hw stats\n");
+   goto err_stats_tq;
+   }
+   taskqueue_start_threads(>stats_tq, 1, PI_REALTIME,
+   "%s stats tq", device_get_nameunit(adapter->pdev));
+
/* Initialize statistics */
ena_alloc_counters((counter_u64_t *)>dev_stats,
sizeof(struct ena_stats_dev));
@@ -3628,6 +3650,8 @@ ena_attach(device_t pdev)
adapter->running = true;
return (0);
 
+err_stats_tq:
+   taskqueue_free(adapter->reset_tq);
 err_reset_tq:
ena_free_mgmnt_irq(adapter);
ena_disable_msix(adapter);
@@ -3682,6 +3706,8 @@ ena_detach(device_t pdev)
sx_xlock(>ioctl_sx);
ena_down(adapter);
sx_unlock(>ioctl_sx);
+
+   taskqueue_free(adapter->stats_tq);
 

svn commit: r319199 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue May 30 11:56:54 2017
New Revision: 319199
URL: https://svnweb.freebsd.org/changeset/base/319199

Log:
  Add error handling to the ENA driver if init of the reset task fails
  
  Also, to simplify cleaning routine, reset task is initialized before
  allocating statistics and other resources.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.
  Differential revision: https://reviews.freebsd.org/D10925

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue May 30 11:55:02 2017(r319198)
+++ head/sys/dev/ena/ena.c  Tue May 30 11:56:54 2017(r319199)
@@ -3604,6 +3604,18 @@ ena_attach(device_t pdev)
goto err_ifp_free;
}
 
+   /* Initialize reset task queue */
+   TASK_INIT(>reset_task, 0, ena_reset_task, adapter);
+   adapter->reset_tq = taskqueue_create("ena_reset_enqueue",
+   M_WAITOK | M_ZERO, taskqueue_thread_enqueue, >reset_tq);
+   if (adapter->reset_tq == NULL) {
+   device_printf(adapter->pdev,
+   "Unable to create reset task queue\n");
+   goto err_reset_tq;
+   }
+   taskqueue_start_threads(>reset_tq, 1, PI_NET,
+   "%s rstq", device_get_nameunit(adapter->pdev));
+
/* Initialize statistics */
ena_alloc_counters((counter_u64_t *)>dev_stats,
sizeof(struct ena_stats_dev));
@@ -3613,16 +3625,12 @@ ena_attach(device_t pdev)
/* Tell the stack that the interface is not active */
if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
 
-   /* Initialize reset task queue */
-   TASK_INIT(>reset_task, 0, ena_reset_task, adapter);
-   adapter->reset_tq = taskqueue_create("ena_reset_enqueue",
-   M_WAITOK | M_ZERO, taskqueue_thread_enqueue, >reset_tq);
-   taskqueue_start_threads(>reset_tq, 1, PI_NET,
-   "%s rstq", device_get_nameunit(adapter->pdev));
-
adapter->running = true;
return (0);
 
+err_reset_tq:
+   ena_free_mgmnt_irq(adapter);
+   ena_disable_msix(adapter);
 err_ifp_free:
if_detach(adapter->ifp);
if_free(adapter->ifp);
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svn commit: r319198 - head/sys/dev/ena

[Zbigniew Bodek]

Author: zbb
Date: Tue May 30 11:55:02 2017
New Revision: 319198
URL: https://svnweb.freebsd.org/changeset/base/319198

Log:
  Add locks before each ena_up and ena_down
  
  Lock only ena_up and ena_down calls in ioctl handler, instead of whole
  ioctl. Locking ioctl with sx lock that is sleepable, is not allowed in
  some cases, e.g. when multicast options are being changed.
  Additional locking was added in deatch function to prevent race condition
  with ioctl function.
  
  Submitted by:   Michal Krawczyk 
  Obtained from:  Semihalf
  Sponsored by:   Amazon.com Inc.
  Differential revision: https://reviews.freebsd.org/D10924

Modified:
  head/sys/dev/ena/ena.c

Modified: head/sys/dev/ena/ena.c
==
--- head/sys/dev/ena/ena.c  Tue May 30 11:53:18 2017(r319197)
+++ head/sys/dev/ena/ena.c  Tue May 30 11:55:02 2017(r319198)
@@ -2285,16 +2285,16 @@ ena_ioctl(if_t ifp, u_long command, caddr_t data)
/*
 * Acquiring lock to prevent from running up and down routines parallel.
 */
-   sx_xlock(>ioctl_sx);
-
rc = 0;
switch (command) {
case SIOCSIFMTU:
+   sx_xlock(>ioctl_sx);
ena_down(adapter);
 
ena_change_mtu(ifp, ifr->ifr_mtu);
 
rc = ena_up(adapter);
+   sx_unlock(>ioctl_sx);
break;
 
case SIOCSIFFLAGS:
@@ -2306,11 +2306,16 @@ ena_ioctl(if_t ifp, u_long command, caddr_t data)
"ioctl promisc/allmulti\n");
}
} else {
+   sx_xlock(>ioctl_sx);
rc = ena_up(adapter);
+   sx_unlock(>ioctl_sx);
}
} else {
-   if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+   if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+   sx_xlock(>ioctl_sx);
ena_down(adapter);
+   sx_unlock(>ioctl_sx);
+   }
}
break;
 
@@ -2333,8 +2338,10 @@ ena_ioctl(if_t ifp, u_long command, caddr_t data)
}
 
if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
+   sx_xlock(>ioctl_sx);
ena_down(adapter);
rc = ena_up(adapter);
+   sx_unlock(>ioctl_sx);
}
}
 
@@ -2344,8 +2351,6 @@ ena_ioctl(if_t ifp, u_long command, caddr_t data)
break;
}
 
-   sx_unlock(>ioctl_sx);
-
return (rc);
 }
 
@@ -3666,7 +3671,9 @@ ena_detach(device_t pdev)
taskqueue_drain(adapter->reset_tq, >reset_task);
taskqueue_free(adapter->reset_tq);
 
+   sx_xlock(>ioctl_sx);
ena_down(adapter);
+   sx_unlock(>ioctl_sx);
 
if (adapter->ifp != NULL) {
ether_ifdetach(adapter->ifp);
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svn commit: r318880 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:34:21 2017
New Revision: 318880
URL: https://svnweb.freebsd.org/changeset/base/318880

Log:
  Unmask legacy interrupts on Marvell PCIE controller
  
  This patch fixes a bug introduced with commit:
  r294510  "Remove an extra '!' found by clang 3.8."
  
  '!' was removed without inverting the logic, which
  broke PCIe legacy interrupts operation for Marvell
  controllers.
  
  Submitted by: Michal Mazur 
  Obtained from: Semihalf
  Sponsored by: Netgate

Modified:
  head/sys/arm/mv/mv_pci.c

Modified: head/sys/arm/mv/mv_pci.c
==
--- head/sys/arm/mv/mv_pci.cThu May 25 14:27:54 2017(r318879)
+++ head/sys/arm/mv/mv_pci.cThu May 25 14:34:21 2017(r318880)
@@ -918,7 +918,7 @@ static inline void
 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
 {
 
-   if (sc->sc_type != MV_TYPE_PCI)
+   if (sc->sc_type != MV_TYPE_PCIE)
return;
 
bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
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svn commit: r318878 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:25:05 2017
New Revision: 318878
URL: https://svnweb.freebsd.org/changeset/base/318878

Log:
  Add workaround for CESA MBUS windows with 4GB DRAM
  
  Armada 38x SoC's equipped with 4GB DRAM suffer freeze
  during CESA operation, if MBUS window opened at given
  DRAM CS reaches end of the address space. Apply a workaround
  by setting the window size to the closest possible
  value, i.e. divide it by 2 (it has to be power-of-2).
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10724

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu May 25 14:23:49 2017(r318877)
+++ head/sys/arm/mv/mv_common.c Thu May 25 14:25:05 2017(r318878)
@@ -1116,6 +1116,7 @@ static void
 decode_win_cesa_setup(u_long base)
 {
uint32_t br, cr;
+   uint64_t size;
int i, j;
 
for (i = 0; i < MV_WIN_CESA_MAX; i++) {
@@ -1128,7 +1129,21 @@ decode_win_cesa_setup(u_long base)
if (ddr_is_active(i)) {
br = ddr_base(i);
 
-   cr = (((ddr_size(i) - 1) & 0x) |
+   size = ddr_size(i);
+#ifdef SOC_MV_ARMADA38X
+   /*
+* Armada 38x SoC's equipped with 4GB DRAM
+* suffer freeze during CESA operation, if
+* MBUS window opened at given DRAM CS reaches
+* end of the address space. Apply a workaround
+* by setting the window size to the closest possible
+* value, i.e. divide it by 2.
+*/
+   if (size + ddr_base(i) == 0x1ULL)
+   size /= 2;
+#endif
+
+   cr = (((size - 1) & 0x) |
(ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
(ddr_target(i) << IO_WIN_TGT_SHIFT) |
IO_WIN_ENA_MASK);
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svn commit: r318877 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:23:49 2017
New Revision: 318877
URL: https://svnweb.freebsd.org/changeset/base/318877

Log:
  Fix PM recognition on recent Marvell boards
  
  PM status is only supported on Kirkwood and Disvovery.
  Cleanup the code to properly report its state on
  other platforms.
  
  Submitted by: Wojciech Macek 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10718

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu May 25 14:22:00 2017(r318876)
+++ head/sys/arm/mv/mv_common.c Thu May 25 14:23:49 2017(r318877)
@@ -133,6 +133,16 @@ const struct decode_win *cpu_wins = cpu_
 typedef void (*decode_win_setup_t)(u_long);
 typedef void (*dump_win_t)(u_long);
 
+/*
+ * The power status of device feature is only supported on
+ * Kirkwood and Discovery SoCs.
+ */
+#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
+#defineSOC_MV_POWER_STAT_SUPPORTED 1
+#else
+#defineSOC_MV_POWER_STAT_SUPPORTED 0
+#endif
+
 struct soc_node_spec {
const char  *compat;
decode_win_setup_t  decode_handler;
@@ -174,10 +184,10 @@ static struct fdt_pm_mask_entry fdt_pm_m
 static __inline int
 pm_is_disabled(uint32_t mask)
 {
-#if defined(SOC_MV_KIRKWOOD)
-   return (soc_power_ctrl_get(mask) == mask);
-#else
+#if SOC_MV_POWER_STAT_SUPPORTED
return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
+#else
+   return (0);
 #endif
 }
 
@@ -364,7 +374,7 @@ uint32_t
 soc_power_ctrl_get(uint32_t mask)
 {
 
-#if !defined(SOC_MV_ORION)
+#if SOC_MV_POWER_STAT_SUPPORTED
if (mask != CPU_PM_CTRL_NONE)
mask &= read_cpu_ctrl(CPU_PM_CTRL);
 
@@ -1168,7 +1178,6 @@ decode_win_usb_setup(u_long base)
uint32_t br, cr;
int i, j;
 
-
if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
return;
 
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svn commit: r318876 - in head/sys/arm/mv: . armada armada38x

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:22:00 2017
New Revision: 318876
URL: https://svnweb.freebsd.org/changeset/base/318876

Log:
  Introduce separate watchdog driver for Armada to fix phony DELAY
  
  DELAY is a problematic routine called all over the kernel.
  Armada38x using CA-9 CPUs are using mpcore timer to count events
  and measure time but DELAY in the mpcore timer code is a weak
  function reference and therefore will be replaced by the platform
  implementation if the one is introduced. Since Armada38x uses
  on-chip watchdog to which the driver is merged with the on-chip timer
  driver there will be a platform DELAY implementation.
  The latter however will not use any HW timers as it will not attempt
  to configure any. Phony busy loop will be used instead.
  
  To fix that we introduce a separate watchdog driver for Armada platforms,
  (currently only A38X) and stop using Marvell timer driver. That
  switches DELAY to the desired implementation.
  
  Submitted by: Zbigniew Bodek <z...@semihalf.com>
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10710

Added:
  head/sys/arm/mv/armada/wdt.c   (contents, props changed)
Modified:
  head/sys/arm/mv/armada38x/files.armada38x
  head/sys/arm/mv/files.mv

Added: head/sys/arm/mv/armada/wdt.c
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/arm/mv/armada/wdt.cThu May 25 14:22:00 2017
(r318876)
@@ -0,0 +1,285 @@
+/*-
+ * Copyright (c) 2006 Benno Rice.
+ * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
+ * All rights reserved.
+ *
+ * Adapted to Marvell SoC by Semihalf.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * from: FreeBSD: 
//depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
+ */
+
+#include 
+__FBSDID("$FreeBSD$");
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#define INITIAL_TIMECOUNTER(0x)
+#define MAX_WATCHDOG_TICKS (0x)
+
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
+#define MV_CLOCK_SRC   2500/* Timers' 25MHz mode */
+#else
+#define MV_CLOCK_SRC   get_tclk()
+#endif
+
+#if defined(SOC_MV_ARMADA38X)
+#defineWATCHDOG_TIMER  4
+#else
+#defineWATCHDOG_TIMER  2
+#endif
+
+struct mv_wdt_softc {
+   struct resource *   wdt_res;
+   struct mtx  wdt_mtx;
+};
+
+static struct resource_spec mv_wdt_spec[] = {
+   { SYS_RES_MEMORY,   0,  RF_ACTIVE },
+   { -1, 0 }
+};
+
+static struct ofw_compat_data mv_wdt_compat[] = {
+   {"marvell,armada-380-wdt",  true},
+   {NULL,  false}
+};
+
+static struct mv_wdt_softc *wdt_softc = NULL;
+int timers_initialized = 0;
+
+static int mv_wdt_probe(device_t);
+static int mv_wdt_attach(device_t);
+
+static uint32_tmv_get_timer_control(void);
+static void mv_set_timer_control(uint32_t);
+static void mv_set_timer(uint32_t, uint32_t);
+
+static void mv_watchdog_enable(void);
+static void mv_watchdog_disable(void);
+static void mv_watchdog_event(void *, unsigned int, int *);
+
+static device_method_t mv_wdt_methods[] = {
+   DEVMETHOD(device_probe, mv_wdt_probe),
+   DEVMETHOD(device_attach, mv_wdt_attach),
+
+   { 0, 0 }
+};
+
+static driver_t mv_wdt_driver = {
+   "wdt",
+   mv_wdt_methods,
+   sizeof(struct mv_wdt_softc),
+};
+
+static devclass_t mv_wdt_devclass;
+
+DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, mv_wdt_devclass, 0, 0);
+s

svn commit: r318875 - in head/sys/arm/mv: . armada38x

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:19:20 2017
New Revision: 318875
URL: https://svnweb.freebsd.org/changeset/base/318875

Log:
  Enable SCU Speculative linefills to L2 on Armada 38x
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10709

Modified:
  head/sys/arm/mv/armada38x/armada38x.c
  head/sys/arm/mv/mvreg.h

Modified: head/sys/arm/mv/armada38x/armada38x.c
==
--- head/sys/arm/mv/armada38x/armada38x.c   Thu May 25 14:16:43 2017
(r318874)
+++ head/sys/arm/mv/armada38x/armada38x.c   Thu May 25 14:19:20 2017
(r318875)
@@ -173,9 +173,13 @@ armada38x_scu_enable(void)
 
/* Enable SCU */
val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
-   if (!(val & MV_SCU_ENABLE))
+   if (!(val & MV_SCU_ENABLE)) {
+   /* Enable SCU Speculative linefills to L2 */
+   val |= MV_SCU_SL_L2_ENABLE;
+
bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
val | MV_SCU_ENABLE);
+   }
 
bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
return (0);

Modified: head/sys/arm/mv/mvreg.h
==
--- head/sys/arm/mv/mvreg.h Thu May 25 14:16:43 2017(r318874)
+++ head/sys/arm/mv/mvreg.h Thu May 25 14:19:20 2017(r318875)
@@ -424,7 +424,8 @@
 #defineMV_SCU_REGS_LEN 0x100
 #defineMV_SCU_REG_CTRL 0x00
 #defineMV_SCU_REG_CONFIG   0x04
-#defineMV_SCU_ENABLE   1
+#defineMV_SCU_ENABLE   (1 << 0)
+#defineMV_SCU_SL_L2_ENABLE (1 << 3)
 #defineSCU_CFG_REG_NCPU_MASK   0x3
 #endif
 
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svn commit: r318874 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu May 25 14:16:43 2017
New Revision: 318874
URL: https://svnweb.freebsd.org/changeset/base/318874

Log:
  Fix memory corruption while configuring CPU windows on Marvell SoCs
  
  Resolving CPU windows from localbus entry caused buffer overflow
  and memory corruption. Fix wrong indexing and ensure the index
  does not exceed table size.
  
  Submitted by: Wojciech Macek 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10720

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu May 25 12:57:15 2017(r318873)
+++ head/sys/arm/mv/mv_common.c Thu May 25 14:16:43 2017(r318874)
@@ -2269,6 +2269,12 @@ win_cpu_from_dt(void)
entry_size = tuple_size / sizeof(pcell_t);
cpu_wins_no = tuples;
 
+   /* Check range */
+   if (tuples > nitems(cpu_win_tbl)) {
+   debugf("too many tuples to fit into cpu_win_tbl\n");
+   return (ENOMEM);
+   }
+
for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
cpu_win_tbl[t].target = 1;
cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
@@ -2301,6 +2307,12 @@ moveon:
if (fdt_regsize(node, _base, _size) != 0)
return (EINVAL);
 
+   /* Check range */
+   if (t >= nitems(cpu_win_tbl)) {
+   debugf("cannot fit CESA tuple into cpu_win_tbl\n");
+   return (ENOMEM);
+   }
+
cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
 #ifdef SOC_MV_ARMADA38X
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
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svn commit: r318647 - in head: share/man/man4 sys/conf sys/dev/ena sys/modules sys/modules/ena

[Zbigniew Bodek]

Author: zbb
Date: Mon May 22 14:46:13 2017
New Revision: 318647
URL: https://svnweb.freebsd.org/changeset/base/318647

Log:
  Add support for Amazon Elastic Network Adapter (ENA) NIC
  
  ENA is a networking interface designed to make good use of modern CPU
  features and system architectures.
  
  The ENA device exposes a lightweight management interface with a
  minimal set of memory mapped registers and extendable command set
  through an Admin Queue.
  
  The driver supports a range of ENA devices, is link-speed independent
  (i.e., the same driver is used for 10GbE, 25GbE, 40GbE, etc.), and has
  a negotiated and extendable feature set.
  
  Some ENA devices support SR-IOV. This driver is used for both the
  SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
  
  ENA devices enable high speed and low overhead network traffic
  processing by providing multiple Tx/Rx queue pairs (the maximum number
  is advertised by the device via the Admin Queue), a dedicated MSI-X
  interrupt vector per Tx/Rx queue pair, and CPU cacheline optimized
  data placement.
  
  The ENA driver supports industry standard TCP/IP offload features such
  as checksum offload and TCP transmit segmentation offload (TSO).
  Receive-side scaling (RSS) is supported for multi-core scaling.
  
  The ENA driver and its corresponding devices implement health
  monitoring mechanisms such as watchdog, enabling the device and driver
  to recover in a manner transparent to the application, as well as
  debug logs.
  
  Some of the ENA devices support a working mode called Low-latency
  Queue (LLQ), which saves several more microseconds. This feature will
  be implemented for driver in future releases.
  
  Submitted by: Michal Krawczyk 
Jakub Palider 
Jan Medala 
  Obtained from: Semihalf
  Sponsored by: Amazon.com Inc.
  Differential revision: https://reviews.freebsd.org/D10427

Added:
  head/share/man/man4/ena.4   (contents, props changed)
  head/sys/dev/ena/
  head/sys/dev/ena/ena.c   (contents, props changed)
  head/sys/dev/ena/ena.h   (contents, props changed)
  head/sys/dev/ena/ena_sysctl.c   (contents, props changed)
  head/sys/dev/ena/ena_sysctl.h   (contents, props changed)
  head/sys/modules/ena/
  head/sys/modules/ena/Makefile   (contents, props changed)
Modified:
  head/sys/conf/files
  head/sys/modules/Makefile

Added: head/share/man/man4/ena.4
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/share/man/man4/ena.4   Mon May 22 14:46:13 2017(r318647)
@@ -0,0 +1,255 @@
+.\" Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\"
+.\" 1. Redistributions of source code must retain the above copyright
+.\"notice, this list of conditions and the following disclaimer.
+.\"
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"notice, this list of conditions and the following disclaimer in
+.\"the documentation and/or other materials provided with the
+.\"distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+.\" "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+.\" LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+.\" A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+.\" OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+.\" SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+.\" LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+.\" OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd May 04, 2017
+.Dt ENA 4
+.Os
+.Sh NAME
+.Nm ena
+.Nd "FreeBSD kernel driver for Elastic Network Adapter (ENA) family"
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device ena"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+if_ena_load="YES"
+.Ed
+.Sh DESCRIPTION
+The ENA is a networking interface designed to make good use of modern CPU
+features and system architectures.
+.Pp
+The ENA device exposes a lightweight management interface with a
+minimal set of memory mapped registers and extendable command set
+through an Admin Queue.
+.Pp
+The driver supports a range of ENA devices, is 

svn commit: r318411 - head/sys/dev/etherswitch/e6000sw

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:59:45 2017
New Revision: 318411
URL: https://svnweb.freebsd.org/changeset/base/318411

Log:
  Add missing unlock in e6000sw driver
  
  This patch adds missing unlock on attach failure.
  
  Submitted by:  Zbigniew Bodek <z...@semihalf.com>
  Obtained from: Semihalf
  Sponsored by:  Stormshield
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10712

Modified:
  head/sys/dev/etherswitch/e6000sw/e6000sw.c

Modified: head/sys/dev/etherswitch/e6000sw/e6000sw.c
==
--- head/sys/dev/etherswitch/e6000sw/e6000sw.c  Wed May 17 15:58:39 2017
(r318410)
+++ head/sys/dev/etherswitch/e6000sw/e6000sw.c  Wed May 17 15:59:45 2017
(r318411)
@@ -425,6 +425,7 @@ e6000sw_attach(device_t dev)
return (0);
 
 out_fail:
+   E6000SW_UNLOCK(sc);
e6000sw_detach(dev);
 
return (err);
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svn commit: r318410 - head/sys/dev/etherswitch/e6000sw

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:58:39 2017
New Revision: 318410
URL: https://svnweb.freebsd.org/changeset/base/318410

Log:
  Fix broken malloc in e6000sw
  
  Malloc should always return something when M_WAITOK flag is used,
  but keep this code and change flag to M_NOWAIT as it is under a lock
  (allows for possible future change). Free ifnet structure to avoid
  memory leak on failure.
  
  Submitted by:  Zbigniew Bodek <z...@semihalf.com>
  Obtained from: Semihalf
  Sponsored by:  Stormshield
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10711

Modified:
  head/sys/dev/etherswitch/e6000sw/e6000sw.c

Modified: head/sys/dev/etherswitch/e6000sw/e6000sw.c
==
--- head/sys/dev/etherswitch/e6000sw/e6000sw.c  Wed May 17 15:57:14 2017
(r318409)
+++ head/sys/dev/etherswitch/e6000sw/e6000sw.c  Wed May 17 15:58:39 2017
(r318410)
@@ -321,9 +321,11 @@ e6000sw_init_interface(e6000sw_softc_t *
sc->ifp[port]->if_softc = sc;
sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST |
IFF_DRV_RUNNING | IFF_SIMPLEX;
-   sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_WAITOK);
-   if (sc->ifname[port] == NULL)
+   sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT);
+   if (sc->ifname[port] == NULL) {
+   if_free(sc->ifp[port]);
return (ENOMEM);
+   }
memcpy(sc->ifname[port], name, strlen(name) + 1);
if_initname(sc->ifp[port], sc->ifname[port], port);
 
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svn commit: r318409 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:57:14 2017
New Revision: 318409
URL: https://svnweb.freebsd.org/changeset/base/318409

Log:
  Fix registration of MPIC driver
  
  Submitted by:  Michal Mazur 
  Obtained from: Semihalf
  Sponsored by:  Netgate
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10717

Modified:
  head/sys/arm/mv/mpic.c

Modified: head/sys/arm/mv/mpic.c
==
--- head/sys/arm/mv/mpic.c  Wed May 17 15:56:09 2017(r318408)
+++ head/sys/arm/mv/mpic.c  Wed May 17 15:57:14 2017(r318409)
@@ -273,6 +273,9 @@ mv_mpic_attach(device_t dev)
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);
}
+
+   OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
+
if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
device_printf(dev, "could not register PIC\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
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svn commit: r318408 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:56:09 2017
New Revision: 318408
URL: https://svnweb.freebsd.org/changeset/base/318408

Log:
  Correct MPIC order of attachment
  
  If MPIC happens to be a slave interrupt controller (as on Armada38x),
  it should be attached after primary interrupt controller.
  Thus BUS_PASS_ORDER_LATE was added to default BUS_PASS_INTERRUPT.
  
  This change doesn't affect the cases when MPIC is standalone IC.
  
  Submitted by:  Bartosz Szczepanek 
  Obtained from: Semihalf
  Sponsored by:  Stormshield, Netgate
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10715

Modified:
  head/sys/arm/mv/mpic.c

Modified: head/sys/arm/mv/mpic.c
==
--- head/sys/arm/mv/mpic.c  Wed May 17 15:54:33 2017(r318407)
+++ head/sys/arm/mv/mpic.c  Wed May 17 15:56:09 2017(r318408)
@@ -398,7 +398,7 @@ static driver_t mv_mpic_driver = {
 static devclass_t mv_mpic_devclass;
 
 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
-BUS_PASS_INTERRUPT);
+BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
 
 #ifndef INTRNG
 int
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svn commit: r318407 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:54:33 2017
New Revision: 318407
URL: https://svnweb.freebsd.org/changeset/base/318407

Log:
  Enable proper parsing of nested simlpe-buses on Marvell platforms
  
  OF_finddevice doesn't find the "simple-bus" node, which is problematic
  for Marvell platforms, using nested buses in Device Tree, like
  Armada 38x SoC.
  
  Submitted by: Arnaud Ysmal 
  Obtained from: Stormshield
  Sponsored by: Stormshield
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10719

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Wed May 17 15:53:13 2017(r318406)
+++ head/sys/arm/mv/mv_common.c Wed May 17 15:54:33 2017(r318407)
@@ -2280,11 +2280,12 @@ moveon:
 static int
 fdt_win_setup(void)
 {
-   phandle_t node, child;
+   phandle_t node, child, sb;
struct soc_node_spec *soc_node;
u_long size, base;
int err, i;
 
+   sb = 0;
node = OF_finddevice("/");
if (node == -1)
panic("fdt_win_setup: no root node");
@@ -2326,7 +2327,7 @@ fdt_win_setup(void)
 */
child = OF_peer(child);
if ((child == 0) && (node == OF_finddevice("/"))) {
-   node = fdt_find_compatible(node, "simple-bus", 0);
+   sb = node = fdt_find_compatible(node, "simple-bus", 0);
if (node == 0)
return (ENXIO);
child = OF_child(node);
@@ -2336,7 +2337,7 @@ fdt_win_setup(void)
 * it is present) and its children. This node also have
 * "simple-bus" compatible.
 */
-   if ((child == 0) && (node == OF_finddevice("simple-bus"))) {
+   if ((child == 0) && (node == sb)) {
node = fdt_find_compatible(node, "simple-bus", 0);
if (node == 0)
return (0);
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svn commit: r318406 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:53:13 2017
New Revision: 318406
URL: https://svnweb.freebsd.org/changeset/base/318406

Log:
  Parse EHCI windows on Marvell platforms
  
  Add missing compatibility string to allow proper
  window configuration for EHCI devices.
  
  Submitted by: Wojciech Macek 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10722

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Wed May 17 15:52:04 2017(r318405)
+++ head/sys/arm/mv/mv_common.c Wed May 17 15:53:13 2017(r318406)
@@ -139,6 +139,7 @@ struct soc_node_spec {
 static struct soc_node_spec soc_nodes[] = {
{ "mrvl,ge", _win_eth_setup, _win_eth_dump },
{ "mrvl,usb-ehci", _win_usb_setup, _win_usb_dump },
+   { "marvell,orion-ehci", _win_usb_setup, _win_usb_dump },
{ "marvell,armada-380-xhci", _win_usb3_setup, 
_win_usb3_dump },
{ "marvell,armada-380-ahci", _win_ahci_setup, 
_win_ahci_dump },
{ "marvell,armada-380-sdhci", _win_sdhci_setup, 
_win_sdhci_dump },
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svn commit: r318405 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Wed May 17 15:52:04 2017
New Revision: 318405
URL: https://svnweb.freebsd.org/changeset/base/318405

Log:
  Fix USB3.0 decoding windows on Armada38x
  
  Set correct offset for MBUS windows configuration in
  USB3.0 interface.
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: loos
  Differential revision: https://reviews.freebsd.org/D10721

Modified:
  head/sys/arm/mv/mvwin.h

Modified: head/sys/arm/mv/mvwin.h
==
--- head/sys/arm/mv/mvwin.h Wed May 17 15:13:01 2017(r318404)
+++ head/sys/arm/mv/mvwin.h Wed May 17 15:52:04 2017(r318405)
@@ -220,8 +220,8 @@
 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
 #define MV_WIN_USB_MAX 4
 
-#defineMV_WIN_USB3_CTRL(n) (0x8 * (n))
-#defineMV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4)
+#defineMV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
+#defineMV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
 #defineMV_WIN_USB3_MAX 8
 
 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
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svn commit: r317518 - head/sys/contrib/ena-com

[Zbigniew Bodek]

Author: zbb
Date: Thu Apr 27 19:57:18 2017
New Revision: 317518
URL: https://svnweb.freebsd.org/changeset/base/317518

Log:
  Import Amazon Elastic Network Adapter (ENA) HAL to sys/contrib/
  
  Import from vendor-sys/ena-com/1.1.4.1
  SVN rev.: 317516
  Version: 1.1.4.1
  
  Obtained from: Amazon.com, Inc.

Added:
  head/sys/contrib/ena-com/
 - copied from r317517, vendor-sys/ena-com/1.1.4.1/
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svn commit: r317516 - in vendor-sys/ena-com: . 1.1.4.1 dist

[Zbigniew Bodek]

Author: zbb
Date: Thu Apr 27 19:40:53 2017
New Revision: 317516
URL: https://svnweb.freebsd.org/changeset/base/317516

Log:
  Introduce HAL for Amazon Elastic Network Adapter (ENA)
  
  This commit adds HAL (Hardware Abstraction Layer) code
  for Amazon Elastic Network Adapter (ENA).
  
  Version: 1.1.4.1
  
  Obtained from: Amazon.com, Inc.

Added:
  vendor-sys/ena-com/
  vendor-sys/ena-com/1.1.4.1/
  vendor-sys/ena-com/1.1.4.1/ena_admin_defs.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_com.c   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_com.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_common_defs.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_eth_com.c   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_eth_com.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_eth_io_defs.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_plat.h   (contents, props changed)
  vendor-sys/ena-com/1.1.4.1/ena_regs_defs.h   (contents, props changed)
  vendor-sys/ena-com/dist/
  vendor-sys/ena-com/dist/ena_admin_defs.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_com.c   (contents, props changed)
  vendor-sys/ena-com/dist/ena_com.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_common_defs.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_eth_com.c   (contents, props changed)
  vendor-sys/ena-com/dist/ena_eth_com.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_eth_io_defs.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_plat.h   (contents, props changed)
  vendor-sys/ena-com/dist/ena_regs_defs.h   (contents, props changed)

Added: vendor-sys/ena-com/1.1.4.1/ena_admin_defs.h
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ vendor-sys/ena-com/1.1.4.1/ena_admin_defs.h Thu Apr 27 19:40:53 2017
(r317516)
@@ -0,0 +1,1412 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ENA_ADMIN_H_
+#define _ENA_ADMIN_H_
+
+enum ena_admin_aq_opcode {
+   ENA_ADMIN_CREATE_SQ = 1,
+
+   ENA_ADMIN_DESTROY_SQ= 2,
+
+   ENA_ADMIN_CREATE_CQ = 3,
+
+   ENA_ADMIN_DESTROY_CQ= 4,
+
+   ENA_ADMIN_GET_FEATURE   = 8,
+
+   ENA_ADMIN_SET_FEATURE   = 9,
+
+   ENA_ADMIN_GET_STATS = 11,
+};
+
+enum ena_admin_aq_completion_status {
+   ENA_ADMIN_SUCCESS   = 0,
+
+   ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE   = 1,
+
+   ENA_ADMIN_BAD_OPCODE= 2,
+
+   ENA_ADMIN_UNSUPPORTED_OPCODE= 3,
+
+   ENA_ADMIN_MALFORMED_REQUEST = 4,
+
+   /* Additional status is provided in ACQ entry extended_status */
+   ENA_ADMIN_ILLEGAL_PARAMETER = 5,
+
+   ENA_ADMIN_UNKNOWN_ERROR = 6,
+};
+
+enum ena_admin_aq_feature_id {
+   ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
+
+   ENA_ADMIN_MAX_QUEUES_NUM= 2,
+
+   ENA_ADMIN_HW_HINTS  = 3,
+
+   ENA_ADMIN_RSS_HASH_FUNCTION = 10,
+
+   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG  = 11,
+
+   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG  = 12,
+
+   ENA_ADMIN_MTU   = 14,
+
+   ENA_ADMIN_RSS_HASH_INPUT= 18,
+
+   

svn commit: r317090 - in head/sys/arm/mv: . armada38x

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:39:14 2017
New Revision: 317090
URL: https://svnweb.freebsd.org/changeset/base/317090

Log:
  Optimize Armada38x low-level MBUS settings
  
  Add early init handler, which comprises various internal
  bus optimisations for Armada 38x SoC's. Magic values used
  due to undocumented registers.
  
  Submitted by: Marcin Wojtas ,
Arnaud Ysmal 
  Obtained from: Semihalf, Stormshield
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10219

Modified:
  head/sys/arm/mv/armada38x/armada38x.c
  head/sys/arm/mv/mv_machdep.c
  head/sys/arm/mv/mvreg.h

Modified: head/sys/arm/mv/armada38x/armada38x.c
==
--- head/sys/arm/mv/armada38x/armada38x.c   Tue Apr 18 10:37:08 2017
(r317089)
+++ head/sys/arm/mv/armada38x/armada38x.c   Tue Apr 18 10:39:14 2017
(r317090)
@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
 int armada38x_open_bootrom_win(void);
 int armada38x_scu_enable(void);
 int armada38x_win_set_iosync_barrier(void);
+int armada38x_mbus_optimization(void);
 
 uint32_t
 get_tclk(void)
@@ -115,6 +116,50 @@ armada38x_open_bootrom_win(void)
 }
 
 int
+armada38x_mbus_optimization(void)
+{
+   bus_space_handle_t vaddr_iowind;
+   int rv;
+
+   rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE,
+   MV_MBUS_CTRL_REGS_LEN, 0, _iowind);
+   if (rv != 0)
+   return (rv);
+
+   /*
+* MBUS Units Priority Control Register - Prioritize XOR,
+* PCIe and GbEs (ID=4,6,3,7,8) DRAM access
+* GbE is High and others are Medium.
+*/
+   bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180);
+
+   /*
+* Fabric Units Priority Control Register -
+* Prioritize CPUs requests.
+*/
+   bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A);
+
+   /*
+* MBUS Units Prefetch Control Register -
+* Pre-fetch enable for all IO masters.
+*/
+   bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0x);
+
+   /*
+* Fabric Units Prefetch Control Register -
+* Enable the CPUs Instruction and Data prefetch.
+*/
+   bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303);
+
+   bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN,
+   BUS_SPACE_BARRIER_WRITE);
+
+   bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN);
+
+   return (rv);
+}
+
+int
 armada38x_scu_enable(void)
 {
bus_space_handle_t vaddr_scu;

Modified: head/sys/arm/mv/mv_machdep.c
==
--- head/sys/arm/mv/mv_machdep.cTue Apr 18 10:37:08 2017
(r317089)
+++ head/sys/arm/mv/mv_machdep.cTue Apr 18 10:39:14 2017
(r317090)
@@ -77,6 +77,7 @@ void armadaxp_l2_init(void);
 int armada38x_win_set_iosync_barrier(void);
 int armada38x_scu_enable(void);
 int armada38x_open_bootrom_win(void);
+int armada38x_mbus_optimization(void);
 #endif
 
 #define MPP_PIN_MAX68
@@ -259,6 +260,8 @@ platform_late_init(void)
/* Set IO Sync Barrier bit for all Mbus devices */
if (armada38x_win_set_iosync_barrier() != 0)
printf("WARNING: could not map CPU Subsystem registers\n");
+   if (armada38x_mbus_optimization() != 0)
+   printf("WARNING: could not enable mbus optimization\n");
if (armada38x_scu_enable() != 0)
printf("WARNING: could not enable SCU\n");
 #ifdef SMP

Modified: head/sys/arm/mv/mvreg.h
==
--- head/sys/arm/mv/mvreg.h Tue Apr 18 10:37:08 2017(r317089)
+++ head/sys/arm/mv/mvreg.h Tue Apr 18 10:39:14 2017(r317090)
@@ -447,4 +447,9 @@
 #defineCPU_RESET_ASSERT0x1
 #endif
 
+#if defined(SOC_MV_ARMADA38X)
+#defineMV_MBUS_CTRL_BASE   (MV_BASE + 0x20420)
+#defineMV_MBUS_CTRL_REGS_LEN   0x10
+#endif
+
 #endif /* _MVREG_H_ */
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svn commit: r317089 - head/sys/arm/include

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:37:08 2017
New Revision: 317089
URL: https://svnweb.freebsd.org/changeset/base/317089

Log:
  Fix bit assignment in PL310_POWER_CTRL
  
  Align to ARM specification:
  
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246f/BEIEHICF.html
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: meloun-miracle-cz
  Differential revision: https://reviews.freebsd.org/D10223

Modified:
  head/sys/arm/include/pl310.h

Modified: head/sys/arm/include/pl310.h
==
--- head/sys/arm/include/pl310.hTue Apr 18 10:35:30 2017
(r317088)
+++ head/sys/arm/include/pl310.hTue Apr 18 10:37:08 2017
(r317089)
@@ -134,8 +134,8 @@
 #definePREFETCH_CTRL_INSTR_PREFETCH(1 << 29)
 #definePREFETCH_CTRL_DL(1 << 30)
 #define PL310_POWER_CTRL   0xF80
-#definePOWER_CTRL_ENABLE_GATING(1 << 0)
-#definePOWER_CTRL_ENABLE_STANDBY   (1 << 1)
+#definePOWER_CTRL_ENABLE_GATING(1 << 1)
+#definePOWER_CTRL_ENABLE_STANDBY   (1 << 0)
 
 struct intr_config_hook;
 
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svn commit: r317088 - head/sys/arm/conf

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:35:30 2017
New Revision: 317088
URL: https://svnweb.freebsd.org/changeset/base/317088

Log:
  Add PL310 device in ARMADA38X config
  
  Submitted by: Arnaud Ysmal 
  Obtained from: Stormshield
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10222

Modified:
  head/sys/arm/conf/ARMADA38X

Modified: head/sys/arm/conf/ARMADA38X
==
--- head/sys/arm/conf/ARMADA38X Tue Apr 18 10:34:10 2017(r317087)
+++ head/sys/arm/conf/ARMADA38X Tue Apr 18 10:35:30 2017(r317088)
@@ -75,6 +75,9 @@ devicecesa
 device crypto
 device cryptodev
 
+# L2 Cache
+device pl310
+
 #FDT
 optionsFDT
 optionsFDT_DTB_STATIC
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svn commit: r317087 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:34:10 2017
New Revision: 317087
URL: https://svnweb.freebsd.org/changeset/base/317087

Log:
  Execute PL310_ERRATA_727915 only for related revisions
  
  Part of PL310 erratum 727915 in pl310_wbinv_range() was
  executed uncoditionally for all possible controllers'
  revisions. This patch adds appropriate condition, since
  extra operations are required only for revisions between
  r2p0 and r3p0.
  
  Submitted by: Marcin Wojtas 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: meloun-miracle-cz
  Differential revision: https://reviews.freebsd.org/D10221

Modified:
  head/sys/arm/arm/pl310.c

Modified: head/sys/arm/arm/pl310.c
==
--- head/sys/arm/arm/pl310.cTue Apr 18 10:32:21 2017(r317086)
+++ head/sys/arm/arm/pl310.cTue Apr 18 10:34:10 2017(r317087)
@@ -272,7 +272,9 @@ pl310_wbinv_range(vm_paddr_t start, vm_s
 
 
 #ifdef PL310_ERRATA_727915
-   platform_pl310_write_debug(pl310_softc, 3);
+   if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
+   pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
+   platform_pl310_write_debug(pl310_softc, 3);
 #endif
while (size > 0) {
 #ifdef PL310_ERRATA_588369
@@ -293,7 +295,9 @@ pl310_wbinv_range(vm_paddr_t start, vm_s
size -= g_l2cache_line_size;
}
 #ifdef PL310_ERRATA_727915
-   platform_pl310_write_debug(pl310_softc, 0);
+   if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 &&
+   pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1)
+   platform_pl310_write_debug(pl310_softc, 0);
 #endif
 
pl310_cache_sync();
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svn commit: r317086 - head/sys/arm/mv/armada38x

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:32:21 2017
New Revision: 317086
URL: https://svnweb.freebsd.org/changeset/base/317086

Log:
  Add PL310 platform initialization for Armada 38x
  
  Introduce machine-dependent part of the arm/pl310 driver for
  Armada 38x SoCs. Add prefetch and power savings configuration.
  
  Submitted by: 
  Obtained from: Stormshield
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10220

Added:
  head/sys/arm/mv/armada38x/armada38x_pl310.c   (contents, props changed)
Modified:
  head/sys/arm/mv/armada38x/files.armada38x

Added: head/sys/arm/mv/armada38x/armada38x_pl310.c
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/arm/mv/armada38x/armada38x_pl310.c Tue Apr 18 10:32:21 2017
(r317086)
@@ -0,0 +1,74 @@
+/*-
+ * Copyright (c) 2017 Stormshield.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+__FBSDID("$FreeBSD$");
+
+/*
+ * The machine-dependent part of the arm/pl310 driver for Armada 38x SoCs.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+void
+platform_pl310_init(struct pl310_softc *sc)
+{
+   uint32_t reg;
+
+   /*
+* Enable power saving modes:
+*  - Dynamic Gating stops the clock when the controller is idle.
+*/
+   reg = pl310_read4(sc, PL310_POWER_CTRL);
+   reg |= POWER_CTRL_ENABLE_GATING;
+   pl310_write4(sc, PL310_POWER_CTRL, reg);
+
+   pl310_write4(sc, PL310_PREFETCH_CTRL, PREFETCH_CTRL_DL |
+   PREFETCH_CTRL_DATA_PREFETCH | PREFETCH_CTRL_INCR_DL |
+   PREFETCH_CTRL_DL_ON_WRAP);
+}
+
+void
+platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val)
+{
+
+   pl310_write4(sc, PL310_CTRL, val);
+}
+
+void
+platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val)
+{
+
+   pl310_write4(sc, PL310_DEBUG_CTRL, val);
+}

Modified: head/sys/arm/mv/armada38x/files.armada38x
==
--- head/sys/arm/mv/armada38x/files.armada38x   Tue Apr 18 10:25:59 2017
(r317085)
+++ head/sys/arm/mv/armada38x/files.armada38x   Tue Apr 18 10:32:21 2017
(r317086)
@@ -7,3 +7,4 @@ arm/mv/armada38x/armada38x.cstandard
 arm/mv/armada38x/armada38x_mp.coptional smp
 arm/mv/armada38x/pmsu.cstandard
 arm/mv/armada38x/rtc.c standard
+arm/mv/armada38x/armada38x_pl310.c optional pl310
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svn commit: r317085 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:25:59 2017
New Revision: 317085
URL: https://svnweb.freebsd.org/changeset/base/317085

Log:
  Increase number of L2 tables required for kernel bootstrap
  
  Memory space reserved for pmap_kernel_l2dtable_kva and
  pmap_kernel_l2ptp_kva has not been taken into account in
  original code. All the memory reserved from kernel space by
  pmap_alloc_specials() function called in pmap_bootstrap()
  should be mapped initially by initarm(). To create initial
  mapping initarm() function reserves proper number of l2 page
  tables. However the number of the l2 page tables does not take
  into account memory for: pmap_kernel_l2ptp_kva,
  pmap_kernel_l2dtable_kva, crashdumpmap, etc.
  
  Submitted by: Grzegorz Bernacki 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Reviewed by: meloun-miracle-cz
  Differential revision: https://reviews.freebsd.org/D10217

Modified:
  head/sys/arm/arm/machdep.c

Modified: head/sys/arm/arm/machdep.c
==
--- head/sys/arm/arm/machdep.c  Tue Apr 18 10:20:42 2017(r317084)
+++ head/sys/arm/arm/machdep.c  Tue Apr 18 10:25:59 2017(r317085)
@@ -814,9 +814,10 @@ initarm(struct arm_boot_params *abp)
 
/*
 * Add one table for end of kernel map, one for stacks, msgbuf and
-* L1 and L2 tables map and one for vectors map.
+* L1 and L2 tables map,  one for vectors map and two for
+* l2 structures from pmap_bootstrap.
 */
-   l2size += 3;
+   l2size += 5;
 
/* Make it divisible by 4 */
l2size = (l2size + 3) & ~3;
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svn commit: r317084 - head/sys/arm/conf

[Zbigniew Bodek]

Author: zbb
Date: Tue Apr 18 10:20:42 2017
New Revision: 317084
URL: https://svnweb.freebsd.org/changeset/base/317084

Log:
  Reduce kmem_arena maximum size for Armada38x
  
  VM_KMEM_SIZE_MAX allows to limit kmem arena size. In our case this was
  necessary, as decreasing size of kmem_arena leaves more space for
  kernel_arena.
  
  kernel_arena is pool used for contigmalloc (in effect, DMA) allocations,
  which failed on Armada38x. This resulted in 'no memory errors'
  (e.g. USB_ERR_NOMEM errors) and failure of whole system. The need for
  greater size of kernel_arena probably comes from more peripherals making
  use of busdma.
  
  Value used as upper limit is half of the default value
  (0x1399a000).
  
  Submitted by: Wojciech Macek 
  Obtained from: Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D10216

Modified:
  head/sys/arm/conf/ARMADA38X

Modified: head/sys/arm/conf/ARMADA38X
==
--- head/sys/arm/conf/ARMADA38X Tue Apr 18 09:27:26 2017(r317083)
+++ head/sys/arm/conf/ARMADA38X Tue Apr 18 10:20:42 2017(r317084)
@@ -21,6 +21,8 @@ options   ROOTDEVNAME=\"/dev/da0s1a\"
 optionsSCHED_ULE   # ULE scheduler
 optionsSMP
 
+optionsVM_KMEM_SIZE_MAX=0x9CCD000
+
 # Pseudo devices
 device random
 device pty
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svn commit: r316336 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Fri Mar 31 18:04:34 2017
New Revision: 316336
URL: https://svnweb.freebsd.org/changeset/base/316336

Log:
  Rework BGX detection to support both new and old firmware
  
  Improve existing BGX detection and adjust it to support both
  new and older ThunderX firmwares. Match BGX FDT nodes by name
  and reg. Match PHY instances by qlm-mode and name.
  Tested on Firmware Version: 2016-09-30 09:12:11
  
  Obtained from:Semihalf
  Differential Revision:https://reviews.freebsd.org/D9863

Modified:
  head/sys/dev/vnic/thunder_bgx_fdt.c

Modified: head/sys/dev/vnic/thunder_bgx_fdt.c
==
--- head/sys/dev/vnic/thunder_bgx_fdt.c Fri Mar 31 15:46:47 2017
(r316335)
+++ head/sys/dev/vnic/thunder_bgx_fdt.c Fri Mar 31 18:04:34 2017
(r316336)
@@ -64,6 +64,8 @@ __FBSDID("$FreeBSD$");
 
 #defineBGX_NODE_NAME   "bgx"
 #defineBGX_MAXID   9
+/* BGX func. 0, i.e.: reg = <0x8000 0 0 0 0>; DEVFN = 0x80 */
+#defineBGX_DEVFN_0 0x80
 
 #defineFDT_NAME_MAXLEN 31
 
@@ -82,57 +84,136 @@ bgx_fdt_get_macaddr(phandle_t phy, uint8
 }
 
 static boolean_t
-bgx_fdt_phy_mode_match(struct bgx *bgx, char *qlm_mode, size_t size)
+bgx_fdt_phy_mode_match(struct bgx *bgx, char *qlm_mode, ssize_t size)
 {
-
-   size -= CONN_TYPE_OFFSET;
+   const char *type;
+   ssize_t sz;
+   ssize_t offset;
 
switch (bgx->qlm_mode) {
case QLM_MODE_SGMII:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "sgmii", size) == 0)
-   return (TRUE);
+   type = "sgmii";
+   sz = sizeof("sgmii") - 1;
+   offset = size - sz;
break;
case QLM_MODE_XAUI_1X4:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "xaui", size) == 0)
-   return (TRUE);
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "dxaui", size) == 0)
+   type = "xaui";
+   sz = sizeof("xaui") - 1;
+   offset = size - sz;
+   if (offset < 0)
+   return (FALSE);
+   if (strncmp(_mode[offset], type, sz) == 0)
return (TRUE);
+   type = "dxaui";
+   sz = sizeof("dxaui") - 1;
+   offset = size - sz;
break;
case QLM_MODE_RXAUI_2X2:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "raui", size) == 0)
-   return (TRUE);
+   type = "raui";
+   sz = sizeof("raui") - 1;
+   offset = size - sz;
break;
case QLM_MODE_XFI_4X1:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "xfi", size) == 0)
-   return (TRUE);
+   type = "xfi";
+   sz = sizeof("xfi") - 1;
+   offset = size - sz;
break;
case QLM_MODE_XLAUI_1X4:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "xlaui", size) == 0)
-   return (TRUE);
+   type = "xlaui";
+   sz = sizeof("xlaui") - 1;
+   offset = size - sz;
break;
case QLM_MODE_10G_KR_4X1:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "xfi-10g-kr", size) == 
0)
-   return (TRUE);
+   type = "xfi-10g-kr";
+   sz = sizeof("xfi-10g-kr") - 1;
+   offset = size - sz;
break;
case QLM_MODE_40G_KR4_1X4:
-   if (strncmp(_mode[CONN_TYPE_OFFSET], "xlaui-40g-kr", size) 
== 0)
+   type = "xlaui-40g-kr";
+   sz = sizeof("xlaui-40g-kr") - 1;
+   offset = size - sz;
+   break;
+   default:
+   return (FALSE);
+   }
+
+   if (offset < 0)
+   return (FALSE);
+
+   if (strncmp(_mode[offset], type, sz) == 0)
+   return (TRUE);
+
+   return (FALSE);
+}
+
+static boolean_t
+bgx_fdt_phy_name_match(struct bgx *bgx, char *phy_name, ssize_t size)
+{
+   const char *type;
+   ssize_t sz;
+
+   switch (bgx->qlm_mode) {
+   case QLM_MODE_SGMII:
+   type = "sgmii";
+   sz = sizeof("sgmii") - 1;
+   break;
+   case QLM_MODE_XAUI_1X4:
+   type = "xaui";
+   sz = sizeof("xaui") - 1;
+   if (sz < size)
+   return (FALSE);
+   if (strncmp(phy_name, type, sz) == 0)
return (TRUE);
+   type = "dxaui";
+   sz = sizeof("dxaui") - 1;
+   break;
+   case QLM_MODE_RXAUI_2X2:
+   type = "raui";
+   sz = sizeof("raui") - 1;
+   break;
+   case QLM_MODE_XFI_4X1:
+   type = "xfi";
+   sz = sizeof("xfi") - 1;
+   break;
+   case QLM_MODE_XLAUI_1X4:
+   

svn commit: r311455 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:27:50 2017
New Revision: 311455
URL: https://svnweb.freebsd.org/changeset/base/311455

Log:
  Add DTS file for Armada 385 DB-AP board
  
  Armada38x is already supported in the tree.
  This commit adds support for DB-AP board.
  File was taken from Linux v4.8 and accustomed to FreeBSD
  in minimal possible way.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D7327

Added:
  head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts   (contents, props changed)

Added: head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/armada-385-db-ap.dts  Thu Jan  5 17:27:50 
2017(r311455)
@@ -0,0 +1,271 @@
+/*
+ * Device Tree file for Marvell Armada 385 Access Point Development board
+ * (DB-88F6820-AP)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Nadav Haklai 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+#include 
+
+/ {
+   model = "Marvell Armada 385 Access Point Development Board";
+   compatible = "marvell,a385-db-ap", "marvell,armada385", 
"marvell,armada380";
+
+   chosen {
+   stdout-path = "serial1";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x 0x8000>; /* 2GB */
+   };
+
+   soc {
+   ranges = ;
+
+   internal-regs {
+   i2c0: i2c@11000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+
+   /*
+* This bus is wired to two EEPROM
+* sockets, one of which holding the
+* board ID used by the bootloader.
+* Erasing this EEPROM's content will
+* brick the board.
+* Use this bus with caution.
+*/
+   };
+
+   mdio@72004 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+
+   phy0: ethernet-phy@1 {
+   reg = <1>;
+   };
+
+   phy1: ethernet-phy@4 {
+   reg = <4>;
+   };
+
+   phy2: ethernet-phy@6 {
+   reg = <6>;
+   };
+   };
+
+   /* UART0 is exposed through the JP8 connector */
+   uart0: serial@12000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   status = "okay";
+   };
+
+   /*
+* UART1 is exposed through a FTDI chip
+  

svn commit: r311454 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:25:16 2017
New Revision: 311454
URL: https://svnweb.freebsd.org/changeset/base/311454

Log:
  Add DTS file for Solidrun ClearFog board
  
  ClearFog is equipped with Marvell Armada 388 SoC, which is already
  supported in FreeBSD.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D7326

Added:
  head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts   (contents, props changed)
  head/sys/boot/fdt/dts/arm/armada-38x-solidrun-microsom.dtsi   (contents, 
props changed)

Added: head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts
==
--- /dev/null   00:00:00 1970   (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/armada-388-clearfog.dts   Thu Jan  5 17:25:16 
2017(r311454)
@@ -0,0 +1,463 @@
+/*
+ * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
+ *
+ *  Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board.  Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include "armada-38x-solidrun-microsom.dtsi"
+
+/ {
+   model = "SolidRun Clearfog A1";
+   compatible = "solidrun,clearfog-a1", "marvell,armada388",
+   "marvell,armada385", "marvell,armada380";
+
+   aliases {
+   /* So that mvebu u-boot can update the MAC addresses */
+   ethernet1 = 
+   ethernet2 = 
+   ethernet3 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   reg_3p3v: regulator-3p3v {
+   compatible = "regulator-fixed";
+   regulator-name = "3P3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   soc {
+   internal-regs {
+   ethernet@3 {
+   phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
+   bm,pool-short = <1>;
+   status = "okay";
+
+   fixed-link {
+   speed = <1000>;
+   full-duplex;
+   };
+   };
+
+   ethernet@34000 {
+   phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
+   bm,pool-short = <1>;
+   status = "okay";
+
+   fixed-link {
+   speed = <1000>;
+

svn commit: r311451 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:14:56 2017
New Revision: 311451
URL: https://svnweb.freebsd.org/changeset/base/311451

Log:
  Correct CESA node in armada-38x.dtsi
  
  CESA resources were invalid, what caused driver to fail
  during attach call.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D8180

Modified:
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jan  5 17:12:53 2017
(r311450)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jan  5 17:14:56 2017
(r311451)
@@ -154,7 +154,8 @@
 
crypto@9 {
compatible = "mrvl,cesa";
-   reg = <0x9 0x1>;
+   reg = <0x9 0x1000   /* tdma base reg chan 0 
*/
+  0x9D000 0x1000>; /* cesa base reg chan 0 
*/
interrupts = ;
interrupt-parent = <>;
sram-handle = <>;
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svn commit: r311450 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:12:53 2017
New Revision: 311450
URL: https://svnweb.freebsd.org/changeset/base/311450

Log:
  Add buffer management entries to armada-38x.dtsi
  
  Hardware buffer management entries are not used yet by FreeBSD.
  They were added for compliance with Linux Armada 38x device tree
  representation and will be used in future network support.
  
  Submitted by:  Bartosz Szczepanek 
  Obtained from: Semihalf
  Sponsored by:  Stormshield
  Differential revision: https://reviews.freebsd.org/D8179

Modified:
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi

Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jan  5 17:10:52 2017
(r311449)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jan  5 17:12:53 2017
(r311450)
@@ -562,6 +562,14 @@
status = "disabled";
};
 
+   bm: bm@c8000 {
+   compatible = "marvell,armada-380-neta-bm";
+   reg = <0xc8000 0xac>;
+   clocks = < 13>;
+   internal-mem = <_bppi>;
+   status = "disabled";
+   };
+
sata@e {
compatible = "marvell,armada-380-ahci";
reg = <0xe 0x2000>;
@@ -622,6 +630,17 @@
status = "disabled";
};
};
+
+   bm_bppi: bm-bppi {
+   compatible = "mmio-sram";
+   reg = ;
+   ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < 13>;
+   no-memory-wc;
+   status = "disabled";
+   };
};
 
pci0: pcie@f108 {
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svn commit: r311449 - in head/sys: arm/conf conf

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:10:52 2017
New Revision: 311449
URL: https://svnweb.freebsd.org/changeset/base/311449

Log:
  Include e6000sw driver in ARMADA38X configuration
  
  e6000sw Marvell switch driver was added to files
  and Armada38x kernel configuration file.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D8178

Modified:
  head/sys/arm/conf/ARMADA38X
  head/sys/conf/files

Modified: head/sys/arm/conf/ARMADA38X
==
--- head/sys/arm/conf/ARMADA38X Thu Jan  5 17:08:10 2017(r311448)
+++ head/sys/arm/conf/ARMADA38X Thu Jan  5 17:10:52 2017(r311449)
@@ -37,6 +37,9 @@ devicevlan
 device mii
 device bpf
 device re
+device mdio
+device etherswitch
+device e6000sw
 
 # PCI
 device pci

Modified: head/sys/conf/files
==
--- head/sys/conf/files Thu Jan  5 17:08:10 2017(r311448)
+++ head/sys/conf/files Thu Jan  5 17:10:52 2017(r311449)
@@ -1639,6 +1639,7 @@ dev/etherswitch/ip17x/ip17x_phy.c option
 dev/etherswitch/ip17x/ip17x_vlans.coptional ip17x
 dev/etherswitch/miiproxy.c optional miiproxy
 dev/etherswitch/rtl8366/rtl8366rb.coptional rtl8366rb
+dev/etherswitch/e6000sw/e6000sw.c  optional e6000sw
 dev/etherswitch/ukswitch/ukswitch.coptional ukswitch
 dev/evdev/cdev.c   optional evdev
 dev/evdev/evdev.c  optional evdev
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svn commit: r311448 - head/sys/dev/etherswitch/e6000sw

[Zbigniew Bodek]

Author: zbb
Date: Thu Jan  5 17:08:10 2017
New Revision: 311448
URL: https://svnweb.freebsd.org/changeset/base/311448

Log:
  Improve ports handling in e6000sw driver
  
  - recognize ports and vlangroups based on DTS file
  - support multi-chip addresing mode (required in upcoming
Armada-388-Clearfog support)
  - refactor attachment function
  
  Each port in 'dsa' node should have 'vlangroup' property. Otherwise,
  e6000sw will fail to attach.
  
  Submitted by: Bartosz Szczepanek 
Konrad Adamczyk 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision: https://reviews.freebsd.org/D7328

Modified:
  head/sys/dev/etherswitch/e6000sw/e6000sw.c
  head/sys/dev/etherswitch/e6000sw/e6000swreg.h

Modified: head/sys/dev/etherswitch/e6000sw/e6000sw.c
==
--- head/sys/dev/etherswitch/e6000sw/e6000sw.c  Thu Jan  5 17:03:35 2017
(r311447)
+++ head/sys/dev/etherswitch/e6000sw/e6000sw.c  Thu Jan  5 17:08:10 2017
(r311448)
@@ -59,6 +59,10 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 
+#include 
+#include 
+#include 
+
 #include "e6000swreg.h"
 #include "etherswitch_if.h"
 #include "miibus_if.h"
@@ -78,23 +82,28 @@ MALLOC_DEFINE(M_E6000SW, "e6000sw", "e60
 
 typedef struct e6000sw_softc {
device_tdev;
+   phandle_t   node;
 
struct sx   sx;
-   struct ifnet*ifp[E6000SW_NUM_PHYS];
-   char*ifname[E6000SW_NUM_PHYS];
-   device_tmiibus[E6000SW_NUM_PHYS];
-   struct mii_data *mii[E6000SW_NUM_PHYS];
+   struct ifnet*ifp[E6000SW_MAX_PORTS];
+   char*ifname[E6000SW_MAX_PORTS];
+   device_tmiibus[E6000SW_MAX_PORTS];
+   struct mii_data *mii[E6000SW_MAX_PORTS];
struct callout  tick_callout;
 
uint32_tcpuports_mask;
+   uint32_tfixed_mask;
+   int sw_addr;
+   int num_ports;
+   boolean_t   multi_chip;
 
int vid[E6000SW_NUM_VGROUPS];
int members[E6000SW_NUM_VGROUPS];
-   int vgroup[E6000SW_NUM_PORTS];
+   int vgroup[E6000SW_MAX_PORTS];
 } e6000sw_softc_t;
 
 static etherswitch_info_t etherswitch_info = {
-   .es_nports =E6000SW_NUM_PORTS,
+   .es_nports =0,
.es_nvlangroups =   E6000SW_NUM_VGROUPS,
.es_name =  "Marvell 6000 series switch"
 };
@@ -134,7 +143,9 @@ static int e6000sw_atu_mac_table(device_
 atu_opt *atu, int flag);
 static int e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid);
 static int e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid);
-static __inline int e6000sw_cpuport(e6000sw_softc_t *sc, int port);
+static __inline int e6000sw_is_cpuport(e6000sw_softc_t *sc, int port);
+static __inline int e6000sw_is_fixedport(e6000sw_softc_t *sc, int port);
+static __inline int e6000sw_is_phyport(e6000sw_softc_t *sc, int port);
 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *sc,
 unsigned int phy);
 
@@ -181,6 +192,14 @@ DRIVER_MODULE(etherswitch, e6000sw, ethe
 DRIVER_MODULE(miibus, e6000sw, miibus_driver, miibus_devclass, 0, 0);
 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1);
 
+#define SMI_CMD 0
+#define SMI_CMD_BUSY   (1<<15)
+#define SMI_CMD_OP_READ((2<<10)|SMI_CMD_BUSY|(1<<12))
+#define SMI_CMD_OP_WRITE   ((1<<10)|SMI_CMD_BUSY|(1<<12))
+#define SMI_DATA   1
+
+#define MDIO_READ(dev, addr, reg) MDIO_READREG(device_get_parent(dev), (addr), 
(reg))
+#define MDIO_WRITE(dev, addr, reg, val) MDIO_WRITEREG(device_get_parent(dev), 
(addr), (reg), (val))
 static void
 e6000sw_identify(driver_t *driver, device_t parent)
 {
@@ -195,10 +214,37 @@ e6000sw_probe(device_t dev)
e6000sw_softc_t *sc;
const char *description;
unsigned int id;
+   uint16_t dev_addr;
+   phandle_t dsa_node, switch_node;
+
+   dsa_node = fdt_find_compatible(OF_finddevice("/"),
+   "marvell,dsa", 0);
+   switch_node = OF_child(dsa_node);
+
+   if (switch_node == 0)
+   return (ENXIO);
 
sc = device_get_softc(dev);
bzero(sc, sizeof(e6000sw_softc_t));
sc->dev = dev;
+   sc->node = switch_node;
+
+   /* Read ADDR[4:1]n using indirect access */
+   MDIO_WRITE(dev, REG_GLOBAL2, SCR_AND_MISC_REG,
+   SCR_AND_MISC_PTR_CFG);
+   dev_addr = MDIO_READ(dev, REG_GLOBAL2, SCR_AND_MISC_REG) &
+   SCR_AND_MISC_DATA_CFG_MASK;
+   if (dev_addr != 0) {
+   sc->multi_chip = true;
+   device_printf(dev, "multi-chip addresing mode\n");
+   } else {
+   device_printf(dev, "single-chip addressing 

Re: svn commit: r307072 - in head/usr.sbin: . efivar

[Zbigniew Bodek]

Hello Warner,

Did you try to build world for ARMv6 on HEAD? I'm not able to do so and the
issues seems to be related to this commit (missing efivar.h file).

Kind regards
zbb

2016-10-12 0:31 GMT+02:00 Warner Losh :

> Author: imp
> Date: Tue Oct 11 22:31:45 2016
> New Revision: 307072
> URL: https://svnweb.freebsd.org/changeset/base/307072
>
> Log:
>   Add efivar(1) to manipulate EFI variables. It uses a similar command
>   line interface to the Linux program, as well as adding a number of
>   useful features to make using it in shell scripts easier (since we
>   don't have a filesystem to fall back on interacting with).
>
>   Differential Revision: https://reviews.freebsd.org/D8128
>   Reviewed by: kib@, wblock@, Ganael Laplanche
>
> Added:
>   head/usr.sbin/efivar/
>   head/usr.sbin/efivar/Makefile   (contents, props changed)
>   head/usr.sbin/efivar/efivar.8   (contents, props changed)
>   head/usr.sbin/efivar/efivar.c   (contents, props changed)
> Modified:
>   head/usr.sbin/Makefile
>
> Modified: head/usr.sbin/Makefile
> 
> ==
> --- head/usr.sbin/Makefile  Tue Oct 11 22:30:41 2016(r307071)
> +++ head/usr.sbin/Makefile  Tue Oct 11 22:31:45 2016(r307072)
> @@ -123,6 +123,7 @@ SUBDIR.${MK_BSNMP}+=bsnmpd
>  SUBDIR.${MK_CTM}+= ctm
>  SUBDIR.${MK_DIALOG}+=  tzsetup
>  SUBDIR.${MK_DIALOG}+=  bsdconfig
> +SUBDIR.${MK_EFI}+= efivar
>  SUBDIR.${MK_FLOPPY}+=  fdcontrol
>  SUBDIR.${MK_FLOPPY}+=  fdformat
>  SUBDIR.${MK_FLOPPY}+=  fdread
>
> Added: head/usr.sbin/efivar/Makefile
> 
> ==
> --- /dev/null   00:00:00 1970   (empty, because file is newly added)
> +++ head/usr.sbin/efivar/Makefile   Tue Oct 11 22:31:45 2016
> (r307072)
> @@ -0,0 +1,8 @@
> +# $FreeBSD$
> +
> +PROG=  efivar
> +MAN=   efivar.8
> +
> +LIBADD= efivar
> +
> +.include 
>
> Added: head/usr.sbin/efivar/efivar.8
> 
> ==
> --- /dev/null   00:00:00 1970   (empty, because file is newly added)
> +++ head/usr.sbin/efivar/efivar.8   Tue Oct 11 22:31:45 2016
> (r307072)
> @@ -0,0 +1,164 @@
> +.\" Copyright (c) 2003 Netflix, Inc
> +.\" All rights reserved.
> +.\"
> +.\" Redistribution and use in source and binary forms, with or without
> +.\" modification, are permitted provided that the following conditions
> +.\" are met:
> +.\" 1. Redistributions of source code must retain the above copyright
> +.\"notice, this list of conditions and the following disclaimer.
> +.\" 2. Redistributions in binary form must reproduce the above copyright
> +.\"notice, this list of conditions and the following disclaimer in the
> +.\"documentation and/or other materials provided with the
> distribution.
> +.\"
> +.\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
> AND
> +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
> PURPOSE
> +.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
> LIABLE
> +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> CONSEQUENTIAL
> +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
> GOODS
> +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
> STRICT
> +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
> WAY
> +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> +.\" SUCH DAMAGE.
> +.\"
> +.\" $FreeBSD$
> +.\"
> +.Dd September 29, 2016
> +.Dt EFIVAR 8
> +.Os
> +.Sh NAME
> +.Nm efivar
> +.Nd UEFI environemnt variable interaction
> +.Sh SYNOPSIS
> +.Nm
> +.Op Fl abdDHlLNpRtw
> +.Op Fl n Ar name
> +.Op Fl f Ar file
> +.Op Fl -append
> +.Op Fl -ascii
> +.Op Fl -attributes
> +.Op Fl -binary
> +.Op Fl -delete
> +.Op Fl -fromfile Ar file
> +.Op Fl -hex
> +.Op Fl -list-guids
> +.Op Fl -list
> +.Op Fl -name Ar name
> +.Op Fl -no-name
> +.Op Fl -print
> +.Op Fl -print-decimal
> +.Op Fl -raw-guid
> +.Op Fl -write
> +.Ar name Ns Op = Ns Ar value
> +.Sh DESCRIPTION
> +This program manages
> +.Dq Unified Extensible Firmware Interface
> +.Pq UEFI
> +environment variables.
> +UEFI variables have three part: A namespace, a name and a value.
> +The namespace is a GUID that's self assigned by the group defining the
> +variables.
> +The name is a Unicode name for the variable.
> +The value is binary data.
> +All Unicode data is presented to the user as UTF-8.
> +.Pp
> +The following options are available:
> +.Bl -tag -width 20m
> +.It Fl n Ar name Fl -name Ar name
> +Specify the name of the variable to operate on.
> +The
> +.Ar name
> +argument is the GUID of variable, followed by a dash, followed by the
> +UEFI variable name.
> +The GUID may be 

svn commit: r301282 - head/sys/dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun  3 18:54:16 2016
New Revision: 301282
URL: https://svnweb.freebsd.org/changeset/base/301282

Log:
  Use proper interface for FDT parsing and memory mapping in CESA
  
  Improvements after r301220.
  Bus space methods are not called so simple pmap_mapdev will suffice.
  Use OF_getencprop to get buffer with already converted endianess.
  
  Pointed out by: ian
  Submitted by:   Michal Stanek 
  Obtained from:  Semihalf

Modified:
  head/sys/dev/cesa/cesa.c
  head/sys/dev/cesa/cesa.h

Modified: head/sys/dev/cesa/cesa.c
==
--- head/sys/dev/cesa/cesa.cFri Jun  3 18:52:57 2016(r301281)
+++ head/sys/dev/cesa/cesa.cFri Jun  3 18:54:16 2016(r301282)
@@ -970,29 +970,30 @@ cesa_setup_sram(struct cesa_softc *sc)
pcell_t sram_handle, sram_reg[2];
int rv;
 
-   rv = OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
+   rv = OF_getencprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
(void *)_handle, sizeof(sram_handle));
if (rv <= 0)
return (rv);
 
sram_ihandle = (ihandle_t)sram_handle;
-   sram_ihandle = fdt32_to_cpu(sram_ihandle);
sram_node = OF_instance_to_package(sram_ihandle);
 
-   rv = OF_getprop(sram_node, "reg", (void *)sram_reg, sizeof(sram_reg));
+   rv = OF_getencprop(sram_node, "reg", (void *)sram_reg, 
sizeof(sram_reg));
if (rv <= 0)
return (rv);
 
-   sc->sc_sram_base_pa = fdt32_to_cpu(sram_reg[0]);
+   sc->sc_sram_base_pa = sram_reg[0];
/* Store SRAM size to be able to unmap in detach() */
-   sc->sc_sram_size = fdt32_to_cpu(sram_reg[1]);
+   sc->sc_sram_size = sram_reg[1];
 
 #if defined(SOC_MV_ARMADA38X)
+   void *sram_va;
+
/* SRAM memory was not mapped in platform_sram_devmap(), map it now */
-   rv = bus_space_map(fdtbus_bs_tag, sc->sc_sram_base_pa, sc->sc_sram_size,
-   0, &(sc->sc_sram_base_va));
-   if (rv != 0)
-   return (rv);
+   sram_va = pmap_mapdev(sc->sc_sram_base_pa, sc->sc_sram_size);
+   if (sram_va == NULL)
+   return (ENOMEM);
+   sc->sc_sram_base_va = (vm_offset_t)sram_va;
 #endif
return (0);
 }
@@ -1246,7 +1247,7 @@ err3:
bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie);
 err2:
 #if defined(SOC_MV_ARMADA38X)
-   bus_space_unmap(fdtbus_bs_tag, sc->sc_sram_base_va, sc->sc_sram_size);
+   pmap_unmapdev(sc->sc_sram_base_va, sc->sc_sram_size);
 #endif
 err1:
bus_release_resources(dev, cesa_res_spec, sc->sc_res);
@@ -1297,7 +1298,7 @@ cesa_detach(device_t dev)
 
 #if defined(SOC_MV_ARMADA38X)
/* Unmap SRAM memory */
-   bus_space_unmap(fdtbus_bs_tag, sc->sc_sram_base_va, sc->sc_sram_size);
+   pmap_unmapdev(sc->sc_sram_base_va, sc->sc_sram_size);
 #endif
/* Destroy mutexes */
mtx_destroy(>sc_sessions_lock);

Modified: head/sys/dev/cesa/cesa.h
==
--- head/sys/dev/cesa/cesa.hFri Jun  3 18:52:57 2016(r301281)
+++ head/sys/dev/cesa/cesa.hFri Jun  3 18:54:16 2016(r301282)
@@ -267,7 +267,7 @@ struct cesa_softc {
 
/* CESA SRAM Address */
bus_addr_t  sc_sram_base_pa;
-   bus_space_handle_t  sc_sram_base_va;
+   vm_offset_t sc_sram_base_va;
bus_size_t  sc_sram_size;
 };
 
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svn commit: r301281 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Fri Jun  3 18:52:57 2016
New Revision: 301281
URL: https://svnweb.freebsd.org/changeset/base/301281

Log:
  Use nitems() macro instead of re-inventing it
  
  Fixed after r301221.
  
  Pointed out by:   oshogbo
  Submitted by: Michal Stanek 
  Obtained from:Semihalf

Modified:
  head/sys/arm/mv/mv_common.c

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Fri Jun  3 18:37:56 2016(r301280)
+++ head/sys/arm/mv/mv_common.c Fri Jun  3 18:52:57 2016(r301281)
@@ -2131,7 +2131,7 @@ moveon:
return (0);
 
t++;
-   if (t >= ((sizeof(cpu_win_tbl))/(sizeof(cpu_win_tbl[0] {
+   if (t >= nitems(cpu_win_tbl)) {
debugf("cannot fit CESA tuple into cpu_win_tbl\n");
return (ENOMEM);
}
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Re: svn commit: r301220 - in head/sys: arm/mv dev/cesa

[Zbigniew Bodek]

2016-06-02 20:48 GMT+02:00 Ian Lepore <i...@freebsd.org>:

> On Thu, 2016-06-02 at 18:31 +, Zbigniew Bodek wrote:
> > Author: zbb
> > Date: Thu Jun  2 18:31:36 2016
> > New Revision: 301220
> > URL: https://svnweb.freebsd.org/changeset/base/301220
> >
> > Log:
> >   Map CESA SRAM memory in driver attach for Armada38x
> >
> >   On other platforms with CESA accelerator the SRAM memory is mapped
> > in
> >   early init before driver is attached. This method only works
> > correctly
> >   with mappings no smaller than L1 section size (1MB). There may be
> > more
> >   SRAM blocks and they may have smaller sizes than 1MB as is the case
> >   for Armada38x. Instead, map SRAM memory with bus_space_map() in
> > CESA
> >   driver attach. Note that we can no longer assume that VA == PA for
> > the
> >   SRAM.
> >
> >   Submitted by:   Michal Stanek <m...@semihalf.com
> >   Obtained from:  Semihalf
> >   Sponsored by:   Stormshield
> >   Differential revision:  https://reviews.freebsd.org/D6215
> > [...]
> > -
> > + rv = OF_getprop(sram_node, "reg", (void *)sram_reg,
> > sizeof(sram_reg));
> > + if (rv <= 0)
> > + return (rv);
> > +
> > + sc->sc_sram_base_pa = fdt32_to_cpu(sram_reg[0]);
> > + /* Store SRAM size to be able to unmap in detach() */
> > + sc->sc_sram_size = fdt32_to_cpu(sram_reg[1]);
> > +
>
> OF_getprop() followed by fdt32_to_cpu() calls is properly spelled
> OF_getencprop() (with no fdt32_to_cpu calls).
>
> > +#if defined(SOC_MV_ARMADA38X)
> > + /* SRAM memory was not mapped in platform_sram_devmap(), map
> > it now */
> > + rv = bus_space_map(fdtbus_bs_tag, sc->sc_sram_base_pa, sc
> > ->sc_sram_size,
> > + 0, &(sc->sc_sram_base_va));
>
> bus_space_map() returns a bus_space_handle_t for use with other
> bus_space functions.  The handle is not necessarily "just the virtual
> address" (although that happens to be the case right now on arm).  I
> don't see any bus_space_x() calls using this handle, that means
> that probably the correct function to use is pmap_mapdev(), not
> bus_space_map().
>
> -- Ian
>
> Thanks Ian,

We will fix this ASAP.
BTW. It would be better to get this review prior to committing the patch
;-)
Phabricator revision didn't attract anyone's attention:
https://reviews.freebsd.org/D6215

Kind regards
zbb
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svn commit: r301225 - in head/sys: arm/conf boot/fdt/dts/arm dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:41:33 2016
New Revision: 301225
URL: https://svnweb.freebsd.org/changeset/base/301225

Log:
  Add support for CESA on Armada38x
  
  Changes:
  - added new SoC ID in CESA attach
  - allowed crypto driver IDs other than 0
  - added CESA nodes to Armada38x .dts files
  - enabled required devices in kernconf
  
  Submitted by: Michal Stanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6220

Modified:
  head/sys/arm/conf/ARMADA38X
  head/sys/boot/fdt/dts/arm/armada-388-gp.dts
  head/sys/boot/fdt/dts/arm/armada-38x.dtsi
  head/sys/dev/cesa/cesa.c

Modified: head/sys/arm/conf/ARMADA38X
==
--- head/sys/arm/conf/ARMADA38X Thu Jun  2 18:39:33 2016(r301224)
+++ head/sys/arm/conf/ARMADA38X Thu Jun  2 18:41:33 2016(r301225)
@@ -81,6 +81,11 @@ device   iic
 device iicbus
 device twsi
 
+# CESA
+device cesa
+device crypto
+device cryptodev
+
 #FDT
 optionsFDT
 optionsFDT_DTB_STATIC

Modified: head/sys/boot/fdt/dts/arm/armada-388-gp.dts
==
--- head/sys/boot/fdt/dts/arm/armada-388-gp.dts Thu Jun  2 18:39:33 2016
(r301224)
+++ head/sys/boot/fdt/dts/arm/armada-388-gp.dts Thu Jun  2 18:41:33 2016
(r301225)
@@ -62,6 +62,13 @@
ranges = ;
 
internal-regs {
+   crypto@9 {
+   status = "okay";
+   };
+   crypto@92000 {
+   status = "okay";
+   };
+
spi@10600 {
pinctrl-names = "default";
pinctrl-0 = <_pins>;

Modified: head/sys/boot/fdt/dts/arm/armada-38x.dtsi
==
--- head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jun  2 18:39:33 2016
(r301224)
+++ head/sys/boot/fdt/dts/arm/armada-38x.dtsi   Thu Jun  2 18:41:33 2016
(r301225)
@@ -63,6 +63,8 @@
gpio1 = 
serial0 = 
serial1 = 
+   sram0 = 
+   sram1 = 
};
 
pmu {
@@ -70,6 +72,16 @@
interrupts-extended = < 3>;
};
 
+   SRAM0: sram@f110 {
+   compatible = "mrvl,cesa-sram";
+   reg = <0xf110 0x001>;
+   };
+
+   SRAM1: sram@f111 {
+   compatible = "mrvl,cesa-sram";
+   reg = <0xf111 0x001>;
+   };
+
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
#address-cells = <2>;
@@ -140,6 +152,25 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x10>;
 
+   crypto@9 {
+   compatible = "mrvl,cesa";
+   reg = <0x9 0x1>;
+   interrupts = ;
+   interrupt-parent = <>;
+   sram-handle = <>;
+   status = "disabled";
+   };
+
+   crypto@92000 {
+   compatible = "mrvl,cesa";
+   reg = <0x92000 0x1000   /* tdma base reg chan 1 
*/
+  0x9F000 0x1000>; /* cesa base reg chan 1 
*/
+   interrupts = ;
+   interrupt-parent = <>;
+   sram-handle = <>;
+   status = "disabled";
+   };
+
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;

Modified: head/sys/dev/cesa/cesa.c
==
--- head/sys/dev/cesa/cesa.cThu Jun  2 18:39:33 2016(r301224)
+++ head/sys/dev/cesa/cesa.cThu Jun  2 18:41:33 2016(r301225)
@@ -1043,6 +1043,7 @@ cesa_attach(device_t dev)
switch (d) {
case MV_DEV_88F6281:
case MV_DEV_88F6282:
+   case MV_DEV_88F6828:
sc->sc_tperr = 0;
break;
case MV_DEV_MV78100:
@@ -1214,7 +1215,7 @@ cesa_attach(device_t dev)
 
/* Register in OCF */
sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
-   if (sc->sc_cid) {
+   if (sc->sc_cid < 0) {
device_printf(dev, "could not get crypto driver id\n");
goto err8;
}

svn commit: r301224 - head/sys/dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:39:33 2016
New Revision: 301224
URL: https://svnweb.freebsd.org/changeset/base/301224

Log:
  Add HMAC-SHA256 support in CESA
  
  Only HMAC-SHA256 is added as it is the only SHA-2 variant supported by
  cryptodev. It is not possible to register hardware support for other
  algorithms in the family including regular non-keyed SHA256.
  
  Submitted by: Michal Stanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6219

Modified:
  head/sys/dev/cesa/cesa.c
  head/sys/dev/cesa/cesa.h

Modified: head/sys/dev/cesa/cesa.c
==
--- head/sys/dev/cesa/cesa.cThu Jun  2 18:37:50 2016(r301223)
+++ head/sys/dev/cesa/cesa.cThu Jun  2 18:39:33 2016(r301224)
@@ -63,6 +63,7 @@ __FBSDID("$FreeBSD$");
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "cryptodev_if.h"
@@ -449,6 +450,7 @@ cesa_set_mkey(struct cesa_session *cs, i
uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN];
uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN];
SHA1_CTX sha1ctx;
+   SHA256_CTX sha256ctx;
MD5_CTX md5ctx;
uint32_t *hout;
uint32_t *hin;
@@ -481,6 +483,14 @@ cesa_set_mkey(struct cesa_session *cs, i
SHA1Update(, opad, SHA1_HMAC_BLOCK_LEN);
memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32));
break;
+   case CRYPTO_SHA2_256_HMAC:
+   SHA256_Init();
+   SHA256_Update(, ipad, SHA2_256_HMAC_BLOCK_LEN);
+   memcpy(hin, sha256ctx.state, sizeof(sha256ctx.state));
+   SHA256_Init();
+   SHA256_Update(, opad, SHA2_256_HMAC_BLOCK_LEN);
+   memcpy(hout, sha256ctx.state, sizeof(sha256ctx.state));
+   break;
default:
return (EINVAL);
}
@@ -541,6 +551,7 @@ cesa_is_hash(int alg)
case CRYPTO_MD5_HMAC:
case CRYPTO_SHA1:
case CRYPTO_SHA1_HMAC:
+   case CRYPTO_SHA2_256_HMAC:
return (1);
default:
return (0);
@@ -942,7 +953,11 @@ cesa_execute(struct cesa_softc *sc)
ctd = STAILQ_FIRST(>cr_tdesc);
 
CESA_TDMA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr);
+#if defined (SOC_MV_ARMADA38X)
+   CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE | CESA_SA_CMD_SHA2);
+#else
CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE);
+#endif
 
CESA_UNLOCK(sc, requests);
 }
@@ -1174,6 +1189,9 @@ cesa_attach(device_t dev)
 */
CESA_TDMA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 |
CESA_TDMA_CR_SBL128 | CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS |
+#if defined (SOC_MV_ARMADA38X)
+   CESA_TDMA_NUM_OUTSTAND |
+#endif
CESA_TDMA_CR_ENABLE);
 
/*
@@ -1208,6 +1226,7 @@ cesa_attach(device_t dev)
crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
+   crypto_register(sc->sc_cid, CRYPTO_SHA2_256_HMAC, 0, 0);
 
return (0);
 err8:
@@ -1478,6 +1497,12 @@ cesa_newsession(device_t dev, uint32_t *
if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN)
cs->cs_config |= CESA_CSHD_96_BIT_HMAC;
break;
+   case CRYPTO_SHA2_256_HMAC:
+   cs->cs_mblen = SHA2_256_HMAC_BLOCK_LEN;
+   cs->cs_hlen = (mac->cri_mlen == 0) ? SHA2_256_HASH_LEN :
+   mac->cri_mlen;
+   cs->cs_config |= CESA_CSHD_SHA2_256_HMAC;
+   break;
default:
error = EINVAL;
break;

Modified: head/sys/dev/cesa/cesa.h
==
--- head/sys/dev/cesa/cesa.hThu Jun  2 18:37:50 2016(r301223)
+++ head/sys/dev/cesa/cesa.hThu Jun  2 18:39:33 2016(r301224)
@@ -74,11 +74,9 @@
 
 /*
  * CESA_MAX_HASH_LEN is maximum length of hash generated by CESA.
- * As CESA suports only MD5 and SHA1 this equals to 20 bytes.
- * However we increase the value to 24 bytes to meet alignment
- * requirements in cesa_sa_data structure.
+ * As CESA supports MD5, SHA1 and SHA-256 this equals to 32 bytes.
  */
-#define CESA_MAX_HASH_LEN  24
+#define CESA_MAX_HASH_LEN  32
 #define CESA_MAX_KEY_LEN   32
 #define CESA_MAX_IV_LEN16
 #define CESA_MAX_HMAC_BLOCK_LEN64
@@ -293,8 +291,10 @@ struct cesa_chain_info {
 
 #define CESA_CSHD_MD5  (4 << 4)
 #define CESA_CSHD_SHA1 (5 << 4)
+#define CESA_CSHD_SHA2_256 (1 << 4)
 #define CESA_CSHD_MD5_HMAC (6 << 4)
 #define CESA_CSHD_SHA1_HMAC(7 << 4)

svn commit: r301223 - head/sys/dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:37:50 2016
New Revision: 301223
URL: https://svnweb.freebsd.org/changeset/base/301223

Log:
  Truncate HMAC output only if requested by the client
  
  The output of HMAC was previously truncated to 12 bytes. This was only
  correct in case of one particular crypto client - the new version of IPSEC.
  Fix by taking into account the cri_mlen field in cryptoini session request
  filled in by the client.
  
  Submitted by: Michal Stanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6218

Modified:
  head/sys/dev/cesa/cesa.c
  head/sys/dev/cesa/cesa.h

Modified: head/sys/dev/cesa/cesa.c
==
--- head/sys/dev/cesa/cesa.cThu Jun  2 18:35:35 2016(r301222)
+++ head/sys/dev/cesa/cesa.cThu Jun  2 18:37:50 2016(r301223)
@@ -1451,24 +1451,32 @@ cesa_newsession(device_t dev, uint32_t *
if (!error && mac) {
switch (mac->cri_alg) {
case CRYPTO_MD5:
-   cs->cs_config |= CESA_CSHD_MD5;
cs->cs_mblen = 1;
-   cs->cs_hlen = MD5_HASH_LEN;
+   cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN :
+   mac->cri_mlen;
+   cs->cs_config |= CESA_CSHD_MD5;
break;
case CRYPTO_MD5_HMAC:
-   cs->cs_config |= CESA_CSHD_MD5_HMAC;
cs->cs_mblen = MD5_HMAC_BLOCK_LEN;
-   cs->cs_hlen = CESA_HMAC_HASH_LENGTH;
+   cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN :
+   mac->cri_mlen;
+   cs->cs_config |= CESA_CSHD_MD5_HMAC;
+   if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN)
+   cs->cs_config |= CESA_CSHD_96_BIT_HMAC;
break;
case CRYPTO_SHA1:
-   cs->cs_config |= CESA_CSHD_SHA1;
cs->cs_mblen = 1;
-   cs->cs_hlen = SHA1_HASH_LEN;
+   cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN :
+   mac->cri_mlen;
+   cs->cs_config |= CESA_CSHD_SHA1;
break;
case CRYPTO_SHA1_HMAC:
-   cs->cs_config |= CESA_CSHD_SHA1_HMAC;
cs->cs_mblen = SHA1_HMAC_BLOCK_LEN;
-   cs->cs_hlen = CESA_HMAC_HASH_LENGTH;
+   cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN :
+   mac->cri_mlen;
+   cs->cs_config |= CESA_CSHD_SHA1_HMAC;
+   if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN)
+   cs->cs_config |= CESA_CSHD_96_BIT_HMAC;
break;
default:
error = EINVAL;

Modified: head/sys/dev/cesa/cesa.h
==
--- head/sys/dev/cesa/cesa.hThu Jun  2 18:35:35 2016(r301222)
+++ head/sys/dev/cesa/cesa.hThu Jun  2 18:37:50 2016(r301223)
@@ -68,7 +68,7 @@
 #define CESA_TDMA_DESCRIPTORS  (CESA_TDMA_DESC_PER_REQ * CESA_REQUESTS)
 
 /* Useful constants */
-#define CESA_HMAC_HASH_LENGTH  12
+#define CESA_HMAC_TRUNC_LEN12
 #define CESA_MAX_FRAGMENTS 64
 #define CESA_SRAM_SIZE 2048
 
@@ -293,8 +293,10 @@ struct cesa_chain_info {
 
 #define CESA_CSHD_MD5  (4 << 4)
 #define CESA_CSHD_SHA1 (5 << 4)
-#define CESA_CSHD_MD5_HMAC ((6 << 4) | (1 << 7))
-#define CESA_CSHD_SHA1_HMAC((7 << 4) | (1 << 7))
+#define CESA_CSHD_MD5_HMAC (6 << 4)
+#define CESA_CSHD_SHA1_HMAC(7 << 4)
+
+#define CESA_CSHD_96_BIT_HMAC  (1 << 7)
 
 #define CESA_CSHD_DES  (1 << 8)
 #define CESA_CSHD_3DES (2 << 8)
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svn commit: r301222 - in head/sys: boot/fdt/dts/arm dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:35:35 2016
New Revision: 301222
URL: https://svnweb.freebsd.org/changeset/base/301222

Log:
  Split CESA memory resource into TDMA and CESA regs
  
  TDMA and CESA registers are placed in different ranges of memory. Split
  memory resource in DTS to reflect that. This change is needed to support
  multiple CESA nodes as otherwise the ranges of different nodes would
  overlap.
  
  In consequence, CESA_WRITE and CESA_READ macros have been split depending
  on which range of registers is accessed. Offsets for CESA registers have
  been modified as the base address has changed.
  
  Submitted by: Michal Stanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6217

Modified:
  head/sys/boot/fdt/dts/arm/db78100.dts
  head/sys/boot/fdt/dts/arm/db88f6281.dts
  head/sys/boot/fdt/dts/arm/dockstar.dts
  head/sys/boot/fdt/dts/arm/dreamplug-1001.dts
  head/sys/boot/fdt/dts/arm/dreamplug-1001N.dts
  head/sys/boot/fdt/dts/arm/sheevaplug.dts
  head/sys/dev/cesa/cesa.c
  head/sys/dev/cesa/cesa.h

Modified: head/sys/boot/fdt/dts/arm/db78100.dts
==
--- head/sys/boot/fdt/dts/arm/db78100.dts   Thu Jun  2 18:33:26 2016
(r301221)
+++ head/sys/boot/fdt/dts/arm/db78100.dts   Thu Jun  2 18:35:35 2016
(r301222)
@@ -283,7 +283,8 @@
 
crypto@9 {
compatible = "mrvl,cesa";
-   reg = <0x9 0x1>;
+   reg = <0x9 0x1000   /* tdma base reg chan 0 */
+  0x9D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <19>;
interrupt-parent = <>;
};

Modified: head/sys/boot/fdt/dts/arm/db88f6281.dts
==
--- head/sys/boot/fdt/dts/arm/db88f6281.dts Thu Jun  2 18:33:26 2016
(r301221)
+++ head/sys/boot/fdt/dts/arm/db88f6281.dts Thu Jun  2 18:35:35 2016
(r301222)
@@ -221,7 +221,8 @@
 
crypto@3 {
compatible = "mrvl,cesa";
-   reg = <0x3 0x1>;
+   reg = <0x3 0x1000   /* tdma base reg chan 0 */
+  0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <>;
 

Modified: head/sys/boot/fdt/dts/arm/dockstar.dts
==
--- head/sys/boot/fdt/dts/arm/dockstar.dts  Thu Jun  2 18:33:26 2016
(r301221)
+++ head/sys/boot/fdt/dts/arm/dockstar.dts  Thu Jun  2 18:35:35 2016
(r301222)
@@ -206,7 +206,8 @@
 
crypto@3 {
compatible = "mrvl,cesa";
-   reg = <0x3 0x1>;
+   reg = <0x3 0x1000   /* tdma base reg chan 0 */
+  0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <>;
 

Modified: head/sys/boot/fdt/dts/arm/dreamplug-1001.dts
==
--- head/sys/boot/fdt/dts/arm/dreamplug-1001.dtsThu Jun  2 18:33:26 
2016(r301221)
+++ head/sys/boot/fdt/dts/arm/dreamplug-1001.dtsThu Jun  2 18:35:35 
2016(r301222)
@@ -270,7 +270,8 @@
 
crypto@3 {
compatible = "mrvl,cesa";
-   reg = <0x3 0x1>;
+   reg = <0x3 0x1000   /* tdma base reg chan 0 */
+  0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <>;
 

Modified: head/sys/boot/fdt/dts/arm/dreamplug-1001N.dts
==
--- head/sys/boot/fdt/dts/arm/dreamplug-1001N.dts   Thu Jun  2 18:33:26 
2016(r301221)
+++ head/sys/boot/fdt/dts/arm/dreamplug-1001N.dts   Thu Jun  2 18:35:35 
2016(r301222)
@@ -291,7 +291,8 @@
 
crypto@3 {
compatible = "mrvl,cesa";
-   reg = <0x3 0x1>;
+   reg = <0x3 0x1000   /* tdma base reg chan 0 */
+  0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <>;
 

Modified: head/sys/boot/fdt/dts/arm/sheevaplug.dts
==
--- head/sys/boot/fdt/dts/arm/sheevaplug.dtsThu Jun  2 18:33:26 2016
(r301221)
+++ head/sys/boot/fdt/dts/arm/sheevaplug.dtsThu Jun  2 18:35:35 

svn commit: r301221 - head/sys/arm/mv

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:33:26 2016
New Revision: 301221
URL: https://svnweb.freebsd.org/changeset/base/301221

Log:
  Configure CPU window to second CESA SRAM
  
  Check if there is a second CESA SRAM node in FDT and add a CPU window
  for it. Define A38X specific macro for setting device attribute for
  each node.
  
  Submitted by: Michal Stanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6216

Modified:
  head/sys/arm/mv/mv_common.c
  head/sys/arm/mv/mvwin.h

Modified: head/sys/arm/mv/mv_common.c
==
--- head/sys/arm/mv/mv_common.c Thu Jun  2 18:31:36 2016(r301220)
+++ head/sys/arm/mv/mv_common.c Thu Jun  2 18:33:26 2016(r301221)
@@ -2107,6 +2107,37 @@ moveon:
return (EINVAL);
 
cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
+#ifdef SOC_MV_ARMADA38X
+   cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);
+#else
+   cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
+#endif
+   cpu_win_tbl[t].base = sram_base;
+   cpu_win_tbl[t].size = sram_size;
+   cpu_win_tbl[t].remap = ~0;
+   cpu_wins_no++;
+   debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
+
+   /* Check if there is a second CESA node */
+   while ((node = OF_peer(node)) != 0) {
+   if (fdt_is_compatible(node, "mrvl,cesa-sram")) {
+   if (fdt_regsize(node, _base, _size) != 0)
+   return (EINVAL);
+   break;
+   }
+   }
+
+   if (node == 0)
+   return (0);
+
+   t++;
+   if (t >= ((sizeof(cpu_win_tbl))/(sizeof(cpu_win_tbl[0] {
+   debugf("cannot fit CESA tuple into cpu_win_tbl\n");
+   return (ENOMEM);
+   }
+
+   /* Configure window for CESA1 */
+   cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;

Modified: head/sys/arm/mv/mvwin.h
==
--- head/sys/arm/mv/mvwin.h Thu Jun  2 18:31:36 2016(r301220)
+++ head/sys/arm/mv/mvwin.h Thu Jun  2 18:33:26 2016(r301221)
@@ -233,6 +233,19 @@
  *  2: engine0
  */
 #define MV_WIN_CESA_ATTR(eng_sel)  (1 | ((eng_sel) << 2))
+#elif defined(SOC_MV_ARMADA38X)
+#define MV_WIN_CESA_TARGET 9
+/*
+ * Bits [1:0] = Data swapping
+ *  0x0 = Byte swap
+ *  0x1 = No swap
+ *  0x2 = Byte and word swap
+ *  0x3 = Word swap
+ * Bits [4:2] = CESA select:
+ *  0x6 = CESA0
+ *  0x5 = CESA1
+ */
+#define MV_WIN_CESA_ATTR(eng_sel)  (0x11 | (1 << (3 - (eng_sel
 #else
 #define MV_WIN_CESA_TARGET 3
 #define MV_WIN_CESA_ATTR(eng_sel)  0
___
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svn commit: r301220 - in head/sys: arm/mv dev/cesa

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:31:36 2016
New Revision: 301220
URL: https://svnweb.freebsd.org/changeset/base/301220

Log:
  Map CESA SRAM memory in driver attach for Armada38x
  
  On other platforms with CESA accelerator the SRAM memory is mapped in
  early init before driver is attached. This method only works correctly
  with mappings no smaller than L1 section size (1MB). There may be more
  SRAM blocks and they may have smaller sizes than 1MB as is the case
  for Armada38x. Instead, map SRAM memory with bus_space_map() in CESA
  driver attach. Note that we can no longer assume that VA == PA for the
  SRAM.
  
  Submitted by: Michal Stanek sc_sram_base + CESA_SRAM_SIZE
+ * ++ <= sc->sc_sram_base_va + CESA_SRAM_SIZE
  * ||
  * |  DATA  |
  * ||
- * ++ <= sc->sc_sram_base + CESA_DATA(0)
+ * ++ <= sc->sc_sram_base_va + CESA_DATA(0)
  * |  struct cesa_sa_data   |
  * ++
  * |  struct cesa_sa_hdesc  |
- * ++ <= sc->sc_sram_base
+ * ++ <= sc->sc_sram_base_va
  */
 
 #include 
@@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -373,7 +374,7 @@ static struct cesa_tdma_desc *
 cesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
 {
 
-   return (cesa_tdma_copy(sc, sc->sc_sram_base +
+   return (cesa_tdma_copy(sc, sc->sc_sram_base_pa +
sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr,
sizeof(struct cesa_sa_data)));
 }
@@ -382,7 +383,7 @@ static struct cesa_tdma_desc *
 cesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
 {
 
-   return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base +
+   return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base_pa +
sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data)));
 }
 
@@ -390,7 +391,7 @@ static struct cesa_tdma_desc *
 cesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd)
 {
 
-   return (cesa_tdma_copy(sc, sc->sc_sram_base, csd->csd_cshd_paddr,
+   return (cesa_tdma_copy(sc, sc->sc_sram_base_pa, csd->csd_cshd_paddr,
sizeof(struct cesa_sa_hdesc)));
 }
 
@@ -566,14 +567,14 @@ cesa_fill_packet(struct cesa_softc *sc, 
bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset);
 
if (bsize > 0) {
-   ctd = cesa_tdma_copy(sc, sc->sc_sram_base +
+   ctd = cesa_tdma_copy(sc, sc->sc_sram_base_pa +
CESA_DATA(cp->cp_offset), seg->ds_addr, bsize);
if (!ctd)
return (-ENOMEM);
 
STAILQ_INSERT_TAIL(>cp_copyin, ctd, ctd_stq);
 
-   ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base +
+   ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base_pa +
CESA_DATA(cp->cp_offset), bsize);
if (!ctd)
return (-ENOMEM);
@@ -950,22 +951,33 @@ cesa_setup_sram(struct cesa_softc *sc)
 {
phandle_t sram_node;
ihandle_t sram_ihandle;
-   pcell_t sram_handle, sram_reg;
+   pcell_t sram_handle, sram_reg[2];
+   int rv;
 
-   if (OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
-   (void *)_handle, sizeof(sram_handle)) <= 0)
-   return (ENXIO);
+   rv = OF_getprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
+   (void *)_handle, sizeof(sram_handle));
+   if (rv <= 0)
+   return (rv);
 
sram_ihandle = (ihandle_t)sram_handle;
sram_ihandle = fdt32_to_cpu(sram_ihandle);
sram_node = OF_instance_to_package(sram_ihandle);
 
-   if 

svn commit: r301218 - head/sys/boot/fdt/dts/arm

[Zbigniew Bodek]

Author: zbb
Date: Thu Jun  2 18:24:00 2016
New Revision: 301218
URL: https://svnweb.freebsd.org/changeset/base/301218

Log:
  Revert part of r294418 ("Correct ranges...")
  
  Commit was temporary fix due to rman_res_t defined as 32-bit u_long.
  After redefining it as 64-bit variable workaround is not needed and
  was removed.
  
  Submitted by: Bartosz Szczepanek 
  Obtained from:Semihalf
  Sponsored by: Stormshield
  Differential revision:https://reviews.freebsd.org/D6214

Modified:
  head/sys/boot/fdt/dts/arm/armada-388-gp.dts

Modified: head/sys/boot/fdt/dts/arm/armada-388-gp.dts
==
--- head/sys/boot/fdt/dts/arm/armada-388-gp.dts Thu Jun  2 17:51:29 2016
(r301217)
+++ head/sys/boot/fdt/dts/arm/armada-388-gp.dts Thu Jun  2 18:24:00 2016
(r301218)
@@ -59,7 +59,7 @@
};
 
soc {
-   ranges = <0 0 0xf100 0x10>;
+   ranges = ;
 
internal-regs {
spi@10600 {
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svn commit: r301112 - head/sys/arm64/arm64

[Zbigniew Bodek]

Author: zbb
Date: Wed Jun  1 08:20:10 2016
New Revision: 301112
URL: https://svnweb.freebsd.org/changeset/base/301112

Log:
  Return real error value instead of hard-coded ENXIO (fix after r300149)
  
  It is possible to return real error value in case of gic_v3_attach()
  failure instead of hard-coded ENXIO.
  
  Obtained from:Semihalf
  Sponsored by: Cavium

Modified:
  head/sys/arm64/arm64/gic_v3_fdt.c

Modified: head/sys/arm64/arm64/gic_v3_fdt.c
==
--- head/sys/arm64/arm64/gic_v3_fdt.c   Wed Jun  1 08:20:07 2016
(r30)
+++ head/sys/arm64/arm64/gic_v3_fdt.c   Wed Jun  1 08:20:10 2016
(r301112)
@@ -141,11 +141,13 @@ gic_v3_fdt_attach(device_t dev)
xref = OF_xref_from_node(ofw_bus_get_node(dev));
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
+   err = ENXIO;
goto error;
}
 
if (intr_pic_claim_root(dev, xref, arm_gic_v3_intr, sc,
GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) {
+   err = ENXIO;
goto error;
}
 #endif
@@ -172,7 +174,7 @@ error:
/* Failure so free resources */
gic_v3_detach(dev);
 
-   return (ENXIO);
+   return (err);
 }
 
 /* OFW bus interface */
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svn commit: r300969 - in head/sys/arm: arm include

[Zbigniew Bodek]

Author: zbb
Date: Sun May 29 17:35:38 2016
New Revision: 300969
URL: https://svnweb.freebsd.org/changeset/base/300969

Log:
  Improve ARM debug_monitor for SMP machines
  
  - Reset debug architecture and enable monitor for secondary
CPUs in init_secondary() rather than when configuring watchpoint, etc.
  - Disable HW debugging capabilities when one of the CPU cores fails
to set up.
  - Use dbg_capable() in a more atomic manner to avoid any mismatch
between CPUs.
  
  Differential Revision: https://reviews.freebsd.org/D6009

Modified:
  head/sys/arm/arm/debug_monitor.c
  head/sys/arm/arm/mp_machdep.c
  head/sys/arm/include/debug_monitor.h

Modified: head/sys/arm/arm/debug_monitor.c
==
--- head/sys/arm/arm/debug_monitor.cSun May 29 17:33:49 2016
(r300968)
+++ head/sys/arm/arm/debug_monitor.cSun May 29 17:35:38 2016
(r300969)
@@ -72,9 +72,8 @@ static boolean_t dbg_check_slot_free(enu
 static int dbg_remove_xpoint(struct dbg_wb_conf *);
 static int dbg_setup_xpoint(struct dbg_wb_conf *);
 
-static boolean_t dbg_capable;  /* Indicates that machine is capable of using
+static int dbg_capable_var;/* Indicates that machine is capable of using
   HW watchpoints/breakpoints */
-static boolean_t dbg_ready[MAXCPU]; /* Debug arch. reset performed on this CPU 
*/
 
 static uint32_t dbg_model; /* Debug Arch. Model */
 static boolean_t dbg_ossr; /* OS Save and Restore implemented */
@@ -245,6 +244,13 @@ dbg_wb_write_reg(int reg, int n, uint32_
isb();
 }
 
+static __inline boolean_t
+dbg_capable(void)
+{
+
+   return (atomic_cmpset_int(_capable_var, 0, 0) == 0);
+}
+
 boolean_t
 kdb_cpu_pc_is_singlestep(db_addr_t pc)
 {
@@ -253,7 +259,7 @@ kdb_cpu_pc_is_singlestep(db_addr_t pc)
 *  there will be no stepping capabilities
 *  (SOFTWARE_SSTEP is not defined for __ARM_ARCH >= 6).
 */
-   if (!dbg_capable)
+   if (!dbg_capable())
return (FALSE);
 
if (dbg_find_slot(DBG_TYPE_BREAKPOINT, pc) != ~0U)
@@ -270,7 +276,7 @@ kdb_cpu_set_singlestep(void)
uint32_t wcr;
u_int i;
 
-   if (!dbg_capable)
+   if (!dbg_capable())
return;
 
/*
@@ -303,7 +309,7 @@ kdb_cpu_clear_singlestep(void)
uint32_t wvr, wcr;
u_int i;
 
-   if (!dbg_capable)
+   if (!dbg_capable())
return;
 
dbg_remove_breakpoint(DBG_BKPT_BT_SLOT);
@@ -423,7 +429,7 @@ dbg_show_watchpoint(void)
boolean_t is_enabled;
int i;
 
-   if (!dbg_capable) {
+   if (!dbg_capable()) {
db_printf("Architecture does not support HW "
"breakpoints/watchpoints\n");
return;
@@ -591,24 +597,15 @@ dbg_setup_xpoint(struct dbg_wb_conf *con
uint32_t cr_size, cr_priv, cr_access;
uint32_t reg_ctrl, reg_addr, ctrl, addr;
boolean_t is_bkpt;
-   u_int cpuid, cpu;
+   u_int cpu;
u_int i;
-   int err;
 
-   if (!dbg_capable)
+   if (!dbg_capable())
return (ENXIO);
 
is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
typestr = is_bkpt ? "breakpoint" : "watchpoint";
 
-   cpuid = PCPU_GET(cpuid);
-   if (!dbg_ready[cpuid]) {
-   err = dbg_reset_state();
-   if (err != 0)
-   return (err);
-   dbg_ready[cpuid] = TRUE;
-   }
-
if (is_bkpt) {
if (dbg_breakpoint_num == 0) {
db_printf("Breakpoints not supported on this 
architecture\n");
@@ -698,7 +695,7 @@ dbg_setup_xpoint(struct dbg_wb_conf *con
d->dbg_wvr[i] = addr;
d->dbg_wcr[i] = ctrl;
/* Skip update command for the current CPU */
-   if (cpu != cpuid)
+   if (cpu != PCPU_GET(cpuid))
pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
}
}
@@ -715,23 +712,13 @@ dbg_remove_xpoint(struct dbg_wb_conf *co
struct dbreg *d;
uint32_t reg_ctrl, reg_addr, addr;
boolean_t is_bkpt;
-   u_int cpuid, cpu;
+   u_int cpu;
u_int i;
-   int err;
 
-   if (!dbg_capable)
+   if (!dbg_capable())
return (ENXIO);
 
is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
-
-   cpuid = PCPU_GET(cpuid);
-   if (!dbg_ready[cpuid]) {
-   err = dbg_reset_state();
-   if (err != 0)
-   return (err);
-   dbg_ready[cpuid] = TRUE;
-   }
-
addr = conf->address;
 
if (is_bkpt) {
@@ -764,7 +751,7 @@ dbg_remove_xpoint(struct dbg_wb_conf *co
d->dbg_wvr[i] = 0;
d->dbg_wcr[i] = 0;
/* Skip update command for the current CPU */
-   

svn commit: r300968 - head/sys/arm/arm

[Zbigniew Bodek]

Author: zbb
Date: Sun May 29 17:33:49 2016
New Revision: 300968
URL: https://svnweb.freebsd.org/changeset/base/300968

Log:
  Fix debug_monitor code for older ARMs (ARM11)
  
  - Enable monitor mode prior to accessing watchpoint
registers for v6, v6.1 architectures.
  - Fix configuration scheme for v6, v6.1 and v7 Debug Archs
  - Enable monitor unconditionally and for good instead
of enabling and disabling it (needed for single stepping
on on v6/v6.1)
  
  Tested on RPI-B and Arndale
  
  Differential Revision: https://reviews.freebsd.org/D6008

Modified:
  head/sys/arm/arm/debug_monitor.c

Modified: head/sys/arm/arm/debug_monitor.c
==
--- head/sys/arm/arm/debug_monitor.cSun May 29 17:32:19 2016
(r300967)
+++ head/sys/arm/arm/debug_monitor.cSun May 29 17:33:49 2016
(r300968)
@@ -82,8 +82,6 @@ static boolean_t dbg_ossr;/* OS Save an
 static uint32_t dbg_watchpoint_num;
 static uint32_t dbg_breakpoint_num;
 
-static int dbg_ref_count_mme; /* Times monitor mode was enabled */
-
 /* ID_DFR0 - Debug Feature Register 0 */
 #defineID_DFR0_CP_DEBUG_M_SHIFT0
 #defineID_DFR0_CP_DEBUG_M_MASK (0xF << 
ID_DFR0_CP_DEBUG_M_SHIFT)
@@ -250,6 +248,13 @@ dbg_wb_write_reg(int reg, int n, uint32_
 boolean_t
 kdb_cpu_pc_is_singlestep(db_addr_t pc)
 {
+   /*
+* XXX: If the platform fails to enable its debug arch.
+*  there will be no stepping capabilities
+*  (SOFTWARE_SSTEP is not defined for __ARM_ARCH >= 6).
+*/
+   if (!dbg_capable)
+   return (FALSE);
 
if (dbg_find_slot(DBG_TYPE_BREAKPOINT, pc) != ~0U)
return (TRUE);
@@ -265,6 +270,9 @@ kdb_cpu_set_singlestep(void)
uint32_t wcr;
u_int i;
 
+   if (!dbg_capable)
+   return;
+
/*
 * Disable watchpoints, e.g. stepping over watched instruction will
 * trigger break exception instead of single-step exception and locks
@@ -295,6 +303,9 @@ kdb_cpu_clear_singlestep(void)
uint32_t wvr, wcr;
u_int i;
 
+   if (!dbg_capable)
+   return;
+
dbg_remove_breakpoint(DBG_BKPT_BT_SLOT);
dbg_remove_breakpoint(DBG_BKPT_BNT_SLOT);
 
@@ -572,34 +583,6 @@ dbg_enable_monitor(void)
 }
 
 static int
-dbg_disable_monitor(void)
-{
-   uint32_t dbg_dscr;
-
-   if (!dbg_monitor_is_enabled())
-   return (0);
-
-   dbg_dscr = cp14_dbgdscrint_get();
-   switch (dbg_model) {
-   case ID_DFR0_CP_DEBUG_M_V6:
-   case ID_DFR0_CP_DEBUG_M_V6_1: /* fall through */
-   dbg_dscr &= ~DBGSCR_MDBG_EN;
-   cp14_dbgdscr_v6_set(dbg_dscr);
-   break;
-   case ID_DFR0_CP_DEBUG_M_V7: /* fall through */
-   case ID_DFR0_CP_DEBUG_M_V7_1:
-   dbg_dscr &= ~DBGSCR_MDBG_EN;
-   cp14_dbgdscr_v7_set(dbg_dscr);
-   break;
-   default:
-   return (ENXIO);
-   }
-   isb();
-
-   return (0);
-}
-
-static int
 dbg_setup_xpoint(struct dbg_wb_conf *conf)
 {
struct pcpu *pcpu;
@@ -702,13 +685,6 @@ dbg_setup_xpoint(struct dbg_wb_conf *con
dbg_wb_write_reg(reg_addr, i, addr);
dbg_wb_write_reg(reg_ctrl, i, ctrl);
 
-   err = dbg_enable_monitor();
-   if (err != 0)
-   return (err);
-
-   /* Increment monitor enable counter */
-   dbg_ref_count_mme++;
-
/*
 * Save watchpoint settings for all CPUs.
 * We don't need to do the same with breakpoints since HW breakpoints
@@ -775,19 +751,6 @@ dbg_remove_xpoint(struct dbg_wb_conf *co
dbg_wb_write_reg(reg_ctrl, i, 0);
dbg_wb_write_reg(reg_addr, i, 0);
 
-   /* Decrement monitor enable counter */
-   dbg_ref_count_mme--;
-   if (dbg_ref_count_mme < 0)
-   dbg_ref_count_mme = 0;
-
-   atomic_thread_fence_rel();
-
-   if (dbg_ref_count_mme == 0) {
-   err = dbg_disable_monitor();
-   if (err != 0)
-   return (err);
-   }
-
/*
 * Save watchpoint settings for all CPUs.
 * We don't need to do the same with breakpoints since HW breakpoints
@@ -827,7 +790,7 @@ dbg_get_ossr(void)
 {
 
switch (dbg_model) {
-   case ID_DFR0_CP_DEBUG_M_V6_1:
+   case ID_DFR0_CP_DEBUG_M_V7:
if ((cp14_dbgoslsr_get() & DBGOSLSR_OSLM0) != 0)
return (TRUE);
 
@@ -844,10 +807,8 @@ dbg_arch_supported(void)
 {
 
switch (dbg_model) {
-#ifdef not_yet
case ID_DFR0_CP_DEBUG_M_V6:
case ID_DFR0_CP_DEBUG_M_V6_1:
-#endif
case ID_DFR0_CP_DEBUG_M_V7:
case ID_DFR0_CP_DEBUG_M_V7_1:   /* fall through */
return (TRUE);
@@ -889,9 +850,16 @@ dbg_reset_state(void)
 
switch (dbg_model) {
case ID_DFR0_CP_DEBUG_M_V6:
-   /* v6 Debug logic reset upon 

Re: svn commit: r300149 - in head/sys: arm/allwinner arm/allwinner/a10 arm/arm arm/broadcom/bcm2835 arm/mv arm/nvidia arm/ti arm/ti/omap4 arm64/arm64 kern mips/mediatek mips/mips sys

[Zbigniew Bodek]

Hello Andrew,

Thanks for your reply. Please see my comments in-line.

Kind regards
zbb

2016-05-18 17:24 GMT+02:00 Andrew Turner <and...@fubar.geek.nz>:

> On Wed, 18 May 2016 17:15:10 +0200
> Zbigniew Bodek <z...@semihalf.com> wrote:
>
> > 2016-05-18 17:05 GMT+02:00 Andrew Turner <and...@freebsd.org>:
> ...
> > >  #ifdef INTRNG
> > > xref = OF_xref_from_node(ofw_bus_get_node(dev));
> > > -   if (intr_pic_register(dev, xref) != 0) {
> > > +   if (intr_pic_register(dev, xref) == NULL) {
> > > device_printf(dev, "could not register PIC\n");
> > > goto error;
> > > }
> > > @@ -172,7 +172,7 @@ error:
> > > /* Failure so free resources */
> > > gic_v3_detach(dev);
> > >
> > > -   return (err);
> > > +   return (ENXIO);
> > >
> >
> >
> > Few line above we have:
> > err = gic_v3_attach(dev);
> > if (err != 0)
> > goto error;
> >
> > So now we would not return error code from gic_v3_attach() but always
> > ENXIO...
>
> The error value doesn't matter, as long as it's non-zero. This also
> fixes the return value in the intrng case if either of
> intr_pic_register or intr_pic_claim_root fail. You might get a little
> information from the return value being printed, however it would be
> more useful to have verbose logging to print an error message.
>
>
So if you wanted to fix INTRNG part why didn't you just set an error value
in case of intr_pic_register() failure before "goto error"?
Simply:

 +   if (intr_pic_register(dev, xref) == NULL) {
 device_printf(dev, "could not register PIC\n");
+   err = ENXIO;
 goto error;
}

Because now we set an error value and in case of real error (not when
gic_v3_attach() returns 0) we print ENXIO while doing nothing with the err
variable...



> In all of these failure cases there isn't much we can do as there is no
> root interrupt controller, the boot will fail later on when we enable
> interrupts.
>

I know but that is not the explanation for breaking the logic here.


>
> Andrew
>
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Re: svn commit: r300149 - in head/sys: arm/allwinner arm/allwinner/a10 arm/arm arm/broadcom/bcm2835 arm/mv arm/nvidia arm/ti arm/ti/omap4 arm64/arm64 kern mips/mediatek mips/mips sys

[Zbigniew Bodek]

2016-05-18 17:05 GMT+02:00 Andrew Turner :

> Author: andrew
> Date: Wed May 18 15:05:44 2016
> New Revision: 300149
> URL: https://svnweb.freebsd.org/changeset/base/300149
>
> Log:
>   Return the struct intr_pic pointer from intr_pic_register. This will be
>   needed in later changes where we may not be able to lock the pic list
> lock
>   to perform a lookup, e.g. from within interrupt context.
>
>   Obtained from:ABT Systems Ltd
>   Sponsored by: The FreeBSD Foundation
>
> Modified:
>   head/sys/arm/allwinner/a10/a10_intc.c
>   head/sys/arm/allwinner/aw_nmi.c
>   head/sys/arm/arm/gic.c
>   head/sys/arm/broadcom/bcm2835/bcm2835_gpio.c
>   head/sys/arm/broadcom/bcm2835/bcm2835_intr.c
>   head/sys/arm/broadcom/bcm2835/bcm2836.c
>   head/sys/arm/mv/mpic.c
>   head/sys/arm/nvidia/tegra_gpio.c
>   head/sys/arm/nvidia/tegra_lic.c
>   head/sys/arm/ti/aintc.c
>   head/sys/arm/ti/omap4/omap4_wugen.c
>   head/sys/arm/ti/ti_gpio.c
>   head/sys/arm64/arm64/gic_v3_fdt.c
>   head/sys/kern/subr_intr.c
>   head/sys/mips/mediatek/mtk_gpio_v1.c
>   head/sys/mips/mediatek/mtk_gpio_v2.c
>   head/sys/mips/mediatek/mtk_intr_gic.c
>   head/sys/mips/mediatek/mtk_intr_v1.c
>   head/sys/mips/mediatek/mtk_intr_v2.c
>   head/sys/mips/mediatek/mtk_pcie.c
>   head/sys/mips/mips/mips_pic.c
>   head/sys/sys/intr.h
>
> Modified: head/sys/arm/allwinner/a10/a10_intc.c
>
> ==
> --- head/sys/arm/allwinner/a10/a10_intc.c   Wed May 18 14:43:17 2016
>   (r300148)
> +++ head/sys/arm/allwinner/a10/a10_intc.c   Wed May 18 15:05:44 2016
>   (r300149)
> @@ -250,6 +250,7 @@ a10_intr(void *arg)
>  static int
>  a10_intr_pic_attach(struct a10_aintc_softc *sc)
>  {
> +   struct intr_pic *pic;
> int error;
> uint32_t irq;
> const char *name;
> @@ -266,9 +267,9 @@ a10_intr_pic_attach(struct a10_aintc_sof
> }
>
> xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev));
> -   error = intr_pic_register(sc->sc_dev, xref);
> -   if (error != 0)
> -   return (error);
> +   pic = intr_pic_register(sc->sc_dev, xref);
> +   if (pic == NULL)
> +   return (ENXIO);
>
> return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0));
>  }
>
> Modified: head/sys/arm/allwinner/aw_nmi.c
>
> ==
> --- head/sys/arm/allwinner/aw_nmi.c Wed May 18 14:43:17 2016
> (r300148)
> +++ head/sys/arm/allwinner/aw_nmi.c Wed May 18 15:05:44 2016
> (r300149)
> @@ -362,7 +362,7 @@ aw_nmi_attach(device_t dev)
>   device_get_nameunit(sc->dev), sc->intr.irq) != 0)
> goto error;
>
> -   if (intr_pic_register(dev, (intptr_t)xref) != 0) {
> +   if (intr_pic_register(dev, (intptr_t)xref) == NULL) {
> device_printf(dev, "could not register pic\n");
> goto error;
> }
>
> Modified: head/sys/arm/arm/gic.c
>
> ==
> --- head/sys/arm/arm/gic.c  Wed May 18 14:43:17 2016(r300148)
> +++ head/sys/arm/arm/gic.c  Wed May 18 15:05:44 2016(r300149)
> @@ -711,7 +711,7 @@ arm_gic_attach(device_t dev)
>  * Now, when everything is initialized, it's right time to
>  * register interrupt controller to interrupt framefork.
>  */
> -   if (intr_pic_register(dev, xref) != 0) {
> +   if (intr_pic_register(dev, xref) == NULL) {
> device_printf(dev, "could not register PIC\n");
> goto cleanup;
> }
>
> Modified: head/sys/arm/broadcom/bcm2835/bcm2835_gpio.c
>
> ==
> --- head/sys/arm/broadcom/bcm2835/bcm2835_gpio.cWed May 18
> 14:43:17 2016(r300148)
> +++ head/sys/arm/broadcom/bcm2835/bcm2835_gpio.cWed May 18
> 15:05:44 2016(r300149)
> @@ -1045,8 +1045,11 @@ bcm_gpio_pic_attach(struct bcm_gpio_soft
> if (error != 0)
> return (error); /* XXX deregister ISRCs */
> }
> -   return (intr_pic_register(sc->sc_dev,
> -   OF_xref_from_node(ofw_bus_get_node(sc->sc_dev;
> +   if (intr_pic_register(sc->sc_dev,
> +   OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL)
> +   return (ENXIO);
> +
> +   return (0);
>  }
>
>  static int
>
> Modified: head/sys/arm/broadcom/bcm2835/bcm2835_intr.c
>
> ==
> --- head/sys/arm/broadcom/bcm2835/bcm2835_intr.cWed May 18
> 14:43:17 2016(r300148)
> +++ head/sys/arm/broadcom/bcm2835/bcm2835_intr.cWed May 18
> 15:05:44 2016(r300149)
> @@ -341,7 +341,10 @@ bcm_intc_pic_register(struct bcm_intc_so
> if (error != 0)
> return 

svn commit: r300136 - head/sys/arm64/arm64

[Zbigniew Bodek]

Author: zbb
Date: Wed May 18 10:09:07 2016
New Revision: 300136
URL: https://svnweb.freebsd.org/changeset/base/300136

Log:
  Add support for MSI/MSIX deallocation on GICv3-ITS
  
  Allow to deallocate previously allocated ITS device along with
  its interrupts. Interrupt numbers are being freed when the last
  LPI number is no longer busy.
  
  Reviewed by:  wma
  Obtained from:Semihalf
  Sponsored by: Cavium
  Differential Revision:https://reviews.freebsd.org/D6351

Modified:
  head/sys/arm64/arm64/gic_v3_its.c
  head/sys/arm64/arm64/gic_v3_var.h

Modified: head/sys/arm64/arm64/gic_v3_its.c
==
--- head/sys/arm64/arm64/gic_v3_its.c   Wed May 18 09:57:11 2016
(r300135)
+++ head/sys/arm64/arm64/gic_v3_its.c   Wed May 18 10:09:07 2016
(r300136)
@@ -75,8 +75,10 @@ static device_method_t gic_v3_its_method
 */
/* MSI-X */
DEVMETHOD(pic_alloc_msix,   gic_v3_its_alloc_msix),
+   DEVMETHOD(pic_release_msix, gic_v3_its_release_msix),
/* MSI */
DEVMETHOD(pic_alloc_msi,gic_v3_its_alloc_msi),
+   DEVMETHOD(pic_release_msi,  gic_v3_its_release_msi),
DEVMETHOD(pic_map_msi,  gic_v3_its_map_msi),
 
/* End */
@@ -882,6 +884,7 @@ retry:
bit_nset(bitmap, fclr, fclr + nvecs - 1);
lpic->lpi_base = fclr + GIC_FIRST_LPI;
lpic->lpi_num = nvecs;
+   lpic->lpi_busy = 0;
lpic->lpi_free = lpic->lpi_num;
lpic->lpi_col_ids = col_ids;
for (i = 0; i < lpic->lpi_num; i++) {
@@ -901,10 +904,9 @@ lpi_free_chunk(struct gic_v3_its_softc *
 {
int start, end;
 
-   KASSERT((lpic->lpi_free == lpic->lpi_num),
-   ("Trying to free LPI chunk that is still in use.\n"));
-
mtx_lock_spin(>its_dev_lock);
+   KASSERT((lpic->lpi_busy == 0),
+   ("Trying to free LPI chunk that is still in use.\n"));
/* First bit of this chunk in a global bitmap */
start = lpic->lpi_base - GIC_FIRST_LPI;
/* and last bit of this chunk... */
@@ -1493,6 +1495,7 @@ its_device_alloc(struct gic_v3_its_softc
 u_int nvecs)
 {
struct its_dev *newdev;
+   vm_offset_t itt_addr;
uint64_t typer;
uint32_t devid;
size_t esize;
@@ -1528,16 +1531,18 @@ its_device_alloc(struct gic_v3_its_softc
 * Allocate ITT for this device.
 * PA has to be 256 B aligned. At least two entries for device.
 */
-   newdev->itt = (vm_offset_t)contigmalloc(
-   roundup2(roundup2(nvecs, 2) * esize, 0x100), M_GIC_V3_ITS,
-   (M_NOWAIT | M_ZERO), 0, ~0UL, 0x100, 0);
-   if (newdev->itt == 0) {
+   newdev->itt_size = roundup2(roundup2(nvecs, 2) * esize, 0x100);
+   itt_addr = (vm_offset_t)contigmalloc(
+   newdev->itt_size, M_GIC_V3_ITS, (M_NOWAIT | M_ZERO),
+   0, ~0UL, 0x100, 0);
+   if (itt_addr == 0) {
lpi_free_chunk(sc, >lpis);
free(newdev, M_GIC_V3_ITS);
return (NULL);
}
 
mtx_lock_spin(>its_dev_lock);
+   newdev->itt = itt_addr;
TAILQ_INSERT_TAIL(>its_dev_list, newdev, entry);
mtx_unlock_spin(>its_dev_lock);
 
@@ -1547,6 +1552,50 @@ its_device_alloc(struct gic_v3_its_softc
return (newdev);
 }
 
+static void
+its_device_free(struct gic_v3_its_softc *sc, device_t pci_dev,
+u_int nvecs)
+{
+   struct its_dev *odev;
+
+   mtx_lock_spin(>its_dev_lock);
+   /* Find existing device if any */
+   odev = its_device_find_locked(sc, pci_dev, 0);
+   if (odev == NULL) {
+   mtx_unlock_spin(>its_dev_lock);
+   return;
+   }
+
+   KASSERT((nvecs <= odev->lpis.lpi_num) && (nvecs <= odev->lpis.lpi_busy),
+   ("Invalid number of LPI vectors to free %d (total %d) (busy %d)",
+   nvecs, odev->lpis.lpi_num, odev->lpis.lpi_busy));
+   /* Just decrement number of busy LPIs in chunk */
+   odev->lpis.lpi_busy -= nvecs;
+   if (odev->lpis.lpi_busy != 0) {
+   mtx_unlock_spin(>its_dev_lock);
+   return;
+   }
+
+   /*
+* At that point we know that there are no busy LPIs for this device.
+* Entire ITS device can now be removed.
+*/
+   mtx_unlock_spin(>its_dev_lock);
+   /* Unmap device in ITS */
+   its_cmd_mapd(sc, odev, 0);
+   /* Free ITT */
+   KASSERT(odev->itt != 0, ("Invalid ITT in valid ITS device"));
+   contigfree((void *)odev->itt, odev->itt_size, M_GIC_V3_ITS);
+   /* Free chunk */
+   lpi_free_chunk(sc, >lpis);
+   /* Free device */
+   mtx_lock_spin(>its_dev_lock);
+   TAILQ_REMOVE(>its_dev_list, odev, entry);
+   mtx_unlock_spin(>its_dev_lock);
+   free((void *)odev, M_GIC_V3_ITS);
+
+}
+
 static __inline void
 its_device_asign_lpi_locked(struct gic_v3_its_softc *sc,
 struct its_dev *its_dev, u_int *irq)
@@ 

Re: svn commit: r299944 - in head/sys: arm64/arm64 conf

[Zbigniew Bodek]

Hello Andrew,

Thanks for the comments. Please check in-line below.

Kind regards
zbb

2016-05-17 14:19 GMT+02:00 Andrew Turner <and...@fubar.geek.nz>:

> On Mon, 16 May 2016 18:08:49 +0200
> Zbigniew Bodek <z...@semihalf.com> wrote:
>
> > Hello Andrew,
> >
> > I think committing this code should be preceded by at least brief
> > review. Few remarks to the code found on the first glance below.
>
> See below for comments.
>
> >
> > Kind regards
> > zbb
> >
> > 2016-05-16 16:07 GMT+02:00 Andrew Turner <and...@freebsd.org>:
> >
> > > Author: andrew
> > > Date: Mon May 16 14:07:43 2016
> > > New Revision: 299944
> > > URL: https://svnweb.freebsd.org/changeset/base/299944
> > >
> > > Log:
> > >   Add intrng support to the GICv3 driver. It lacks ITS support so
> > > won't handle
> > >   MSI or MSI-X interrupts, however this is enought to boot FreeBSD
> > > under the
> > >   ARM Foundation Model with a GICv3 interrupt controller.
> > >
> > >   Approved by:  ABT Systems Ltd
> > >   Relnotes: yes
> > >   Sponsored by: The FreeBSD Foundation
> ...
> > > +#ifdef INTRNG
> > > +int
> > > +arm_gic_v3_intr(void *arg)
> > > +{
> > > +   struct gic_v3_softc *sc = arg;
> > > +   struct gic_v3_irqsrc *gi;
> > > +   uint64_t active_irq;
> > > +   struct trapframe *tf;
> > > +   bool first;
> > > +
> > > +   first = true;
> > > +
> > > +   while (1) {
> > > +   if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
> > > +   /*
> > > +* Hardware:Cavium ThunderX
> > > +* Chip revision:   Pass 1.0 (early
> > > version)
> > > +*  Pass 1.1
> > > (production)
> > > +* ERRATUM: 22978, 23154
> > > +*/
> > > +   __asm __volatile(
> > > +   "nop;nop;nop;nop;nop;nop;nop;nop;   \n"
> > > +   "mrs %0, ICC_IAR1_EL1   \n"
> > > +   "nop;nop;nop;nop;   \n"
> > > +   "dsb sy \n"
> > > +   : "=" (active_irq));
> > > +   } else {
> > > +   active_irq = gic_icc_read(IAR1);
> > > +   }
> > > +
> > > +   if (__predict_false(active_irq >= sc->gic_nirqs))
> > > +   return (FILTER_HANDLED);
> > >
> >
> > IMHO this is not true. Active IRQ could be much bigger than number of
> > supported IRQs. We are asking for debugging in the future when we
> > enable ITS.
>
> It is correct, the ITS change to this file is missing so we are unable
> to enable ITS interrupts.
>
>
In general it is not correct in terms of GICv3 but in that particular case.
So it would be good to have a "ARM64TODO" comment here.


> ...
> > > +
> > > +#ifdef FDT
> > > +static int
> > > +gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int
> > > *irqp,
> > > +enum intr_polarity *polp, enum intr_trigger *trigp)
> > >
> >
> > All other functions are called gic_v3 and this one is just gic_
> > Why can't we move as much FDT code to the dedicated file which is
> > gic_v3_fdt.c?
>
> Unfortunately due to the current code in subr_intr.c this is needed for
> simplicity. It it my understanding there is work to fix this, so for
> now I would prefer to keep this.
>

OK.


>
> ...
> > > +   /* Set the trigger and polarity */
> > > +   if (irq <= GIC_LAST_PPI)
> > > +   reg = gic_r_read(sc, 4,
> > > +   GICR_SGI_BASE_SIZE + GICD_ICFGR(irq));
> > > +   else
> > > +   reg = gic_d_read(sc, 4, GICD_ICFGR(irq));
> > > +   if (trig == INTR_TRIGGER_LEVEL)
> > > +   reg &= ~(2 << ((irq % 16) * 2));
> > > +   else
> > > +   reg |= 2 << ((irq % 16) * 2);
> > >
> >
> > The rule of not using magic numbers does not apply here ;-) ?
>
> This is partially why this is still dis

Re: svn commit: r299944 - in head/sys: arm64/arm64 conf

[Zbigniew Bodek]

Hello Andrew,

I think committing this code should be preceded by at least brief review.
Few remarks to the code found on the first glance below.

Kind regards
zbb

2016-05-16 16:07 GMT+02:00 Andrew Turner :

> Author: andrew
> Date: Mon May 16 14:07:43 2016
> New Revision: 299944
> URL: https://svnweb.freebsd.org/changeset/base/299944
>
> Log:
>   Add intrng support to the GICv3 driver. It lacks ITS support so won't
> handle
>   MSI or MSI-X interrupts, however this is enought to boot FreeBSD under
> the
>   ARM Foundation Model with a GICv3 interrupt controller.
>
>   Approved by:  ABT Systems Ltd
>   Relnotes: yes
>   Sponsored by: The FreeBSD Foundation
>
> Modified:
>   head/sys/arm64/arm64/gic_v3.c
>   head/sys/arm64/arm64/gic_v3_fdt.c
>   head/sys/arm64/arm64/gic_v3_var.h
>   head/sys/conf/files.arm64
>
> Modified: head/sys/arm64/arm64/gic_v3.c
>
> ==
> --- head/sys/arm64/arm64/gic_v3.c   Mon May 16 13:39:04 2016
> (r299943)
> +++ head/sys/arm64/arm64/gic_v3.c   Mon May 16 14:07:43 2016
> (r299944)
> @@ -1,7 +1,10 @@
>  /*-
> - * Copyright (c) 2015 The FreeBSD Foundation
> + * Copyright (c) 2015-2016 The FreeBSD Foundation
>   * All rights reserved.
>   *
> + * This software was developed by Andrew Turner under
> + * the sponsorship of the FreeBSD Foundation.
> + *
>   * This software was developed by Semihalf under
>   * the sponsorship of the FreeBSD Foundation.
>   *
> @@ -27,6 +30,8 @@
>   * SUCH DAMAGE.
>   */
>
> +#include "opt_platform.h"
> +
>  #include 
>  __FBSDID("$FreeBSD$");
>
> @@ -58,6 +63,28 @@ __FBSDID("$FreeBSD$");
>  #include "gic_v3_reg.h"
>  #include "gic_v3_var.h"
>
> +#ifdef INTRNG
> +static pic_disable_intr_t gic_v3_disable_intr;
> +static pic_enable_intr_t gic_v3_enable_intr;
> +static pic_map_intr_t gic_v3_map_intr;
> +static pic_setup_intr_t gic_v3_setup_intr;
> +static pic_teardown_intr_t gic_v3_teardown_intr;
> +static pic_post_filter_t gic_v3_post_filter;
> +static pic_post_ithread_t gic_v3_post_ithread;
> +static pic_pre_ithread_t gic_v3_pre_ithread;
> +static pic_bind_intr_t gic_v3_bind_intr;
> +#ifdef SMP
> +static pic_init_secondary_t gic_v3_init_secondary;
> +static pic_ipi_send_t gic_v3_ipi_send;
> +static pic_ipi_setup_t gic_v3_ipi_setup;
> +#endif
> +
> +static u_int gic_irq_cpu;
> +#ifdef SMP
> +static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
> +static u_int sgi_first_unused = GIC_FIRST_SGI;
> +#endif
> +#else
>  /* Device and PIC methods */
>  static int gic_v3_bind(device_t, u_int, u_int);
>  static void gic_v3_dispatch(device_t, struct trapframe *);
> @@ -68,11 +95,29 @@ static void gic_v3_unmask_irq(device_t,
>  static void gic_v3_init_secondary(device_t);
>  static void gic_v3_ipi_send(device_t, cpuset_t, u_int);
>  #endif
> +#endif
>
>  static device_method_t gic_v3_methods[] = {
> /* Device interface */
> DEVMETHOD(device_detach,gic_v3_detach),
>
> +#ifdef INTRNG
> +   /* Interrupt controller interface */
> +   DEVMETHOD(pic_disable_intr, gic_v3_disable_intr),
> +   DEVMETHOD(pic_enable_intr,  gic_v3_enable_intr),
> +   DEVMETHOD(pic_map_intr, gic_v3_map_intr),
> +   DEVMETHOD(pic_setup_intr,   gic_v3_setup_intr),
> +   DEVMETHOD(pic_teardown_intr,gic_v3_teardown_intr),
> +   DEVMETHOD(pic_post_filter,  gic_v3_post_filter),
> +   DEVMETHOD(pic_post_ithread, gic_v3_post_ithread),
> +   DEVMETHOD(pic_pre_ithread,  gic_v3_pre_ithread),
> +#ifdef SMP
> +   DEVMETHOD(pic_bind_intr,gic_v3_bind_intr),
> +   DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
> +   DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
> +   DEVMETHOD(pic_ipi_setup,gic_v3_ipi_setup),
> +#endif
> +#else
> /* PIC interface */
> DEVMETHOD(pic_bind, gic_v3_bind),
> DEVMETHOD(pic_dispatch, gic_v3_dispatch),
> @@ -83,6 +128,8 @@ static device_method_t gic_v3_methods[]
> DEVMETHOD(pic_init_secondary,   gic_v3_init_secondary),
> DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
>  #endif
> +#endif
> +
> /* End */
> DEVMETHOD_END
>  };
> @@ -144,6 +191,10 @@ gic_v3_attach(device_t dev)
> int rid;
> int err;
> size_t i;
> +#ifdef INTRNG
> +   u_int irq;
> +   const char *name;
> +#endif
>
> sc = device_get_softc(dev);
> sc->gic_registered = FALSE;
> @@ -192,6 +243,36 @@ gic_v3_attach(device_t dev)
> if (sc->gic_nirqs > GIC_I_NUM_MAX)
> sc->gic_nirqs = GIC_I_NUM_MAX;
>
> +#ifdef INTRNG
> +   sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
> +   M_GIC_V3, M_WAITOK | M_ZERO);
> +   name = device_get_nameunit(dev);
> +   for (irq = 0; irq < sc->gic_nirqs; irq++) {
> +   struct intr_irqsrc *isrc;
> +
> +   sc->gic_irqs[irq].gi_irq = irq;
> +  

Re: svn commit: r299934 - head/sys/arm64/cavium

[Zbigniew Bodek]

Are these ThunderX related commits going to be reviewed or tested by anyone
that uses ThunderX?

Kind regards
zbb

2016-05-16 12:03 GMT+02:00 Andrew Turner :

> Author: andrew
> Date: Mon May 16 10:03:57 2016
> New Revision: 299934
> URL: https://svnweb.freebsd.org/changeset/base/299934
>
> Log:
>   Teach the ThunderX PCI PEM driver about intrng. This will be used later
>   when arm64 is supported by intrng.
>
>   Obtained from:ABT Systems Ltd
>   Sponsored by: The FreeBSD Foundation
>
> Modified:
>   head/sys/arm64/cavium/thunder_pcie_pem_fdt.c
>
> Modified: head/sys/arm64/cavium/thunder_pcie_pem_fdt.c
>
> ==
> --- head/sys/arm64/cavium/thunder_pcie_pem_fdt.cMon May 16
> 09:56:48 2016(r299933)
> +++ head/sys/arm64/cavium/thunder_pcie_pem_fdt.cMon May 16
> 10:03:57 2016(r299934)
> @@ -109,6 +109,60 @@ thunder_pem_fdt_probe(device_t dev)
> return (ENXIO);
>  }
>
> +#ifdef INTRNG
> +static int
> +thunder_pem_fdt_alloc_msi(device_t pci, device_t child, int count, int
> maxcount,
> +int *irqs)
> +{
> +   phandle_t msi_parent;
> +
> +   ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
> _parent,
> +   NULL);
> +   return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
> +   irqs));
> +}
> +
> +static int
> +thunder_pem_fdt_release_msi(device_t pci, device_t child, int count, int
> *irqs)
> +{
> +   phandle_t msi_parent;
> +
> +   ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
> _parent,
> +   NULL);
> +   return (intr_release_msi(pci, child, msi_parent, count, irqs));
> +}
> +
> +static int
> +thunder_pem_fdt_alloc_msix(device_t pci, device_t child, int *irq)
> +{
> +   phandle_t msi_parent;
> +
> +   ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
> _parent,
> +   NULL);
> +   return (intr_alloc_msix(pci, child, msi_parent, irq));
> +}
> +
> +static int
> +thunder_pem_fdt_release_msix(device_t pci, device_t child, int irq)
> +{
> +   phandle_t msi_parent;
> +
> +   ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
> _parent,
> +   NULL);
> +   return (intr_release_msix(pci, child, msi_parent, irq));
> +}
> +
> +static int
> +thunder_pem_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t
> *addr,
> +uint32_t *data)
> +{
> +   phandle_t msi_parent;
> +
> +   ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child),
> _parent,
> +   NULL);
> +   return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
> +}
> +#else
>  static int
>  thunder_pem_fdt_alloc_msi(device_t pci, device_t child, int count, int
> maxcount,
>  int *irqs)
> @@ -145,6 +199,7 @@ thunder_pem_fdt_map_msi(device_t pci, de
>
> return (arm_map_msi(pci, child, irq, addr, data));
>  }
> +#endif
>
>  static int
>  thunder_pem_fdt_get_id(device_t dev, device_t child, enum pci_id_type
> type,
> ___
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svn commit: r299447 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Wed May 11 13:42:20 2016
New Revision: 299447
URL: https://svnweb.freebsd.org/changeset/base/299447

Log:
  Add support for MTU chaning and Jumbo frames to VNIC
  
  Enable previously added code for MTU handling (based on
  Cavium 1.0 driver released on BSD license).
  This commit enables possibility to change MTU on VNIC driver.
  
  Obtained from: Semihalf
  Sponsored by:  Cavium

Modified:
  head/sys/dev/vnic/nicvf_main.c

Modified: head/sys/dev/vnic/nicvf_main.c
==
--- head/sys/dev/vnic/nicvf_main.c  Wed May 11 13:38:29 2016
(r299446)
+++ head/sys/dev/vnic/nicvf_main.c  Wed May 11 13:42:20 2016
(r299447)
@@ -138,6 +138,7 @@ static int nicvf_allocate_misc_interrupt
 static int nicvf_enable_misc_interrupt(struct nicvf *);
 static int nicvf_allocate_net_interrupts(struct nicvf *);
 static void nicvf_release_all_interrupts(struct nicvf *);
+static int nicvf_update_hw_max_frs(struct nicvf *, int);
 static int nicvf_hw_set_mac_addr(struct nicvf *, uint8_t *);
 static void nicvf_config_cpi(struct nicvf *);
 static int nicvf_rss_init(struct nicvf *);
@@ -362,7 +363,7 @@ nicvf_setup_ifnet(struct nicvf *nic)
if_setcapabilities(ifp, 0);
 
/* Set the default values */
-   if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
+   if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU, 0);
if_setcapabilitiesbit(ifp, IFCAP_LRO, 0);
if (nic->hw_tso) {
/* TSO */
@@ -465,11 +466,16 @@ nicvf_if_ioctl(struct ifnet *ifp, u_long
err = ether_ioctl(ifp, cmd, data);
break;
case SIOCSIFMTU:
-   /*
-* ARM64TODO: Needs to be implemented.
-* Currently ETHERMTU is set by default.
-*/
-   err = ether_ioctl(ifp, cmd, data);
+   if (ifr->ifr_mtu < NIC_HW_MIN_FRS ||
+   ifr->ifr_mtu > NIC_HW_MAX_FRS) {
+   err = EINVAL;
+   } else {
+   NICVF_CORE_LOCK(nic);
+   err = nicvf_update_hw_max_frs(nic, ifr->ifr_mtu);
+   if (err == 0)
+   if_setmtu(ifp, ifr->ifr_mtu);
+   NICVF_CORE_UNLOCK(nic);
+   }
break;
case SIOCSIFFLAGS:
NICVF_CORE_LOCK(nic);
@@ -974,6 +980,18 @@ nicvf_handle_mbx_intr(struct nicvf *nic)
 }
 
 static int
+nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
+{
+   union nic_mbx mbx = {};
+
+   mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
+   mbx.frs.max_frs = mtu;
+   mbx.frs.vf_id = nic->vf_id;
+
+   return nicvf_send_msg_to_pf(nic, );
+}
+
+static int
 nicvf_hw_set_mac_addr(struct nicvf *nic, uint8_t *hwaddr)
 {
union nic_mbx mbx = {};
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svn commit: r299446 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Wed May 11 13:38:29 2016
New Revision: 299446
URL: https://svnweb.freebsd.org/changeset/base/299446

Log:
  Fix deadlock in VNIC when using single CPU only
  
  Number of free Tx descriptors does not need to be locked since
  it can be modified atomically between SND and CQ tasks.
  It will also block Tx routine from sending packets while CQ will not
  be able to free descriptors.
  
  Obtained from:Semihalf
  Sponsored by: Cavium
  Differential Revision: https://reviews.freebsd.org/D6266

Modified:
  head/sys/dev/vnic/nicvf_queues.c

Modified: head/sys/dev/vnic/nicvf_queues.c
==
--- head/sys/dev/vnic/nicvf_queues.cWed May 11 13:23:56 2016
(r299445)
+++ head/sys/dev/vnic/nicvf_queues.cWed May 11 13:38:29 2016
(r299446)
@@ -48,6 +48,7 @@ __FBSDID("$FreeBSD$");
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -691,7 +692,7 @@ nicvf_rcv_pkt_handler(struct nicvf *nic,
return (0);
 }
 
-static int
+static void
 nicvf_snd_pkt_handler(struct nicvf *nic, struct cmp_queue *cq,
 struct cqe_send_t *cqe_tx, int cqe_type)
 {
@@ -702,15 +703,10 @@ nicvf_snd_pkt_handler(struct nicvf *nic,
 
mbuf = NULL;
sq = >qs->sq[cqe_tx->sq_idx];
-   /* Avoid blocking here since we hold a non-sleepable NICVF_CMP_LOCK */
-   if (NICVF_TX_TRYLOCK(sq) == 0)
-   return (EAGAIN);
 
hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
-   if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) {
-   NICVF_TX_UNLOCK(sq);
-   return (0);
-   }
+   if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
+   return;
 
dprintf(nic->dev,
"%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
@@ -728,9 +724,6 @@ nicvf_snd_pkt_handler(struct nicvf *nic,
}
 
nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
-
-   NICVF_TX_UNLOCK(sq);
-   return (0);
 }
 
 static int
@@ -788,16 +781,8 @@ nicvf_cq_intr_handler(struct nicvf *nic,
work_done++;
break;
case CQE_TYPE_SEND:
-   cmp_err = nicvf_snd_pkt_handler(nic, cq,
-   (void *)cq_desc, CQE_TYPE_SEND);
-   if (__predict_false(cmp_err != 0)) {
-   /*
-* Ups. Cannot finish now.
-* Let's try again later.
-*/
-   goto done;
-   }
-
+   nicvf_snd_pkt_handler(nic, cq, (void *)cq_desc,
+   CQE_TYPE_SEND);
tx_done++;
break;
case CQE_TYPE_INVALID:
@@ -1085,7 +1070,7 @@ nicvf_init_snd_queue(struct nicvf *nic, 
 
sq->desc = sq->dmem.base;
sq->head = sq->tail = 0;
-   sq->free_cnt = q_len - 1;
+   atomic_store_rel_int(>free_cnt, q_len - 1);
sq->thresh = SND_QUEUE_THRESH;
sq->idx = qidx;
sq->nic = nic;
@@ -1676,7 +1661,7 @@ nicvf_get_sq_desc(struct snd_queue *sq, 
int qentry;
 
qentry = sq->tail;
-   sq->free_cnt -= desc_cnt;
+   atomic_subtract_int(>free_cnt, desc_cnt);
sq->tail += desc_cnt;
sq->tail &= (sq->dmem.q_len - 1);
 
@@ -1688,7 +1673,7 @@ static void
 nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)
 {
 
-   sq->free_cnt += desc_cnt;
+   atomic_add_int(>free_cnt, desc_cnt);
sq->head += desc_cnt;
sq->head &= (sq->dmem.q_len - 1);
 }
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svn commit: r299445 - head/sys/arm64/include

[Zbigniew Bodek]

Author: zbb
Date: Wed May 11 13:23:56 2016
New Revision: 299445
URL: https://svnweb.freebsd.org/changeset/base/299445

Log:
  Fix I/O coherence issues on ThunderX when SMP is disabled
  
  To maintain coherence between cache and DMA memory appropriate
  shareability flags need to be set in the PTE regardless of SMP
  option.
  
  Reviewed by:  wma
  Obtained from:Semihalf
  Sponsored by: Cavium
  Differential Revision: https://reviews.freebsd.org/D6231

Modified:
  head/sys/arm64/include/pte.h

Modified: head/sys/arm64/include/pte.h
==
--- head/sys/arm64/include/pte.hWed May 11 13:22:13 2016
(r299444)
+++ head/sys/arm64/include/pte.hWed May 11 13:23:56 2016
(r299445)
@@ -63,11 +63,7 @@ typedef  uint64_tpt_entry_t; /* page 
ta
 #defineATTR_IDX(x) ((x) << 2)
 #defineATTR_IDX_MASK   (7 << 2)
 
-#ifdef SMP
 #defineATTR_DEFAULT(ATTR_AF | ATTR_SH(ATTR_SH_IS))
-#else
-#defineATTR_DEFAULT(ATTR_AF)
-#endif
 
 #defineATTR_DESCR_MASK 3
 
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svn commit: r299444 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Wed May 11 13:22:13 2016
New Revision: 299444
URL: https://svnweb.freebsd.org/changeset/base/299444

Log:
  Add HW RSS support to VNIC driver
  
  Based on v1.0 driver provided by Cavium under BSD license.
  Support in-hardware RSS to distribute IP, UDP and TCP traffic
  among available RX Queues and hence multiple CPUs.
  
  Reviewed by:  wma
  Obtained from:Semihalf
  Sponsored by: Cavium
  Differential Revision: https://reviews.freebsd.org/D6230

Modified:
  head/sys/dev/vnic/nic.h
  head/sys/dev/vnic/nic_main.c
  head/sys/dev/vnic/nicvf_main.c
  head/sys/dev/vnic/nicvf_queues.c

Modified: head/sys/dev/vnic/nic.h
==
--- head/sys/dev/vnic/nic.h Wed May 11 13:20:29 2016(r299443)
+++ head/sys/dev/vnic/nic.h Wed May 11 13:22:13 2016(r299444)
@@ -176,6 +176,24 @@ struct msix_entry {
 #defineNIC_MAX_RSS_IDR_TBL_SIZE(1 << NIC_MAX_RSS_HASH_BITS)
 #defineRSS_HASH_KEY_SIZE   5 /* 320 bit key */
 
+struct nicvf_rss_info {
+   boolean_t enable;
+#defineRSS_L2_EXTENDED_HASH_ENA(1UL << 0)
+#defineRSS_IP_HASH_ENA (1UL << 1)
+#defineRSS_TCP_HASH_ENA(1UL << 2)
+#defineRSS_TCP_SYN_DIS (1UL << 3)
+#defineRSS_UDP_HASH_ENA(1UL << 4)
+#defineRSS_L4_EXTENDED_HASH_ENA(1UL << 5)
+#defineRSS_ROCE_ENA(1UL << 6)
+#defineRSS_L3_BI_DIRECTION_ENA (1UL << 7)
+#defineRSS_L4_BI_DIRECTION_ENA (1UL << 8)
+   uint64_t cfg;
+   uint8_t  hash_bits;
+   uint16_t rss_size;
+   uint8_t  ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
+   uint64_t key[RSS_HASH_KEY_SIZE];
+};
+
 enum rx_stats_reg_offset {
RX_OCTS = 0x0,
RX_UCAST = 0x1,
@@ -285,6 +303,7 @@ struct nicvf {
boolean_t   tns_mode:1;
boolean_t   sqs_mode:1;
boolloopback_supported:1;
+   struct nicvf_rss_info   rss_info;
uint16_tmtu;
struct queue_set*qs;
uint8_t rx_queues;

Modified: head/sys/dev/vnic/nic_main.c
==
--- head/sys/dev/vnic/nic_main.cWed May 11 13:20:29 2016
(r299443)
+++ head/sys/dev/vnic/nic_main.cWed May 11 13:22:13 2016
(r299444)
@@ -103,6 +103,7 @@ struct nicpf {
uint8_t duplex[MAX_LMAC];
uint32_tspeed[MAX_LMAC];
uint16_tcpi_base[MAX_NUM_VFS_SUPPORTED];
+   uint16_trssi_base[MAX_NUM_VFS_SUPPORTED];
uint16_trss_ind_tbl_size;
 
/* MSI-X */
@@ -744,6 +745,58 @@ nic_config_cpi(struct nicpf *nic, struct
rssi = ((cpi - cpi_base) & 0x38) >> 3;
}
nic->cpi_base[cfg->vf_id] = cpi_base;
+   nic->rssi_base[cfg->vf_id] = rssi_base;
+}
+
+/* Responsds to VF with its RSS indirection table size */
+static void
+nic_send_rss_size(struct nicpf *nic, int vf)
+{
+   union nic_mbx mbx = {};
+   uint64_t  *msg;
+
+   msg = (uint64_t *)
+
+   mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
+   mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
+   nic_send_msg_to_vf(nic, vf, );
+}
+
+/*
+ * Receive side scaling configuration
+ * configure:
+ * - RSS index
+ * - indir table i.e hash::RQ mapping
+ * - no of hash bits to consider
+ */
+static void
+nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
+{
+   uint8_t qset, idx;
+   uint64_t cpi_cfg, cpi_base, rssi_base, rssi;
+   uint64_t idx_addr;
+
+   idx = 0;
+   rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
+
+   rssi = rssi_base;
+   qset = cfg->vf_id;
+
+   for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
+   nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
+   (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
+   idx++;
+   }
+
+   cpi_base = nic->cpi_base[cfg->vf_id];
+   if (pass1_silicon(nic->dev))
+   idx_addr = NIC_PF_CPI_0_2047_CFG;
+   else
+   idx_addr = NIC_PF_MPI_0_2047_CFG;
+   cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
+   cpi_cfg &= ~(0xFUL << 20);
+   cpi_cfg |= (cfg->hash_bits << 20);
+   nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
 }
 
 /*
@@ -896,6 +949,13 @@ nic_handle_mbx_intr(struct nicpf *nic, i
case NIC_MBOX_MSG_CPI_CFG:
nic_config_cpi(nic, _cfg);
break;
+   case NIC_MBOX_MSG_RSS_SIZE:
+   nic_send_rss_size(nic, vf);
+   goto unlock;
+   case NIC_MBOX_MSG_RSS_CFG:
+   case NIC_MBOX_MSG_RSS_CFG_CONT: /* fall through */
+   nic_config_rss(nic, _cfg);
+   

svn commit: r299443 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Wed May 11 13:20:29 2016
New Revision: 299443
URL: https://svnweb.freebsd.org/changeset/base/299443

Log:
  Bind CQ interrupts and tasks to separate CPUs in VNIC
  
  Delegate interrupts and completion tasks on separate CPUs
  for each VNIC.
  
  Reviewed by:  wma
  Obtained from:Semihalf
  Sponsored by: Cavium
  Differential Revision: https://reviews.freebsd.org/D6229

Modified:
  head/sys/dev/vnic/nicvf_main.c
  head/sys/dev/vnic/nicvf_queues.h

Modified: head/sys/dev/vnic/nicvf_main.c
==
--- head/sys/dev/vnic/nicvf_main.c  Wed May 11 12:58:12 2016
(r299442)
+++ head/sys/dev/vnic/nicvf_main.c  Wed May 11 13:20:29 2016
(r299443)
@@ -1296,6 +1296,7 @@ nicvf_release_net_interrupts(struct nicv
 static int
 nicvf_allocate_net_interrupts(struct nicvf *nic)
 {
+   u_int cpuid;
int irq, rid;
int qidx;
int ret = 0;
@@ -1332,6 +1333,20 @@ nicvf_allocate_net_interrupts(struct nic
(irq - NICVF_INTR_ID_CQ), 
device_get_unit(nic->dev));
goto error;
}
+   cpuid = (device_get_unit(nic->dev) * CMP_QUEUE_CNT) + qidx;
+   cpuid %= mp_ncpus;
+   /*
+* Save CPU ID for later use when system-wide RSS is enabled.
+* It will be used to pit the CQ task to the same CPU that got
+* interrupted.
+*/
+   nic->qs->cq[qidx].cmp_cpuid = cpuid;
+   if (bootverbose) {
+   device_printf(nic->dev, "bind CQ%d IRQ to CPU%d\n",
+   qidx, cpuid);
+   }
+   /* Bind interrupts to the given CPU */
+   bus_bind_intr(nic->dev, nic->msix_entries[irq].irq_res, cpuid);
}
 
/* Register RBDR interrupt */

Modified: head/sys/dev/vnic/nicvf_queues.h
==
--- head/sys/dev/vnic/nicvf_queues.hWed May 11 12:58:12 2016
(r299442)
+++ head/sys/dev/vnic/nicvf_queues.hWed May 11 13:20:29 2016
(r299443)
@@ -296,6 +296,7 @@ struct cmp_queue {
 
struct task cmp_task;
struct taskqueue*cmp_taskq;
+   u_int   cmp_cpuid; /* CPU to which bind the CQ task */
 
void*desc;
struct q_desc_mem   dmem;
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Re: svn commit: r299090 - in head: etc/mtree include lib/libbluetooth sbin/hastd share/man/man3 sys/dev/xen/blkback sys/kern sys/net sys/sys tests/sys tests/sys/sys usr.sbin/bluetooth/hccontrol

[Zbigniew Bodek]

Hi,

It broke build for ARM64 but fixed here:
https://svnweb.freebsd.org/changeset/base/299124

Best regards
zbb

2016-05-05 18:45 GMT+02:00 Alan Somers :

> On Thu, May 5, 2016 at 10:31 AM, John Baldwin  wrote:
>
> > On Wednesday, May 04, 2016 10:34:11 PM Alan Somers wrote:
> > > Author: asomers
> > > Date: Wed May  4 22:34:11 2016
> > > New Revision: 299090
> > > URL: https://svnweb.freebsd.org/changeset/base/299090
> > >
> > > Log:
> > >   Improve performance and functionality of the bitstring(3) api
> > >
> > >   Two new functions are provided, bit_ffs_at() and bit_ffc_at(), which
> > allow
> > >   for efficient searching of set or cleared bits starting from any bit
> > offset
> > >   within the bit string.
> > >
> > >   Performance is improved by operating on longs instead of bytes and
> > using
> > >   ffsl() for searches within a long. ffsl() is a compiler builtin in
> both
> > >   clang and gcc for most architectures, converting what was a brute
> force
> > >   while loop search into a couple of instructions.
> > >
> > >   All of the bitstring(3) API continues to be contained in the header
> > file.
> > >   Some of the functions are large enough that perhaps they should be
> > uninlined
> > >   and moved to a library, but that is beyond the scope of this commit.
> >
> > Doesn't switching from bytes to longs break the ABI?  That is, setting
> bit
> > 9
> > now has a different representation on big-endian systems (0x00 0x01
> before,
> > now 0x00 0x00 0x01 0x00 on 32-bit BE, and 4 more leading 0 bytes on
> > 64-bit).
> > This means you can't have an object file compiled against the old header
> > pass a bitstring to an object file compiled against the new header on
> > big-endian
> > systems.
> >
> > Even on little-endian systems if an old object file allocates storage
> for a
> > bitstring the new code might read off the end of it and fault (or return
> > garbage if bits are set in the extra bytes it reads off the end)?
> >
> > Is the API is so little used we don't care?
> >
> > --
> > John Baldwin
> >
>
> The API isn't used in any shared libraries, so the only risk would be if
> it's used in a user application where the user's build system doesn't check
> for changes in system libraries, and the user upgrades FreeBSD without
> doing a clean build of his application, right?  Am I missing any other
> scenarios?  Do we need to warn users with a line in UPDATING or something?
>
> This is similar to an upgrade of the C++ compiler.  C++ objects built by
> different minor versions of the compiler aren't guaranteed to be
> compatible.
>
> -Alan
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svn commit: r299124 - head/sys/arm64/arm64

[Zbigniew Bodek]

Author: zbb
Date: Thu May  5 17:51:14 2016
New Revision: 299124
URL: https://svnweb.freebsd.org/changeset/base/299124

Log:
  Fix GICv3 build after r299090
  
  Obtained from:Semihalf
  Sponsored by: Cavium

Modified:
  head/sys/arm64/arm64/gic_v3.c
  head/sys/arm64/arm64/gic_v3_fdt.c
  head/sys/arm64/arm64/gic_v3_its.c
  head/sys/arm64/arm64/gic_v3_var.h

Modified: head/sys/arm64/arm64/gic_v3.c
==
--- head/sys/arm64/arm64/gic_v3.c   Thu May  5 17:47:03 2016
(r299123)
+++ head/sys/arm64/arm64/gic_v3.c   Thu May  5 17:51:14 2016
(r299124)
@@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 

Modified: head/sys/arm64/arm64/gic_v3_fdt.c
==
--- head/sys/arm64/arm64/gic_v3_fdt.c   Thu May  5 17:47:03 2016
(r299123)
+++ head/sys/arm64/arm64/gic_v3_fdt.c   Thu May  5 17:51:14 2016
(r299124)
@@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 

Modified: head/sys/arm64/arm64/gic_v3_its.c
==
--- head/sys/arm64/arm64/gic_v3_its.c   Thu May  5 17:47:03 2016
(r299123)
+++ head/sys/arm64/arm64/gic_v3_its.c   Thu May  5 17:51:14 2016
(r299124)
@@ -852,7 +852,7 @@ lpi_alloc_chunk(struct gic_v3_its_softc 
 {
u_int *col_ids;
int fclr; /* First cleared bit */
-   uint8_t *bitmap;
+   bitstr_t *bitmap;
size_t nb, i;
 
col_ids = malloc(sizeof(*col_ids) * nvecs, M_GIC_V3_ITS,
@@ -861,7 +861,7 @@ lpi_alloc_chunk(struct gic_v3_its_softc 
return (ENOMEM);
 
mtx_lock_spin(>its_dev_lock);
-   bitmap = (uint8_t *)sc->its_lpi_bitmap;
+   bitmap = sc->its_lpi_bitmap;
 
fclr = 0;
 retry:
@@ -901,9 +901,6 @@ static void
 lpi_free_chunk(struct gic_v3_its_softc *sc, struct lpi_chunk *lpic)
 {
int start, end;
-   uint8_t *bitmap;
-
-   bitmap = (uint8_t *)sc->its_lpi_bitmap;
 
KASSERT((lpic->lpi_free == lpic->lpi_num),
("Trying to free LPI chunk that is still in use.\n"));
@@ -915,7 +912,7 @@ lpi_free_chunk(struct gic_v3_its_softc *
end = start + lpic->lpi_num - 1;
 
/* Finally free this chunk */
-   bit_nclear(bitmap, start, end);
+   bit_nclear(sc->its_lpi_bitmap, start, end);
mtx_unlock_spin(>its_dev_lock);
 
free(lpic->lpi_col_ids, M_GIC_V3_ITS);

Modified: head/sys/arm64/arm64/gic_v3_var.h
==
--- head/sys/arm64/arm64/gic_v3_var.h   Thu May  5 17:47:03 2016
(r299123)
+++ head/sys/arm64/arm64/gic_v3_var.h   Thu May  5 17:51:14 2016
(r299124)
@@ -236,7 +236,7 @@ struct gic_v3_its_softc {
 
struct its_dev_list its_dev_list;
 
-   unsigned long * its_lpi_bitmap;
+   bitstr_t *  its_lpi_bitmap;
uint32_tits_lpi_maxid;
 
struct mtx  its_dev_lock;
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Re: svn commit: r298425 - head/sys/dev/acpica

[Zbigniew Bodek]

2016-04-27 18:46 GMT+02:00 John Baldwin <j...@freebsd.org>:

> On Wednesday, April 27, 2016 04:57:28 PM Zbigniew Bodek wrote:
> > Hello,
> >
> > I'm forwarding a message from Michal Stanek who found some problems wit
> > this commit. Please see below:
>
> It looks like you have "cpuX" devices that aren't acpi_cpu.c devices.
> That's fine, but that is why this driver is confused a bit.  Before my
> change all that happened was that this triggered extra probe/attach of
> child devices, but now it queues the ACPI-specific task as well.
>
> I've add you to a review for a change I think will fix this (and which I've
> tested on amd64 with ACPI):
>
> https://reviews.freebsd.org/D6133
>
> Thanks. Please add Michal Stanek (mst) as well.

Best regards
zbb
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Re: svn commit: r298425 - head/sys/dev/acpica

[Zbigniew Bodek]

Hello,

I'm forwarding a message from Michal Stanek who found some problems wit
this commit. Please see below:

---
I'm getting a lot of ACPI error messages on ThunderX (arm64). The kernel
also panics before it gets to prompt.
Running bisect pointed to this patch as the culprit.

Removing acpi from GENERIC configuration fixes the issue.

Here is the boot log:

FreeBSD/SMP: Multiprocessor System Detected: 48 CPUs
random: entropy device external interface
ACPI: Table initialisation failed: AE_NOT_FOUND
ACPI: Try disabling either ACPI or apic support.
ofwbus0: 
simplebus0:  on ofwbus0
(...)
Timecounters tick every 1.000 msec
usbus0: 5.0Gbps Super Speed USB v3.0
usbus1: 5.0Gbps Super Speed USB v3.0
ugen0.1: <0x177d> at usbus0
uhub0: <0x177d XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus0
ugen1.1: <0x177d> at usbus1
uhub1: <0x177d XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus1
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ACPI Exception: AE_BAD_PARAMETER, Thread 100112 could not acquire Mutex
[0x1] (20150818/utmutex-320)
ada0 at ahcich0 bus 0 scbus0 target 0 lun 0
ada0:  ATA-7 SATA 1.x device
ada0: Serial Number 9QZ6QN7K
ada0: 150.000MB/s transfers (SATA 1.x, UDMA6, PIO 8192bytes)
ada0: Command Queueing enabled
ada0: 76319MB (156301488 512 byte sectors)
ACPI Exception: AE_BAD_PARAMETER, nfs_diskless: no NFS handle
Release APs
CPU  0: Cavium Thunder r0p1 affinity:  0  0
 Instruction Set Attributes 0 = 
 Instruction Set Attributes 1 = <0>
Thread 100112 could not acquire Mutex [0x1] Processor Features 0 =
< (20150818/utmutex-320)
GICACPI Exception: AE_BAD_PARAMETER, ,AdvSIMDThread 100112 could not
acquire Mutex [0x1],Float (20150818/utmutex-320)
,EL3ACPI Exception: AE_BAD_PARAMETER, ,EL2Thread 100112 could not acquire
Mutex [0x1],EL1 (20150818/utmutex-320)
,EL0ACPI Exception: AE_BAD_PARAMETER, >
Thread 100112 could not acquire Mutex [0x1] Processor Features 1 =
<0>
 (20150818/utmutex-320)
  Memory Model Features 0 = 
 (20150818/utmutex-320)
  Memory Model Features 1 = <0x20>
ACPI Exception: AE_BAD_PARAMETER,  Debug Features 0 = 
Thread 100112 could not acquire Mutex [0x1] Debug Features 1 =
<0>
 (20150818/utmutex-320)
 Auxiliary Features 0 = <0>
ACPI Exception: AE_BAD_PARAMETER,  Auxiliary Features 1 = <0>
Thread 100112 could not acquire Mutex [0x1]CPU  1: Cavium Thunder r0p1
(20150818/utmutex-320)
 affinity:ACPI Exception: AE_BAD_PARAMETER,   0Thread 100112 could not
acquire Mutex [0x1]  1 (20150818/utmutex-320)

ACPI Exception: AE_BAD_PARAMETER, CPU  2: Cavium Thunder r0p1Thread 100112
could not acquire Mutex [0x1] affinity: (20150818/utmutex-320)
  0ACPI Exception: AE_BAD_PARAMETER,   2Thread 100112 could not acquire
Mutex [0x1]
 (20150818/utmutex-320)
CPU  3: Cavium Thunder r0p1ACPI Exception: AE_BAD_PARAMETER,
 affinity:Thread 100112 could not acquire Mutex [0x1]  0
(20150818/utmutex-320)
  3ACPI Exception: AE_BAD_PARAMETER,
Thread 100112 could not acquire Mutex [0x1]CPU  4: Cavium Thunder r0p1
(20150818/utmutex-320)
 affinity:ACPI Exception: AE_BAD_PARAMETER,   0Thread 100112 could not
acquire Mutex [0x1]  4 (20150818/utmutex-320)

ACPI Exception: AE_BAD_PARAMETER, CPU  5: Cavium Thunder r0p1Thread 100112
could not acquire Mutex [0x1] affinity: (20150818/utmutex-320)
  0ACPI Exception: AE_BAD_PARAMETER,   5Thread 100112 could not acquire
Mutex [0x1]
 (20150818/utmutex-320)
CPU  6: Cavium Thunder r0p1ACPI Exception: AE_BAD_PARAMETER,
 affinity:Thread 100112 could not acquire Mutex [0x1]  0
(20150818/utmutex-320)
  6ACPI Exception: AE_BAD_PARAMETER,
Thread 100112 could not acquire Mutex [0x1]CPU  7: Cavium Thunder r0p1
(20150818/utmutex-320)
 affinity:ACPI Exception: AE_BAD_PARAMETER,   0Thread 100112 could not
acquire Mutex [0x1]  7 (20150818/utmutex-320)

ACPI Exception: AE_BAD_PARAMETER, CPU  8: Cavium Thunder r0p1Thread 100112
could not acquire Mutex [0x1] affinity: (20150818/utmutex-320)
  0ACPI Exception: AE_BAD_PARAMETER,   8Thread 100112 could not acquire
Mutex [0x1]
 (20150818/utmutex-320)
CPU  9: Cavium Thunder r0p1ACPI Exception: AE_BAD_PARAMETER,
 affinity:Thread 100112 could not acquire Mutex [0x1] 

svn commit: r297721 - head/sys/dev/vnic

[Zbigniew Bodek]

Author: zbb
Date: Fri Apr  8 16:14:18 2016
New Revision: 297721
URL: https://svnweb.freebsd.org/changeset/base/297721

Log:
  Fix sending TSO packets larger than single DMA segment on VNIC
  
  Due to the bug in the number of 'GATHER' subdescriptors for TSO
  packets, VNIC was not able to transmit more than one DMA segment
  with TSO enabled.
  
  Obtained from: Semihalf
  Sponsored by:  Cavium

Modified:
  head/sys/dev/vnic/nicvf_queues.c

Modified: head/sys/dev/vnic/nicvf_queues.c
==
--- head/sys/dev/vnic/nicvf_queues.cFri Apr  8 15:48:10 2016
(r297720)
+++ head/sys/dev/vnic/nicvf_queues.cFri Apr  8 16:14:18 2016
(r297721)
@@ -1904,7 +1904,6 @@ static int
 nicvf_tx_mbuf_locked(struct snd_queue *sq, struct mbuf **mbufp)
 {
bus_dma_segment_t segs[256];
-   struct nicvf *nic;
struct snd_buff *snd_buff;
size_t seg;
int nsegs, qentry;
@@ -1928,12 +1927,7 @@ nicvf_tx_mbuf_locked(struct snd_queue *s
}
 
/* Set how many subdescriptors is required */
-   nic = sq->nic;
-   if ((*mbufp)->m_pkthdr.tso_segsz != 0 && nic->hw_tso)
-   subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT;
-   else
-   subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT + nsegs - 1;
-
+   subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT + nsegs - 1;
if (subdesc_cnt > sq->free_cnt) {
/* ARM64TODO: Add mbuf defragmentation if we lack descriptors */
bus_dmamap_unload(sq->snd_buff_dmat, snd_buff->dmap);
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