Re: svn commit: r310650 - in head/sys/mips: include mips
On Tuesday, December 27, 2016 09:50:32 PM Adrian Chadd wrote: > hiya, > > so I dug into the mips24k definition of this. It says this: > > " > 3.4.3 Uncached accelerated writes > The 24K core permits memory regions to be marked as “uncached > accelerated”. This type of region is useful to hard- > ware which is “write only” - perhaps video frame buffers, or some > other hardware stream. Sequential word stores in > such regions are gathered into cache-line-sized chunks, before being > written with a single burst cycle on the CPU > interface. > Such regions are uncached for read, and partial-word or > out-of-sequence writes have “unpredictable” effects - don’t > do them. The burst write is normally performed when software writes to > the last location in the memory block or does > an uncached-accelerated write to some other block; but it can also be > triggered by a > sync instruction, a pref nudge, a matching load or any exception. If > the block is not completely written by the time it’s pushed out, it > will be written using a series of doubleword or smaller write cycles > over the 24K core’s 64-bit memory interface. > " > > So, question is - is our write combining page attribute in the VM > suitable for this? Is it defined as "only do full sequential word > writes"? Or do we risk having some other platform use it in a less > "don't do this" way and then MIPS is the one at fault again? :) The description of WC in the Intel SDM appears to be more forgiving. If you do out-of-sequence writes it won't "lose" the data, but there isn't a strong ordering of when the different regions of a cache line are finally written. Also, different WC store buffers may be written out-of-order (e.g. if you partially fill one line, then fully fill a second line, the second line may be written out, but the first one will be held for a bit to see if it will be fully filled). However, you never lose the data, and the last thing written will eventually end up being written to the bus. -- John Baldwin ___ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r310650 - in head/sys/mips: include mips
On Tue, 27 Dec 2016 21:50:32 -0800 Adrian Chadd wrote: > hiya, > > so I dug into the mips24k definition of this. It says this: > > " > 3.4.3 Uncached accelerated writes > The 24K core permits memory regions to be marked as "uncached > accelerated". This type of region is useful to hard- > ware which is "write only" - perhaps video frame buffers, or some > other hardware stream. Sequential word stores in > such regions are gathered into cache-line-sized chunks, before being > written with a single burst cycle on the CPU > interface. > Such regions are uncached for read, and partial-word or > out-of-sequence writes have "unpredictable" effects - don't > do them. The burst write is normally performed when software writes to > the last location in the memory block or does > an uncached-accelerated write to some other block; but it can also be > triggered by a > sync instruction, a pref nudge, a matching load or any exception. If > the block is not completely written by the time it's pushed out, it > will be written using a series of doubleword or smaller write cycles > over the 24K core's 64-bit memory interface. > " > > So, question is - is our write combining page attribute in the VM > suitable for this? Is it defined as "only do full sequential word > writes"? Or do we risk having some other platform use it in a less > "don't do this" way and then MIPS is the one at fault again? :) > > > -adrian > > FWIW, this is more or less standard verbiage for memory mapped devices and devices is where one would expect framebuffer to reside, so I would not read too much into it. I committed change that does not map UA to WC unconditionally and will let people who need write combining to enable it on a case by case basis. For now, only Ingenic XBursts are doing so as these are ones I have tested. -- Alexander Kabaev pgp4owHqbim3S.pgp Description: Цифровая подпись OpenPGP
Re: svn commit: r310650 - in head/sys/mips: include mips
hiya,
so I dug into the mips24k definition of this. It says this:
"
3.4.3 Uncached accelerated writes
The 24K core permits memory regions to be marked as “uncached
accelerated”. This type of region is useful to hard-
ware which is “write only” - perhaps video frame buffers, or some
other hardware stream. Sequential word stores in
such regions are gathered into cache-line-sized chunks, before being
written with a single burst cycle on the CPU
interface.
Such regions are uncached for read, and partial-word or
out-of-sequence writes have “unpredictable” effects - don’t
do them. The burst write is normally performed when software writes to
the last location in the memory block or does
an uncached-accelerated write to some other block; but it can also be
triggered by a
sync instruction, a pref nudge, a matching load or any exception. If
the block is not completely written by the time it’s pushed out, it
will be written using a series of doubleword or smaller write cycles
over the 24K core’s 64-bit memory interface.
"
So, question is - is our write combining page attribute in the VM
suitable for this? Is it defined as "only do full sequential word
writes"? Or do we risk having some other platform use it in a less
"don't do this" way and then MIPS is the one at fault again? :)
-adrian
On 27 December 2016 at 18:55, Alexander Kabaev wrote:
> Author: kan
> Date: Wed Dec 28 02:55:26 2016
> New Revision: 310650
> URL: https://svnweb.freebsd.org/changeset/base/310650
>
> Log:
> Implement pmap_change_attr and related APIs on MIPS
>
> On platforms that have uncached-accelerate cache attribute, map it
> to VM_MEMATTR_WRITE_COMBINING. Otherwise, leave write comining
> undefined.
>
> Reviewed by: adrian, jhb (glance)
> Differential Revision:https://reviews.freebsd.org/D8894
>
> Modified:
> head/sys/mips/include/cpuregs.h
> head/sys/mips/include/pmap.h
> head/sys/mips/include/pte.h
> head/sys/mips/include/vm.h
> head/sys/mips/mips/pmap.c
>
> Modified: head/sys/mips/include/cpuregs.h
> ==
> --- head/sys/mips/include/cpuregs.h Tue Dec 27 23:56:46 2016
> (r310649)
> +++ head/sys/mips/include/cpuregs.h Wed Dec 28 02:55:26 2016
> (r310650)
> @@ -171,6 +171,10 @@
> #defineMIPS_CCA_CACHED MIPS_CCA_CCS
> #endif
>
> +#if defined(CPU_XBURST)
> +#defineMIPS_CCA_UA 0x01
> +#endif
> +
> #ifndefMIPS_CCA_UNCACHED
> #defineMIPS_CCA_UNCACHED MIPS_CCA_UC
> #endif
> @@ -188,6 +192,16 @@
> #endif
> #endif
>
> +/*
> + * Use uncached-accelerated mode for write-combining maps, if one is defined,
> + * otherwise fall back to uncached
> + */
> +#ifndef MIPS_CCA_WC
> +#ifdef MIPS_CCA_UA
> +#defineMIPS_CCA_WC MIPS_CCA_UA
> +#endif
> +#endif
> +
> #defineMIPS_PHYS_TO_XKPHYS(cca,x) \
> ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
> #defineMIPS_PHYS_TO_XKPHYS_CACHED(x) \
>
> Modified: head/sys/mips/include/pmap.h
> ==
> --- head/sys/mips/include/pmap.hTue Dec 27 23:56:46 2016
> (r310649)
> +++ head/sys/mips/include/pmap.hWed Dec 28 02:55:26 2016
> (r310650)
> @@ -74,7 +74,8 @@ struct md_page {
> };
>
> #definePV_TABLE_REF0x02/* referenced */
> -#definePV_MEMATTR_UNCACHEABLE 0x04
> +#definePV_MEMATTR_MASK 0xf0/* store vm_memattr_t here */
> +#definePV_MEMATTR_SHIFT0x04
>
> #defineASID_BITS 8
> #defineASIDGEN_BITS(32 - ASID_BITS)
> @@ -163,22 +164,24 @@ extern vm_offset_t virtual_end;
>
> extern vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
>
> -#definepmap_page_get_memattr(m)VM_MEMATTR_DEFAULT
> +#definepmap_page_get_memattr(m) (((m)->md.pv_flags &
> PV_MEMATTR_MASK) >> PV_MEMATTR_SHIFT)
> #definepmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
> #definepmap_page_is_write_mapped(m)(((m)->aflags &
> PGA_WRITEABLE) != 0)
>
> void pmap_bootstrap(void);
> void *pmap_mapdev(vm_paddr_t, vm_size_t);
> +void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
> void pmap_unmapdev(vm_offset_t, vm_size_t);
> vm_offset_t pmap_steal_memory(vm_size_t size);
> void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
> -void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr);
> +void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t attr);
> void pmap_kremove(vm_offset_t va);
> void *pmap_kenter_temporary(vm_paddr_t pa, int i);
> void pmap_kenter_temporary_free(vm_paddr_t pa);
> void pmap_flush_pvcache(vm_page_t m);
> int pmap_emulate_modified(pmap_t pmap, vm_offset_t va);
> void pmap_page_set_memattr(vm_page_t, vm_memattr_t);
> +int pmap_change_attr(vm_offset_t, vm_size_t, vm_memattr_t);
>
> #endif
svn commit: r310650 - in head/sys/mips: include mips
Author: kan
Date: Wed Dec 28 02:55:26 2016
New Revision: 310650
URL: https://svnweb.freebsd.org/changeset/base/310650
Log:
Implement pmap_change_attr and related APIs on MIPS
On platforms that have uncached-accelerate cache attribute, map it
to VM_MEMATTR_WRITE_COMBINING. Otherwise, leave write comining
undefined.
Reviewed by: adrian, jhb (glance)
Differential Revision:https://reviews.freebsd.org/D8894
Modified:
head/sys/mips/include/cpuregs.h
head/sys/mips/include/pmap.h
head/sys/mips/include/pte.h
head/sys/mips/include/vm.h
head/sys/mips/mips/pmap.c
Modified: head/sys/mips/include/cpuregs.h
==
--- head/sys/mips/include/cpuregs.h Tue Dec 27 23:56:46 2016
(r310649)
+++ head/sys/mips/include/cpuregs.h Wed Dec 28 02:55:26 2016
(r310650)
@@ -171,6 +171,10 @@
#defineMIPS_CCA_CACHED MIPS_CCA_CCS
#endif
+#if defined(CPU_XBURST)
+#defineMIPS_CCA_UA 0x01
+#endif
+
#ifndefMIPS_CCA_UNCACHED
#defineMIPS_CCA_UNCACHED MIPS_CCA_UC
#endif
@@ -188,6 +192,16 @@
#endif
#endif
+/*
+ * Use uncached-accelerated mode for write-combining maps, if one is defined,
+ * otherwise fall back to uncached
+ */
+#ifndef MIPS_CCA_WC
+#ifdef MIPS_CCA_UA
+#defineMIPS_CCA_WC MIPS_CCA_UA
+#endif
+#endif
+
#defineMIPS_PHYS_TO_XKPHYS(cca,x) \
((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
#defineMIPS_PHYS_TO_XKPHYS_CACHED(x) \
Modified: head/sys/mips/include/pmap.h
==
--- head/sys/mips/include/pmap.hTue Dec 27 23:56:46 2016
(r310649)
+++ head/sys/mips/include/pmap.hWed Dec 28 02:55:26 2016
(r310650)
@@ -74,7 +74,8 @@ struct md_page {
};
#definePV_TABLE_REF0x02/* referenced */
-#definePV_MEMATTR_UNCACHEABLE 0x04
+#definePV_MEMATTR_MASK 0xf0/* store vm_memattr_t here */
+#definePV_MEMATTR_SHIFT0x04
#defineASID_BITS 8
#defineASIDGEN_BITS(32 - ASID_BITS)
@@ -163,22 +164,24 @@ extern vm_offset_t virtual_end;
extern vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
-#definepmap_page_get_memattr(m)VM_MEMATTR_DEFAULT
+#definepmap_page_get_memattr(m) (((m)->md.pv_flags & PV_MEMATTR_MASK)
>> PV_MEMATTR_SHIFT)
#definepmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
#definepmap_page_is_write_mapped(m)(((m)->aflags & PGA_WRITEABLE)
!= 0)
void pmap_bootstrap(void);
void *pmap_mapdev(vm_paddr_t, vm_size_t);
+void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
void pmap_unmapdev(vm_offset_t, vm_size_t);
vm_offset_t pmap_steal_memory(vm_size_t size);
void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
-void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr);
+void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t attr);
void pmap_kremove(vm_offset_t va);
void *pmap_kenter_temporary(vm_paddr_t pa, int i);
void pmap_kenter_temporary_free(vm_paddr_t pa);
void pmap_flush_pvcache(vm_page_t m);
int pmap_emulate_modified(pmap_t pmap, vm_offset_t va);
void pmap_page_set_memattr(vm_page_t, vm_memattr_t);
+int pmap_change_attr(vm_offset_t, vm_size_t, vm_memattr_t);
#endif /* _KERNEL */
Modified: head/sys/mips/include/pte.h
==
--- head/sys/mips/include/pte.h Tue Dec 27 23:56:46 2016(r310649)
+++ head/sys/mips/include/pte.h Wed Dec 28 02:55:26 2016(r310650)
@@ -132,8 +132,10 @@ typedefpt_entry_t *pd_entry_t;
* it is matched.
*/
#definePTE_C(attr) ((attr & 0x07) << 3)
+#definePTE_C_MASK (PTE_C(0x07))
#definePTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
#definePTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
+#definePTE_C_WC(PTE_C(MIPS_CCA_WC))
#definePTE_D 0x04
#definePTE_V 0x02
#definePTE_G 0x01
@@ -158,6 +160,7 @@ typedef pt_entry_t *pd_entry_t;
#definepte_clear(pte, bit) (*(pte) &= ~(bit))
#definepte_set(pte, bit) (*(pte) |= (bit))
#definepte_test(pte, bit) ((*(pte) & (bit)) == (bit))
+#definepte_cache_bits(pte) ((*(pte) >> 3) & 0x07)
/* Assembly support for PTE access*/
#ifdef LOCORE
Modified: head/sys/mips/include/vm.h
==
--- head/sys/mips/include/vm.h Tue Dec 27 23:56:46 2016(r310649)
+++ head/sys/mips/include/vm.h Wed Dec 28 02:55:26 2016(r310650)
@@ -32,7 +32,11 @@
#include
/* Memory attributes. */
-#defineVM_MEMATTR_UNCACHEAB
