Re: svn commit: r345158 - head/usr.sbin/bhyve

[Ed Maste]

On Thu, 14 Mar 2019 at 21:51, Marcelo Araujo  wrote:
>
> So there is some license concern around this patch, core@ reverted my first 
> attempt to import this patch from Illumos.

Conrad wrote the patch based on the description I posted on twitter,
it's not imported from anywhere.

However, I was not aware of the history here, and with a patch already
accepted in review we should take it; although the description of the
bug and the patch itself are both trivial there was clearly a
substantial effort involved in taking the bug to root cause.
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Re: svn commit: r345158 - head/usr.sbin/bhyve

[Marcelo Araujo]

Em sex, 15 de mar de 2019 às 05:09, Conrad Meyer  escreveu:

> Author: cem
> Date: Thu Mar 14 21:08:48 2019
> New Revision: 345158
> URL: https://svnweb.freebsd.org/changeset/base/345158
>
> Log:
>   bhyve(8): Fix uart emulation bug
>
>   THRE is always asserted in LSR reads, so REG_IER writes that raise
>   IER_ETXRDY must also set thre_int_pending.
>
>   Reported by:  Illumos, according to emaste@
> https://twitter.com/ed_maste/status/1106195949087584258
>   MFC after:2 weeks
>
> Modified:
>   head/usr.sbin/bhyve/uart_emul.c
>
> Modified: head/usr.sbin/bhyve/uart_emul.c
>
> ==
> --- head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 20:32:48 2019
> (r345157)
> +++ head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 21:08:48 2019
> (r345158)
> @@ -431,6 +431,9 @@ uart_write(struct uart_softc *sc, int offset, uint8_t
> sc->thre_int_pending = true;
> break;
> case REG_IER:
> +   /* Set pending when IER_ETXRDY is raised (edge-triggered).
> */
> +   if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) !=
> 0)
> +   sc->thre_int_pending = true;
> /*
>  * Apply mask so that bits 4-7 are 0
>  * Also enables bits 0-3 only if they're 1
>
>
Hi cem@,

FYI: https://svnweb.freebsd.org/base?view=revision=344057

So there is some license concern around this patch, core@ reverted my first
attempt to import this patch from Illumos.

I guess core@ will ping you soon to do the same.

There is a review made by the Illumos guys:
https://reviews.freebsd.org/D19499
Pending now bhyve maintainer to approve it.

Dark days, we had 2 committers trying to fix the same thing and our hands
are tied.


Best,
-- 

-- 
Marcelo Araujo(__)ara...@freebsd.org
\\\'',)http://www.FreeBSD.org    \/  \ ^
Power To Server. .\. /_)
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Re: svn commit: r345158 - head/usr.sbin/bhyve

[Rodney W. Grimes]

> Author: cem
> Date: Thu Mar 14 21:08:48 2019
> New Revision: 345158
> URL: https://svnweb.freebsd.org/changeset/base/345158
> 
> Log:
>   bhyve(8): Fix uart emulation bug
>   
>   THRE is always asserted in LSR reads, so REG_IER writes that raise
>   IER_ETXRDY must also set thre_int_pending.
>   
>   Reported by:Illumos, according to emaste@
>   https://twitter.com/ed_maste/status/1106195949087584258
>   MFC after:  2 weeks

Per MAINTAINERS this should of had a formal review.
And this is already in process from Patrick Mooney
via the bhyve developemnt group.
Revert this please.


> Modified:
>   head/usr.sbin/bhyve/uart_emul.c
> 
> Modified: head/usr.sbin/bhyve/uart_emul.c
> ==
> --- head/usr.sbin/bhyve/uart_emul.c   Thu Mar 14 20:32:48 2019
> (r345157)
> +++ head/usr.sbin/bhyve/uart_emul.c   Thu Mar 14 21:08:48 2019
> (r345158)
> @@ -431,6 +431,9 @@ uart_write(struct uart_softc *sc, int offset, uint8_t 
>   sc->thre_int_pending = true;
>   break;
>   case REG_IER:
> + /* Set pending when IER_ETXRDY is raised (edge-triggered). */
> + if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
> + sc->thre_int_pending = true;
>   /*
>* Apply mask so that bits 4-7 are 0
>* Also enables bits 0-3 only if they're 1

-- 
Rod Grimes rgri...@freebsd.org
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svn commit: r345158 - head/usr.sbin/bhyve

[Conrad Meyer]

Author: cem
Date: Thu Mar 14 21:08:48 2019
New Revision: 345158
URL: https://svnweb.freebsd.org/changeset/base/345158

Log:
  bhyve(8): Fix uart emulation bug
  
  THRE is always asserted in LSR reads, so REG_IER writes that raise
  IER_ETXRDY must also set thre_int_pending.
  
  Reported by:  Illumos, according to emaste@
https://twitter.com/ed_maste/status/1106195949087584258
  MFC after:2 weeks

Modified:
  head/usr.sbin/bhyve/uart_emul.c

Modified: head/usr.sbin/bhyve/uart_emul.c
==
--- head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 20:32:48 2019
(r345157)
+++ head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 21:08:48 2019
(r345158)
@@ -431,6 +431,9 @@ uart_write(struct uart_softc *sc, int offset, uint8_t 
sc->thre_int_pending = true;
break;
case REG_IER:
+   /* Set pending when IER_ETXRDY is raised (edge-triggered). */
+   if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
+   sc->thre_int_pending = true;
/*
 * Apply mask so that bits 4-7 are 0
 * Also enables bits 0-3 only if they're 1
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