Re: svn commit: r355444 - in head/sys: arm/mv arm64/conf conf
On Fri, Dec 6, 2019 at 12:57 PM Hans Petter Selasky wrote: > > On 2019-12-06 13:55, Luiz Otavio O Souza wrote: > > Author: loos > > Date: Fri Dec 6 12:55:39 2019 > > New Revision: 355444 > > URL: https://svnweb.freebsd.org/changeset/base/355444 > > > > Log: > >Add the SPI driver for the Marvell Armada 37x0 SoC. > > > >Interrupt based driver, implements SPI mode and clock configuration. > > > >Tested on espressobin and SG-3200. > > > >Sponsored by: Rubicon Communications, LLC (Netgate) > > > > Added: > > This breaks aarch64. You need to add #include Fixed in r355461. Sorry for the breakage. Luiz ___ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r355444 - in head/sys: arm/mv arm64/conf conf
On Fri, Dec 6, 2019 at 1:58 PM Ian Lepore wrote:
>
> On Fri, 2019-12-06 at 12:55 +, Luiz Otavio O Souza wrote:
> > Author: loos
> > Date: Fri Dec 6 12:55:39 2019
> > New Revision: 355444
> > URL: https://svnweb.freebsd.org/changeset/base/355444
> >
> > Log:
> > Add the SPI driver for the Marvell Armada 37x0 SoC.
> >
> > Interrupt based driver, implements SPI mode and clock configuration.
> >
> > Tested on espressobin and SG-3200.
> >
> > Sponsored by: Rubicon Communications, LLC (Netgate)
> >
> > Added:
> > head/sys/arm/mv/a37x0_spi.c (contents, props changed)
> > Modified:
> > head/sys/arm64/conf/GENERIC
> > head/sys/conf/files.arm64
> >
> > Added: head/sys/arm/mv/a37x0_spi.c
> >
> >
> > +static int
> > +a37x0_spi_detach(device_t dev)
> > +{
> > + struct a37x0_spi_softc *sc;
> > +
> > + bus_generic_detach(dev);
> >
>
> It's possible for detaching children to fail (like if one of them
> returns EBUSY from its detach), in which case you should bail on your
> detach and return the error status. Also, this needs a
> device_destroy_children() here after detaching them, to remove the
> spibus child added in attach (in case the module is unloaded then
> reloaded, that avoids adding a second copy of the child).
>
Fixed in r355461.
Thanks Ian.
Luiz
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Re: svn commit: r355444 - in head/sys: arm/mv arm64/conf conf
On Fri, 2019-12-06 at 12:55 +, Luiz Otavio O Souza wrote:
> Author: loos
> Date: Fri Dec 6 12:55:39 2019
> New Revision: 355444
> URL: https://svnweb.freebsd.org/changeset/base/355444
>
> Log:
> Add the SPI driver for the Marvell Armada 37x0 SoC.
>
> Interrupt based driver, implements SPI mode and clock configuration.
>
> Tested on espressobin and SG-3200.
>
> Sponsored by: Rubicon Communications, LLC (Netgate)
>
> Added:
> head/sys/arm/mv/a37x0_spi.c (contents, props changed)
> Modified:
> head/sys/arm64/conf/GENERIC
> head/sys/conf/files.arm64
>
> Added: head/sys/arm/mv/a37x0_spi.c
>
>
> +static int
> +a37x0_spi_detach(device_t dev)
> +{
> + struct a37x0_spi_softc *sc;
> +
> + bus_generic_detach(dev);
>
It's possible for detaching children to fail (like if one of them
returns EBUSY from its detach), in which case you should bail on your
detach and return the error status. Also, this needs a
device_destroy_children() here after detaching them, to remove the
spibus child added in attach (in case the module is unloaded then
reloaded, that avoids adding a second copy of the child).
-- Ian
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Re: svn commit: r355444 - in head/sys: arm/mv arm64/conf conf
On 2019-12-06 13:55, Luiz Otavio O Souza wrote: Author: loos Date: Fri Dec 6 12:55:39 2019 New Revision: 355444 URL: https://svnweb.freebsd.org/changeset/base/355444 Log: Add the SPI driver for the Marvell Armada 37x0 SoC. Interrupt based driver, implements SPI mode and clock configuration. Tested on espressobin and SG-3200. Sponsored by: Rubicon Communications, LLC (Netgate) Added: This breaks aarch64. You need to add #include somewhere: 13:30:54 ctfconvert -L VERSION -g bcm2835_rng.o 13:30:54 --- a37x0_spi.o --- 13:30:54 /usr/src/sys/arm/mv/a37x0_spi.c:212:2: error: implicit declaration of function 'mtx_init' is invalid in C99 [-Werror,-Wimplicit-function-declaration] 13:30:54 mtx_init(>sc_mtx, "a37x0_spi", NULL, MTX_DEF); 13:30:54 ^ 13:30:54 --- mv_ap806_gicp.o --- 13:30:54 cc -target aarch64-unknown-freebsd13.0 --sysroot=/usr/obj/usr/src/arm64.aarch64/tmp -B/usr/obj/usr/src/arm64.aarch64/tmp/usr/bin - https://ci.freebsd.org/tinderbox/ --HPS ___ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
svn commit: r355444 - in head/sys: arm/mv arm64/conf conf
Author: loos
Date: Fri Dec 6 12:55:39 2019
New Revision: 355444
URL: https://svnweb.freebsd.org/changeset/base/355444
Log:
Add the SPI driver for the Marvell Armada 37x0 SoC.
Interrupt based driver, implements SPI mode and clock configuration.
Tested on espressobin and SG-3200.
Sponsored by: Rubicon Communications, LLC (Netgate)
Added:
head/sys/arm/mv/a37x0_spi.c (contents, props changed)
Modified:
head/sys/arm64/conf/GENERIC
head/sys/conf/files.arm64
Added: head/sys/arm/mv/a37x0_spi.c
==
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/mv/a37x0_spi.c Fri Dec 6 12:55:39 2019(r355444)
@@ -0,0 +1,494 @@
+/*-
+ * Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include
+__FBSDID("$FreeBSD$");
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "spibus_if.h"
+
+struct a37x0_spi_softc {
+ device_tsc_dev;
+ struct mtx sc_mtx;
+ struct resource *sc_mem_res;
+ struct resource *sc_irq_res;
+ struct spi_command *sc_cmd;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ uint32_tsc_len;
+ uint32_tsc_maxfreq;
+ uint32_tsc_read;
+ uint32_tsc_flags;
+ uint32_tsc_written;
+ void*sc_intrhand;
+};
+
+#defineA37X0_SPI_WRITE(_sc, _off, _val)\
+bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
+#defineA37X0_SPI_READ(_sc, _off) \
+bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
+#defineA37X0_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
+#defineA37X0_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+
+#defineA37X0_SPI_BUSY (1 << 0)
+/*
+ * While the A3700 utils from Marvell usually sets the QSF clock to 200MHz,
+ * there is no guarantee that it is correct without the proper clock framework
+ * to retrieve the actual TBG and PLL settings.
+ */
+#defineA37X0_SPI_CLOCK 2 /* QSF Clock
200MHz */
+
+#defineA37X0_SPI_CONTROL 0x0
+#define A37X0_SPI_CS_SHIFT 16
+#define A37X0_SPI_CS_MASK (0xf << A37X0_SPI_CS_SHIFT)
+#defineA37X0_SPI_CONF 0x4
+#define A37X0_SPI_WFIFO_THRS_SHIFT 28
+#define A37X0_SPI_RFIFO_THRS_SHIFT 24
+#define A37X0_SPI_AUTO_CS_EN (1 << 20)
+#define A37X0_SPI_DMA_WR_EN(1 << 19)
+#define A37X0_SPI_DMA_RD_EN(1 << 18)
+#define A37X0_SPI_FIFO_MODE(1 << 17)
+#define A37X0_SPI_SRST (1 << 16)
+#define A37X0_SPI_XFER_START (1 << 15)
+#define A37X0_SPI_XFER_STOP(1 << 14)
+#define A37X0_SPI_INSTR_PIN(1 << 13)
+#define A37X0_SPI_ADDR_PIN (1 << 12)
+#define A37X0_SPI_DATA_PIN_MASK0x3
+#define A37X0_SPI_DATA_PIN_SHIFT 10
+#define A37X0_SPI_FIFO_FLUSH (1 << 9)
+#define A37X0_SPI_RW_EN(1 << 8)
+#define A37X0_SPI_CLK_POL (1 << 7)
+#define A37X0_SPI_CLK_PHASE(1 << 6)
+#define A37X0_SPI_BYTE_LEN (1 << 5)
+#define A37X0_SPI_PSC_MASK 0x1f
+#defineA37X0_SPI_DATA_OUT
