Re: more of em(4) support for iCH10 chip
On Jun 24, 2009, at 2:30 AM, Brad wrote:
On Fri, Jun 19, 2009 at 09:06:34PM -, sfi...@kefir.sfires.net
wrote:
hi,
following diff brings support for ICH10 R BM LF chip as well, basic
tests
done by matthew at dempsky org (thanks).
no changes to the code except for binging in new defines
(this is again a patch for my previous patch for i82574L
Here is a newer diff with a few more additions..
- Put in the rest of the missing ICH9 and ICH10 PCI id's.
- Some minor changes to deal with the BME1000 rev 2 PHY.
- The initial bits to deal with the em_ich10lan MAC for the
other ICH10 chipsets, which is similar to ICH8 / 9.
- Some minor formatting nits with the for loop in the
PHY probing code.
Please test if you have a system with an Ethernet chipset of
the model ICH9 BM or any ICH10 model.
hi, ill test it on my ICH10_R_BM_LF, unfotunatly i dont have any
ICH10_D_*
a few comments inline :)
Index: if_em.c
===
RCS file: /cvs/src/sys/dev/pci/if_em.c,v
retrieving revision 1.213
diff -u -p -r1.213 if_em.c
--- if_em.c 23 Jun 2009 14:09:51 - 1.213
+++ if_em.c 23 Jun 2009 23:42:10 -
@@ -132,13 +132,19 @@ const struct pci_matchid em_devices[] =
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M },
- { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }
};
/*
@@ -333,13 +339,15 @@ em_attach(struct device *parent, struct
case em_82574:
case em_82575:
case em_ich9lan:
- case em_80003es2lan:/* Limit Jumbo Frame size */
+ case em_ich10lan:
+ case em_80003es2lan:
+ /* Limit Jumbo Frame size */
sc->hw.max_frame_size = 9234;
break;
- /* Adapters that do not support Jumbo frames */
case em_82542_rev2_0:
case em_82542_rev2_1:
case em_ich8lan:
+ /* Adapters that do not support Jumbo frames */
sc->hw.max_frame_size = ETHER_MAX_LEN;
break;
default:
@@ -704,6 +712,7 @@ em_init(void *arg)
pba = E1000_PBA_8K;
break;
case em_ich9lan:
+ case em_ich10lan:
pba = E1000_PBA_10K;
break;
default:
@@ -1532,7 +1541,8 @@ em_allocate_pci_resources(struct em_soft
/* for ICH8 and family we need to find the flash memory */
if (sc->hw.mac_type == em_ich8lan ||
- sc->hw.mac_type == em_ich9lan) {
+ sc->hw.mac_type == em_ich9lan ||
+ sc->hw.mac_type == em_ich10lan) {
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH);
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
printf(": flash is not mem space\n");
Index: if_em_hw.c
===
RCS file: /cvs/src/sys/dev/pci/if_em_hw.c,v
retrieving revision 1.34
diff -u -p -r1.34 if_em_hw.c
--- if_em_hw.c 23 Jun 2009 14:09:51 - 1.34
+++ if_em_hw.c 24 Jun 2009 00:13:17 -
@@ -221,11 +221,9 @@ em_set_phy_type(struct em_hw *hw)
hw->phy_type = em_phy_ife;
break;
caseBME1000_E_PHY_ID:
-if (hw->phy_revision == 1) {
-hw->phy_type = em_phy_bm;
-break;
-}
-/* FALLTHROUGH */
+case BME1000_E_PHY_ID_R2:
+hw->phy_type = em_phy_bm;
+break;
using BME1000_E_PHY_ID_R2 is wrong imho.
BME1000_E_PHY_ID_R2 == (BME1000_E_PHY_ID and phy_revision==1)
intel put BME1000_E_PHY_ID_R2 ito their code, but if you look closely,
they have also rewriten the em_detect_gig_phy() (tey have two of them).
in the new routine they replaced:
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
with:
hw->phy_id |= (uint32_t) (phy_id_low);
which eaves revision number as a part of id, but since you didn't
c
Re: more of em(4) support for iCH10 chip
On Tue, Jun 23, 2009 at 6:15 PM, Brad wrote: > The 82574 diff already went in. Make sure your src tree is up to date. Got it, thanks. Patch works for me. OpenBSD 4.6-beta (GENERIC.MP) #2: Tue Jun 23 18:28:25 PDT 2009 r...@brick.dempsky.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 3180863488 (3033MB) avail mem = 3072495616 (2930MB) mainbus0 at root bios0 at mainbus0: SMBIOS rev. 2.4 @ 0xe8590 (56 entries) bios0: vendor Intel Corp. version "IDG4510H.86A.0101.2009.0526.1006" date 05/26/2009 bios0: Intel Corporation DG45ID acpi0 at bios0: rev 2 acpi0: tables DSDT FACP APIC MCFG ASF! HPET acpi0: wakeup devices P0P1(S3) UAR1(S3) UAR3(S5) P0P2(S3) USB0(S3) USB1(S3) USB2(S3) EUSB(S3) USB3(S3) USB4(S3) USBE(S3) PEX0(S4) PEX1(S4) PEX2(S4) PEX3(S4) PEX4(S4) GBE_(S4) USB5(S3) PWRB(S5) acpitimer0 at acpi0: 3579545 Hz, 24 bits acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz, 3000.02 MHz cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,SMX,EST,TM2,CX16,xTPR,NXE,LONG cpu0: 6MB 64b/line 16-way L2 cache cpu0: apic clock running at 333MHz cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz, 2999.66 MHz cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,SMX,EST,TM2,CX16,xTPR,NXE,LONG cpu1: 6MB 64b/line 16-way L2 cache ioapic0 at mainbus0 apid 0 pa 0xfec0, version 20, 24 pins acpihpet0 at acpi0: 14318179 Hz acpiprt0 at acpi0: bus 0 (PCI0) acpiprt1 at acpi0: bus 1 (P0P2) acpiprt2 at acpi0: bus -1 (PEX0) acpiprt3 at acpi0: bus -1 (PEX1) acpiprt4 at acpi0: bus -1 (PEX2) acpiprt5 at acpi0: bus -1 (PEX3) acpiprt6 at acpi0: bus -1 (PEX4) acpicpu0 at acpi0:, C3, C2, C1, PSS acpicpu1 at acpi0:, C3, C2, C1, PSS acpibtn0 at acpi0: PWRB cpu0: Enhanced SpeedStep 2999 MHz: speeds: 2997, 1998 MHz pci0 at mainbus0 bus 0 pchb0 at pci0 dev 0 function 0 "Intel G45 Host" rev 0x03 vga1 at pci0 dev 2 function 0 "Intel G45 Video" rev 0x03 wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation) wsdisplay0: screen 1-5 added (80x25, vt100 emulation) intagp0 at vga1 agp0 at intagp0: aperture at 0xc000, size 0x1000 inteldrm0 at vga1: apic 0 int 16 (irq 11) drm0 at inteldrm0 "Intel G45 Video" rev 0x03 at pci0 dev 2 function 1 not configured vendor "Intel", unknown product 0x2e24 (class communications subclass miscellaneous, rev 0x03) at pci0 dev 3 function 0 not configured em0 at pci0 dev 25 function 0 "Intel ICH10 R BM LF" rev 0x00: apic 0 int 20 (irq 10), address 00:1c:c0:9b:9f:f0 uhci0 at pci0 dev 26 function 0 "Intel 82801JI USB" rev 0x00: apic 0 int 16 (irq 11) uhci1 at pci0 dev 26 function 1 "Intel 82801JI USB" rev 0x00: apic 0 int 21 (irq 3) uhci2 at pci0 dev 26 function 2 "Intel 82801JI USB" rev 0x00: apic 0 int 18 (irq 11) ehci0 at pci0 dev 26 function 7 "Intel 82801JI USB" rev 0x00: apic 0 int 18 (irq 11) ehci0: timed out waiting for BIOS usb0 at ehci0: USB revision 2.0 uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1 azalia0 at pci0 dev 27 function 0 "Intel 82801JI HD Audio" rev 0x00: apic 0 int 22 (irq 10) azalia0: codecs: IDT 92HD73E1, Intel/0x2803, using IDT 92HD73E1 audio0 at azalia0 uhci3 at pci0 dev 29 function 0 "Intel 82801JI USB" rev 0x00: apic 0 int 23 (irq 3) uhci4 at pci0 dev 29 function 1 "Intel 82801JI USB" rev 0x00: apic 0 int 19 (irq 11) uhci5 at pci0 dev 29 function 2 "Intel 82801JI USB" rev 0x00: apic 0 int 18 (irq 11) ehci1 at pci0 dev 29 function 7 "Intel 82801JI USB" rev 0x00: apic 0 int 23 (irq 3) ehci1: timed out waiting for BIOS usb1 at ehci1: USB revision 2.0 uhub1 at usb1 "Intel EHCI root hub" rev 2.00/1.00 addr 1 ppb0 at pci0 dev 30 function 0 "Intel 82801BA Hub-to-PCI" rev 0x90 pci1 at ppb0 bus 1 dc0 at pci1 dev 0 function 0 "ADMtek AN983" rev 0x11: apic 0 int 21 (irq 3), address 00:08:a1:c0:30:54 ukphy0 at dc0 phy 1: Generic IEEE 802.3u media interface, rev. 1: OUI 0x000749, model 0x0001 "AT&T/Lucent FW322 1394" rev 0x70 at pci1 dev 1 function 0 not configured pcib0 at pci0 dev 31 function 0 "Intel 82801JIR LPC" rev 0x00 ahci0 at pci0 dev 31 function 2 "Intel 82801JI AHCI" rev 0x00: apic 0 int 19 (irq 11), AHCI 1.2 scsibus0 at ahci0: 32 targets sd0 at scsibus0 targ 0 lun 0: SCSI3 0/direct fixed sd0: 715404MB, 512 bytes/sec, 1465149168 sec total cd0 at scsibus0 targ 3 lun 0: ATAPI 5/cdrom removable ichiic0 at pci0 dev 31 function 3 "Intel 82801JI SMBus" rev 0x00: apic 0 int 18 (irq 11) iic0 at ichiic0 spdmem0 at iic0 addr 0x50: 2GB DDR2 SDRAM non-parity PC2-6400CL5 spdmem1 at iic0 addr 0x52: 2GB DDR2 SDRAM non-parity PC2-6400CL5 pciide0 at pci0 dev 31 function 5 "Intel 82801JI SATA" rev 0x00: DMA, channel 0 wired to native-PCI, channel 1 wired to native-PCI pciide0: using apic 0 int 19 (irq 11) for native-PCI interrupt usb2 at uhci0: USB revis
Re: more of em(4) support for iCH10 chip
On Tuesday 23 June 2009 21:13:02 Matthew Dempsky wrote: > On Tue, Jun 23, 2009 at 5:30 PM, Brad wrote: > > Here is a newer diff with a few more additions.. > > > > - Put in the rest of the missing ICH9 and ICH10 PCI id's. > > - Some minor changes to deal with the BME1000 rev 2 PHY. > > - The initial bits to deal with the em_ich10lan MAC for the > > other ICH10 chipsets, which is similar to ICH8 / 9. > > - Some minor formatting nits with the for loop in the > > PHY probing code. > > > > Please test if you have a system with an Ethernet chipset of > > the model ICH9 BM or any ICH10 model. > > Is this patch self-contained, or is it also dependent upon the 82574 patch? The 82574 diff already went in. Make sure your src tree is up to date. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
Re: more of em(4) support for iCH10 chip
On Tue, Jun 23, 2009 at 5:30 PM, Brad wrote: > Here is a newer diff with a few more additions.. > > - Put in the rest of the missing ICH9 and ICH10 PCI id's. > - Some minor changes to deal with the BME1000 rev 2 PHY. > - The initial bits to deal with the em_ich10lan MAC for the > other ICH10 chipsets, which is similar to ICH8 / 9. > - Some minor formatting nits with the for loop in the > PHY probing code. > > Please test if you have a system with an Ethernet chipset of > the model ICH9 BM or any ICH10 model. Is this patch self-contained, or is it also dependent upon the 82574 patch?
remove doubled error messages from ix(4) / ixgb(4).
As was done for em(4).. remove doubled error messages.
Index: if_ix.c
===
RCS file: /cvs/src/sys/dev/pci/if_ix.c,v
retrieving revision 1.18
diff -u -p -r1.18 if_ix.c
--- if_ix.c 4 Jun 2009 22:27:31 - 1.18
+++ if_ix.c 24 Jun 2009 00:43:36 -
@@ -206,10 +206,8 @@ ixgbe_attach(struct device *parent, stru
sc->rx_process_limit = 100; // XXX
/* Do base PCI setup - map BAR0 */
- if (ixgbe_allocate_pci_resources(sc)) {
- printf(": allocation of PCI resources failed\n");
+ if (ixgbe_allocate_pci_resources(sc))
goto err_out;
- }
/* Allocate our TX/RX Queues */
if (ixgbe_allocate_queues(sc))
Index: if_ixgb.c
===
RCS file: /cvs/src/sys/dev/pci/if_ixgb.c,v
retrieving revision 1.52
diff -u -p -r1.52 if_ixgb.c
--- if_ixgb.c 28 Nov 2008 02:44:18 - 1.52
+++ if_ixgb.c 24 Jun 2009 00:43:56 -
@@ -201,11 +201,8 @@ ixgb_attach(struct device *parent, struc
/* Set the max frame size assuming standard ethernet sized frames */
sc->hw.max_frame_size = IXGB_MAX_JUMBO_FRAME_SIZE;
- if (ixgb_allocate_pci_resources(sc)) {
- printf("%s: Allocation of PCI resources failed\n",
- sc->sc_dv.dv_xname);
+ if (ixgb_allocate_pci_resources(sc))
goto err_pci;
- }
tsize = IXGB_ROUNDUP(sc->num_tx_desc * sizeof(struct ixgb_tx_desc),
IXGB_MAX_TXD * sizeof(struct ixgb_tx_desc));
--
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Re: sparc hme(4) diff needs testing.
On Mon, Jun 22, 2009 at 11:02:57PM -0400, Brad wrote:
> Here is a diff for sparc's copy of the hme(4) driver to rewrite the ioctl
> handling code.
>
> Please test with hme(4) on sparc. Send a dmesg.
Looks like I forgot to re-diff after 1.59 was commited.
This is exactly the same but should now be able to apply against 1.59.
Index: hme.c
===
RCS file: /cvs/src/sys/arch/sparc/dev/hme.c,v
retrieving revision 1.59
diff -u -p -r1.59 hme.c
--- hme.c 20 Jun 2009 09:40:29 - 1.59
+++ hme.c 20 Jun 2009 10:26:54 -
@@ -248,7 +248,6 @@ hmeattach(parent, self, aux)
ifp->if_watchdog = hmewatchdog;
ifp->if_flags =
IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
- sc->sc_if_flags = ifp->if_flags;
ifp->if_capabilities = IFCAP_VLAN_MTU;
IFQ_SET_MAXLEN(&ifp->if_snd, HME_TX_RING_SIZE);
IFQ_SET_READY(&ifp->if_snd);
@@ -394,55 +393,24 @@ hmeioctl(ifp, cmd, data)
switch (cmd) {
case SIOCSIFADDR:
- switch (ifa->ifa_addr->sa_family) {
+ ifp->if_flags |= IFF_UP;
+ if (!(ifp->if_flags & IFF_RUNNING))
+ hmeinit(sc);
#ifdef INET
- case AF_INET:
- if (ifp->if_flags & IFF_UP)
- hme_mcreset(sc);
- else {
- ifp->if_flags |= IFF_UP;
- hmeinit(sc);
- }
+ if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
- break;
-#endif /* INET */
- default:
- ifp->if_flags |= IFF_UP;
- hmeinit(sc);
- break;
- }
+#endif
break;
case SIOCSIFFLAGS:
- if ((ifp->if_flags & IFF_UP) == 0 &&
- (ifp->if_flags & IFF_RUNNING) != 0) {
- /*
-* If interface is marked down and it is running, then
-* stop it.
-*/
- hmestop(sc);
- } else if ((ifp->if_flags & IFF_UP) != 0 &&
- (ifp->if_flags & IFF_RUNNING) == 0) {
- /*
-* If interface is marked up and it is stopped, then
-* start it.
-*/
- hmeinit(sc);
- } else {
- /*
-* If setting debug or promiscuous mode, do not reset
-* the chip; for everything else, call hmeinit()
-* which will trigger a reset.
-*/
-#define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG)
- if (ifp->if_flags == sc->sc_if_flags)
- break;
- if ((ifp->if_flags & (~RESETIGN))
- == (sc->sc_if_flags & (~RESETIGN)))
- hme_mcreset(sc);
+ if (ifp->if_flags & IFF_UP) {
+ if (ifp->if_flags & IFF_RUNNING)
+ error = ENETRESET;
else
hmeinit(sc);
-#undef RESETIGN
+ } else {
+ if (ifp->if_flags & IFF_RUNNING)
+ hmestop(sc);
}
break;
@@ -461,7 +429,6 @@ hmeioctl(ifp, cmd, data)
error = 0;
}
- sc->sc_if_flags = ifp->if_flags;
splx(s);
return (error);
}
@@ -605,7 +572,6 @@ hmeinit(sc)
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
- sc->sc_if_flags = ifp->if_flags;
}
void
@@ -1230,5 +1196,4 @@ hme_mii_statchg(self)
cr->tx_cfg &= ~CR_TXCFG_FULLDPLX;
sc->sc_arpcom.ac_if.if_flags &= ~IFF_SIMPLEX;
}
- sc->sc_if_flags = sc->sc_arpcom.ac_if.if_flags;
}
Index: hmevar.h
===
RCS file: /cvs/src/sys/arch/sparc/dev/hmevar.h,v
retrieving revision 1.12
diff -u -p -r1.12 hmevar.h
--- hmevar.h2 Jun 2006 20:00:54 - 1.12
+++ hmevar.h20 Jun 2009 10:13:54 -
@@ -49,8 +49,6 @@ struct hme_softc {
u_int32_t sc_flags; /* status flags */
- short sc_if_flags;
-
/*
* RX/TX ring buffers, descriptors, and counters
*/
--
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Re: more of em(4) support for iCH10 chip
On Fri, Jun 19, 2009 at 09:06:34PM -, sfi...@kefir.sfires.net wrote:
> hi,
>
> following diff brings support for ICH10 R BM LF chip as well, basic tests
> done by matthew at dempsky org (thanks).
> no changes to the code except for binging in new defines
>
> (this is again a patch for my previous patch for i82574L
Here is a newer diff with a few more additions..
- Put in the rest of the missing ICH9 and ICH10 PCI id's.
- Some minor changes to deal with the BME1000 rev 2 PHY.
- The initial bits to deal with the em_ich10lan MAC for the
other ICH10 chipsets, which is similar to ICH8 / 9.
- Some minor formatting nits with the for loop in the
PHY probing code.
Please test if you have a system with an Ethernet chipset of
the model ICH9 BM or any ICH10 model.
Index: if_em.c
===
RCS file: /cvs/src/sys/dev/pci/if_em.c,v
retrieving revision 1.213
diff -u -p -r1.213 if_em.c
--- if_em.c 23 Jun 2009 14:09:51 - 1.213
+++ if_em.c 23 Jun 2009 23:42:10 -
@@ -132,13 +132,19 @@ const struct pci_matchid em_devices[] =
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M },
- { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }
};
/*
@@ -333,13 +339,15 @@ em_attach(struct device *parent, struct
case em_82574:
case em_82575:
case em_ich9lan:
- case em_80003es2lan:/* Limit Jumbo Frame size */
+ case em_ich10lan:
+ case em_80003es2lan:
+ /* Limit Jumbo Frame size */
sc->hw.max_frame_size = 9234;
break;
- /* Adapters that do not support Jumbo frames */
case em_82542_rev2_0:
case em_82542_rev2_1:
case em_ich8lan:
+ /* Adapters that do not support Jumbo frames */
sc->hw.max_frame_size = ETHER_MAX_LEN;
break;
default:
@@ -704,6 +712,7 @@ em_init(void *arg)
pba = E1000_PBA_8K;
break;
case em_ich9lan:
+ case em_ich10lan:
pba = E1000_PBA_10K;
break;
default:
@@ -1532,7 +1541,8 @@ em_allocate_pci_resources(struct em_soft
/* for ICH8 and family we need to find the flash memory */
if (sc->hw.mac_type == em_ich8lan ||
- sc->hw.mac_type == em_ich9lan) {
+ sc->hw.mac_type == em_ich9lan ||
+ sc->hw.mac_type == em_ich10lan) {
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH);
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
printf(": flash is not mem space\n");
Index: if_em_hw.c
===
RCS file: /cvs/src/sys/dev/pci/if_em_hw.c,v
retrieving revision 1.34
diff -u -p -r1.34 if_em_hw.c
--- if_em_hw.c 23 Jun 2009 14:09:51 - 1.34
+++ if_em_hw.c 24 Jun 2009 00:13:17 -
@@ -221,11 +221,9 @@ em_set_phy_type(struct em_hw *hw)
hw->phy_type = em_phy_ife;
break;
case BME1000_E_PHY_ID:
-if (hw->phy_revision == 1) {
-hw->phy_type = em_phy_bm;
-break;
-}
-/* FALLTHROUGH */
+case BME1000_E_PHY_ID_R2:
+hw->phy_type = em_phy_bm;
+break;
case GG82563_E_PHY_ID:
if (hw->mac_type == em_80003es2lan) {
hw->phy_type = em_phy_gg82563;
@@ -475,6 +473,7 @@ em_set_mac_type(struct em_hw *hw)
case E1000_DEV_ID_ICH8_IGP_M_AMT:
hw->mac_type = em_ich8lan;
break;
+case E1000_DEV_ID_ICH9_BM:
case E1000_DEV_ID_ICH9_IFE:
case E1000_DEV_ID_ICH9_IFE_G:
case E1000_DEV_ID_ICH9_IFE_GT:
@@ -482,8 +481,15 @@ em_set_mac_type(struct em_hw *hw)
case E1000_DEV_ID_ICH9_IGP_C:
case E1000_DEV_ID_ICH9_IGP_M:
case E1000_DEV_ID_ICH9_IGP_M_AMT:
+case E1000_DEV_ID
cwm - handle the PAspect flag
This diff supersedes
http://marc.info/?l=openbsd-bugs&m=124471413424140
and attempts to handle the PAspect flag.
The output of
egrep '__int(32|64)_t;' /usr/src/sys/arch/*/include/_types.h
seems to indicate that 'long long' is twice as big as 'int' on all
supported platforms. The code relies on that to prevent arithmetic
overflow.
Comments?
I grant this diff to the public domain.
Index: mousefunc.c
===
RCS file: /cvs/xenocara/app/cwm/mousefunc.c,v
retrieving revision 1.12
diff -u -r1.12 mousefunc.c
--- mousefunc.c 20 Jun 2009 00:55:42 - 1.12
+++ mousefunc.c 23 Jun 2009 17:38:42 -
@@ -25,6 +25,42 @@
static int mousefunc_sweep_calc(struct client_ctx *, int, int, int, int);
static voidmousefunc_sweep_draw(struct client_ctx *);
+/* greater-than for fractions of ints with positive denominator */
+#define GTF(a,b, c,d) ((long long)(a) * (d) > (long long)(b) * (c))
+
+/* ceiling(a/b), if a>0 and b>0 */
+#define CEILDIV(a, b) a) - 1) / (b)) + 1)
+
+static void
+aspect_calc(int *wp, int *hp, int fl, int wi, int hi,
+ int a, int b, int c, int d)
+{
+ int w = *wp, h = *hp, n;
+
+ if (!fl || wi < 1)
+ wi = 1;
+ if (!fl || hi < 1)
+ hi = 1;
+ if (w < 1 || h < 1 || a < 1 || b < 1 || c < 1 || d < 1 ||
+ GTF(a,b, c,d))
+ return;
+ if (GTF(a,b, w,h)) {
+ /* the least n such that a/b <= (w + n*wi)/h */
+ n = CEILDIV(CEILDIV((long long)h * a, b) - w, wi);
+ w += n * wi;
+ if (GTF(w,h, c,d))
+ w -= wi;
+ *wp = w;
+ } else if (GTF(w,h, c,d)) {
+ /* the least n such that w/(h + n*hi) <= c/d */
+ n = CEILDIV(CEILDIV((long long)w * d, c) - h, hi);
+ h += n * hi;
+ if (GTF(a,b, w,h))
+ h -= hi;
+ *hp = h;
+ }
+}
+
static int
mousefunc_sweep_calc(struct client_ctx *cc, int x, int y, int mx, int my)
{
@@ -39,6 +75,13 @@
cc->geom.height -=
(cc->geom.height - cc->geom.min_dy) % cc->size->height_inc;
}
+
+ if (cc->size->flags & PAspect)
+ aspect_calc(&cc->geom.width, &cc->geom.height,
+ (cc->size->flags & PResizeInc) != 0,
+ cc->size->width_inc, cc->size->height_inc,
+ cc->size->min_aspect.x, cc->size->min_aspect.y,
+ cc->size->max_aspect.x, cc->size->max_aspect.y);
if (cc->size->flags & PMinSize) {
cc->geom.width = MAX(cc->geom.width, cc->size->min_width);
Re: USB patch for ATI SB600 / SB700 chipsets needs testing.
On Tue, Jun 23, 2009 at 06:17:37AM -0400, Brad wrote:
> On Tue, Jun 23, 2009 at 05:06:19AM -0400, Brad wrote:
> > The following diff for the ATI SB600 / SB700 chipsets needs testing
> > with the EHCI controller. There is a temporary printf to see when the
> > workaround is being applied.
> >
> > Attached patch is intended to avoid USB subsystem hang symptoms on
> > all ATI SB600 revisions and ATI SB700 south bridge revisions A12 and A13.
> >
> > The USB subsystem hang symptom is observed when the system has multiple
> > USB devices connected to it. In some cases a USB hub may be required to
> > observe this symptom.
> >
> > This patch works around the problem by correcting the internal register
> > setting that will help by changing the behavior of the internal logic to
> > avoid the USB subsystem hang issue. The change in the behavior of the
> > logic does not impact the normal operation of the USB subsystem.
> >
> > From NetBSD (also in Linux)
>
> Ok well as kettenis pointed out the previous diff was a bit overkill
> for infrastructure to do the job.. this is much simpler.
And a little simpler over the second rev..
Index: ehci_pci.c
===
RCS file: /cvs/src/sys/dev/pci/ehci_pci.c,v
retrieving revision 1.15
diff -u -p -r1.15 ehci_pci.c
--- ehci_pci.c 29 Mar 2009 21:53:52 - 1.15
+++ ehci_pci.c 23 Jun 2009 11:24:17 -
@@ -65,6 +65,11 @@ struct ehci_pci_softc {
void*sc_ih; /* interrupt vectoring */
};
+int ehci_sb700_match(struct pci_attach_args *pa);
+
+#define EHCI_SBx00_WORKAROUND_REG 0x50
+#define EHCI_SBx00_WORKAROUND_ENABLE (1 << 3)
+
intehci_pci_match(struct device *, void *, void *);
void ehci_pci_attach(struct device *, struct device *, void *);
intehci_pci_detach(struct device *, int);
@@ -77,7 +82,6 @@ struct cfattach ehci_pci_ca = {
ehci_pci_detach, ehci_activate
};
-
int
ehci_pci_match(struct device *parent, void *match, void *aux)
{
@@ -122,6 +126,21 @@ ehci_pci_attach(struct device *parent, s
DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs));
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
+ /* Handle quirks */
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
+ ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_EHCI ||
+ (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB700_EHCI &&
+ pci_find_device(NULL, ehci_sb700_match) {
+ pcireg_t value;
+
+ printf(", applying ATI SB600/SB700 workaround");
+ value = pci_conf_read(sc->sc_pc, sc->sc_tag,
+ EHCI_SBx00_WORKAROUND_REG);
+ pci_conf_write(sc->sc_pc, sc->sc_tag,
+ EHCI_SBx00_WORKAROUND_REG, value |
+ EHCI_SBx00_WORKAROUND_ENABLE);
+ }
+
/* Map and establish the interrupt. */
if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
@@ -270,4 +289,16 @@ ehci_pci_shutdown(void *v)
/* best not to do this anymore; BIOS SMM spins? */
ehci_pci_givecontroller(sc);
#endif
+}
+
+int
+ehci_sb700_match(struct pci_attach_args *pa)
+{
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB &&
+ (PCI_REVISION(pa->pa_class) == 0x3a ||
+PCI_REVISION(pa->pa_class) == 0x3b))
+ return (1);
+
+ return (0);
}
--
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Re: Request for help identifying NIC's attached to Northbridge
I've tried 4.5 current and 4.6 beta with acpi enabled. No joy. Here is
a dmesg from 4.6 beta.
OpenBSD 4.6-beta (GENERIC) #9: Sun Jun 21 08:38:08 MDT 2009
t...@i386.openbsd.org:/usr/src/sys/arch/i386/compile/GENERIC
cpu0: VIA Esther processor 1500MHz ("CentaurHauls" 686-class) 1.50 GHz
cpu0:
FPU,V86,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,CMOV,PAT,CFLUSH,ACP
I,MMX,FXSR,SSE,SSE2,TM,SBF,SSE3,EST,TM2
real mem = 937586688 (894MB)
avail mem = 897839104 (856MB)
mainbus0 at root
bios0 at mainbus0: AT/286+ BIOS, date 01/17/08, BIOS32 rev. 0 @ 0xfb0b0,
SMBIOS rev. 2.3 @ 0xf (30 entries)
bios0: vendor Phoenix Technologies, LTD version "6.00 PG" date
01/17/2008
bios0: VIA Technologies Ltd. CN896-8251
apm at bios0 function 0x15 not configured
acpi0 at bios0: rev 0
acpi0: tables DSDT FACP MCFG APIC
acpi0: wakeup devices SLPB(S5) PCI0(S5) SATA(S1) USB1(S3) USB2(S3)
USB3(S3) USB4(S3) EHCI(S3) PEXG(S5) PEX0(S5) PEX1(S5) PEX2(S5) PEX3(S5)
PE5C(S5) PE6C(S5) P2PB(S5) UAR1(S5) PE5C(S5) PE6C(S5)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: RNG AES AES-CTR SHA1 SHA256 RSA
cpu0: apic clock running at 99MHz
ioapic0 at mainbus0: apid 2 pa 0xfec0, version 3, 24 pins
ioapic1 at mainbus0: apid 3 pa 0xfecc, version 3, 24 pins
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 2 (PEXG)
acpiprt2 at acpi0: bus 3 (PEX0)
acpiprt3 at acpi0: bus 4 (P2PB)
acpiprt4 at acpi0: bus 128 (PCI1)
acpiprt5 at acpi0: bus 129 (PE5C)
acpiprt6 at acpi0: bus 130 (PE6C)
acpicpu0 at acpi0
acpitz0 at acpi0: critical temperature 130 degC
acpibtn0 at acpi0: PWRB
acpibtn1 at acpi0: SLPB
bios0: ROM list: 0xc/0x9c00 0xcc000/0x4000!
cpu0: unknown Enhanced SpeedStep CPU, msr 0x08100f1308000f13
cpu0: using only highest and lowest power states
cpu0: Enhanced SpeedStep 1497 MHz: speeds: 1500, 800 MHz
pci0 at mainbus0 bus 0: configuration mode 1 (bios)
pchb0 at pci0 dev 0 function 0 "VIA P4M900 Host" rev 0x00
viaagp0 at pchb0: v3
agp0 at viaagp0: aperture at 0xd000, size 0x1000
pchb1 at pci0 dev 0 function 1 "VIA P4M900 Host" rev 0x00
pchb2 at pci0 dev 0 function 2 "VIA P4M900 Host" rev 0x00
pchb3 at pci0 dev 0 function 3 "VIA P4M900 Host" rev 0x00
pchb4 at pci0 dev 0 function 4 "VIA P4M900 Host" rev 0x00
"VIA P4M900 IOAPIC" rev 0x00 at pci0 dev 0 function 5 not configured
pchb5 at pci0 dev 0 function 6 "VIA P4M900 Security" rev 0x00
pchb6 at pci0 dev 0 function 7 "VIA P4M900 Host" rev 0x00
ppb0 at pci0 dev 1 function 0 "VIA VT8377 AGP" rev 0x00
pci1 at ppb0 bus 1
vga1 at pci1 dev 0 function 0 "VIA Chrome9 HC IGP" rev 0x01
wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation)
wsdisplay0: screen 1-5 added (80x25, vt100 emulation)
ppb1 at pci0 dev 2 function 0 "VIA P4M900 PCI-PCI" rev 0x80: apic 3 int
3 (irq 5)
pci2 at ppb1 bus 2
vge0 at pci2 dev 0 function 0 "VIA VT612x" rev 0x82: apic 3 int 0 (irq
5), address 00:40:63:f5:79:8e
ukphy0 at vge0 phy 22: Generic IEEE 802.3u media interface, rev. 0: OUI
0x0090c3, model 0x0019
ppb2 at pci0 dev 3 function 0 "VIA P4M900 PCI-PCI" rev 0x80: apic 3 int
7 (irq 5)
pci3 at ppb2 bus 3
vge1 at pci3 dev 0 function 0 "VIA VT612x" rev 0x82: apic 3 int 4 (irq
5), address 00:40:63:f5:79:91
ukphy1 at vge1 phy 22: Generic IEEE 802.3u media interface, rev. 0: OUI
0x0090c3, model 0x0019
pciide0 at pci0 dev 15 function 0 "VIA VT8251 SATA" rev 0x20: DMA
pciide0: using apic 2 int 21 (irq 11) for native-PCI interrupt
atapiscsi0 at pciide0 channel 0 drive 0
scsibus0 at atapiscsi0: 2 targets
cd0 at scsibus0 targ 0 lun 0: ATAPI
5/cdrom removable
cd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 5
pciide1 at pci0 dev 15 function 1 "VIA VT82C571 IDE" rev 0x07: DMA,
channel 0 configured to compatibility, channel 1 configured to
compatibility
wd0 at pciide1 channel 0 drive 0:
wd0: 4-sector PIO, LBA, 1953MB, 4001760 sectors
wd0(pciide1:0:0): using PIO mode 4, DMA mode 2
pciide1: channel 1 ignored (disabled)
uhci0 at pci0 dev 16 function 0 "VIA VT83C572 USB" rev 0x91: apic 2 int
20 (irq 10)
uhci1 at pci0 dev 16 function 1 "VIA VT83C572 USB" rev 0x91: apic 2 int
22 (irq 6)
uhci2 at pci0 dev 16 function 2 "VIA VT83C572 USB" rev 0x91: apic 2 int
21 (irq 11)
uhci3 at pci0 dev 16 function 3 "VIA VT83C572 USB" rev 0x91: apic 2 int
23 (irq 7)
ehci0 at pci0 dev 16 function 4 "VIA VT6202 USB" rev 0x90: apic 2 int 22
(irq 6)
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "VIA EHCI root hub" rev 2.00/1.00 addr 1
viapm0 at pci0 dev 17 function 0 "VIA VT8251 ISA" rev 0x00
iic0 at viapm0
spdmem0 at iic0 addr 0x50: 512MB DDR2 SDRAM non-parity PC2-5300CL5
spdmem1 at iic0 addr 0x51: 512MB DDR2 SDRAM non-parity PC2-5300CL5
pchb7 at pci0 dev 17 function 7 "VIA VT8251 VLINK" rev 0x00
pchb8 at pci0 dev 19 function 0 "VIA VT8251 PCIE" rev 0x00
ppb3 at pci0 dev 19 function 1 "VIA VT8251 PCI" rev 0x00
pci4 at ppb3 bus 4
vge2 at pci4 dev 14 function 0 "VIA VT612x" rev 0x11: apic 2 int 19 (irq
7), address 00:40:63:f5:79:6f
ciphy0 at vge2 phy 1: CS
Re: USB patch for ATI SB600 / SB700 chipsets needs testing.
On Tue, Jun 23, 2009 at 05:06:19AM -0400, Brad wrote:
> The following diff for the ATI SB600 / SB700 chipsets needs testing
> with the EHCI controller. There is a temporary printf to see when the
> workaround is being applied.
>
> Attached patch is intended to avoid USB subsystem hang symptoms on
> all ATI SB600 revisions and ATI SB700 south bridge revisions A12 and A13.
>
> The USB subsystem hang symptom is observed when the system has multiple
> USB devices connected to it. In some cases a USB hub may be required to
> observe this symptom.
>
> This patch works around the problem by correcting the internal register
> setting that will help by changing the behavior of the internal logic to
> avoid the USB subsystem hang issue. The change in the behavior of the
> logic does not impact the normal operation of the USB subsystem.
>
> From NetBSD (also in Linux)
Ok well as kettenis pointed out the previous diff was a bit overkill
for infrastructure to do the job.. this is much simpler.
Index: ehci_pci.c
===
RCS file: /cvs/src/sys/dev/pci/ehci_pci.c,v
retrieving revision 1.15
diff -u -p -r1.15 ehci_pci.c
--- ehci_pci.c 29 Mar 2009 21:53:52 - 1.15
+++ ehci_pci.c 23 Jun 2009 10:12:16 -
@@ -65,6 +65,12 @@ struct ehci_pci_softc {
void*sc_ih; /* interrupt vectoring */
};
+int ehci_sb700_match(struct pci_attach_args *pa);
+int ehci_apply_ati_quirks(struct ehci_pci_softc *sc);
+
+#define EHCI_SBx00_WORKAROUND_REG 0x50
+#define EHCI_SBx00_WORKAROUND_ENABLE (1 << 3)
+
intehci_pci_match(struct device *, void *, void *);
void ehci_pci_attach(struct device *, struct device *, void *);
intehci_pci_detach(struct device *, int);
@@ -77,7 +83,6 @@ struct cfattach ehci_pci_ca = {
ehci_pci_detach, ehci_activate
};
-
int
ehci_pci_match(struct device *parent, void *match, void *aux)
{
@@ -122,6 +127,19 @@ ehci_pci_attach(struct device *parent, s
DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs));
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
+ /* Handle quirks */
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI) {
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_ATI_SB600_EHCI:
+ ehci_apply_ati_quirks(sc);
+ break;
+ case PCI_PRODUCT_ATI_SB700_EHCI:
+ if (pci_find_device(NULL, ehci_sb700_match))
+ ehci_apply_ati_quirks(sc);
+ break;
+ }
+ }
+
/* Map and establish the interrupt. */
if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
@@ -270,4 +288,30 @@ ehci_pci_shutdown(void *v)
/* best not to do this anymore; BIOS SMM spins? */
ehci_pci_givecontroller(sc);
#endif
+}
+
+int
+ehci_sb700_match(struct pci_attach_args *pa)
+{
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB &&
+ (PCI_REVISION(pa->pa_class) == 0x3a ||
+PCI_REVISION(pa->pa_class) == 0x3b))
+ return (1);
+
+ return (0);
+}
+
+int
+ehci_apply_ati_quirks(struct ehci_pci_softc *sc)
+{
+ pcireg_t value;
+
+ printf(", applying ATI SB600/SB700 workaround");
+ value = pci_conf_read(sc->sc_pc, sc->sc_tag,
+ EHCI_SBx00_WORKAROUND_REG);
+ pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
+ value | EHCI_SBx00_WORKAROUND_ENABLE);
+
+ return (0);
}
--
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USB patch for ATI SB600 / SB700 chipsets needs testing.
The following diff for the ATI SB600 / SB700 chipsets needs testing
with the EHCI controller. There is a temporary printf to see when the
workaround is being applied.
Attached patch is intended to avoid USB subsystem hang symptoms on
all ATI SB600 revisions and ATI SB700 south bridge revisions A12 and A13.
The USB subsystem hang symptom is observed when the system has multiple
USB devices connected to it. In some cases a USB hub may be required to
observe this symptom.
This patch works around the problem by correcting the internal register
setting that will help by changing the behavior of the internal logic to
avoid the USB subsystem hang issue. The change in the behavior of the
logic does not impact the normal operation of the USB subsystem.
>From NetBSD (also in Linux)
Index: ehci_pci.c
===
RCS file: /cvs/src/sys/dev/pci/ehci_pci.c,v
retrieving revision 1.15
diff -u -p -r1.15 ehci_pci.c
--- ehci_pci.c 29 Mar 2009 21:53:52 - 1.15
+++ ehci_pci.c 23 Jun 2009 08:48:36 -
@@ -58,6 +58,18 @@ extern int ehcidebug;
#define DPRINTF(x)
#endif
+enum ehci_pci_quirk_flags {
+ EHCI_PCI_QUIRK_ATI_SB600 = 0x1, /* always need a quirk */
+ EHCI_PCI_QUIRK_ATI_SB700 = 0x2, /* depends on the SMB revision */
+};
+
+static const struct pci_quirkdata ehci_pci_quirks[] = {
+ { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_EHCI,
+ EHCI_PCI_QUIRK_ATI_SB600 },
+ { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_EHCI,
+ EHCI_PCI_QUIRK_ATI_SB700 },
+};
+
struct ehci_pci_softc {
ehci_softc_tsc;
pci_chipset_tag_t sc_pc;
@@ -65,6 +77,14 @@ struct ehci_pci_softc {
void*sc_ih; /* interrupt vectoring */
};
+int ehci_sb700_match(struct pci_attach_args *pa);
+int ehci_apply_ati_quirks(struct ehci_pci_softc *sc);
+enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
+ pci_product_id_t);
+
+#define EHCI_SBx00_WORKAROUND_REG 0x50
+#define EHCI_SBx00_WORKAROUND_ENABLE (1 << 3)
+
intehci_pci_match(struct device *, void *, void *);
void ehci_pci_attach(struct device *, struct device *, void *);
intehci_pci_detach(struct device *, int);
@@ -77,7 +97,6 @@ struct cfattach ehci_pci_ca = {
ehci_pci_detach, ehci_activate
};
-
int
ehci_pci_match(struct device *parent, void *match, void *aux)
{
@@ -103,7 +122,11 @@ ehci_pci_attach(struct device *parent, s
const char *vendor;
char *devname = sc->sc.sc_bus.bdev.dv_xname;
usbd_status r;
- int s;
+ int quirk, s;
+
+ /* Check for quirks */
+ quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
+ PCI_PRODUCT(pa->pa_id));
/* Map I/O registers */
if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
@@ -122,6 +145,17 @@ ehci_pci_attach(struct device *parent, s
DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs));
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
+ /* Handle quirks */
+ switch (quirk) {
+ case EHCI_PCI_QUIRK_ATI_SB600:
+ ehci_apply_ati_quirks(sc);
+ break;
+ case EHCI_PCI_QUIRK_ATI_SB700:
+ if (pci_find_device(NULL, ehci_sb700_match))
+ ehci_apply_ati_quirks(sc);
+ break;
+ }
+
/* Map and establish the interrupt. */
if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
@@ -270,4 +304,48 @@ ehci_pci_shutdown(void *v)
/* best not to do this anymore; BIOS SMM spins? */
ehci_pci_givecontroller(sc);
#endif
+}
+
+int
+ehci_sb700_match(struct pci_attach_args *pa)
+{
+ if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB))
+ return (0);
+
+ switch (PCI_REVISION(pa->pa_class)) {
+ case 0x3a:
+ case 0x3b:
+ return (1);
+ }
+
+ return (0);
+}
+
+int
+ehci_apply_ati_quirks(struct ehci_pci_softc *sc)
+{
+ pcireg_t value;
+
+ printf(", applying ATI SB600/SB700 workaround");
+ value = pci_conf_read(sc->sc_pc, sc->sc_tag,
+ EHCI_SBx00_WORKAROUND_REG);
+ pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
+ value | EHCI_SBx00_WORKAROUND_ENABLE);
+
+ return (0);
+}
+
+enum ehci_pci_quirk_flags
+ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
+{
+ int i;
+
+ for (i = 0; i < nitems(ehci_pci_quirks); i++) {
+ if (vendor == ehci_pci_quirks[i].vendor &&
+ product == ehci_pci_quirks[i].product)
+ return (ehci_pci_quirks[i].quirks);
+ }
+
+ return (0);
}
--
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believed to be clean.
Re: azalia: use line out jack colors in mixer names
On Tuesday 23 June 2009 03.39.55 Jacob Meuser wrote: > this is looking good but more test reports are always nice. It is working okay here. ThinkPad T60. [...] azalia0 at pci0 dev 27 function 0 "Intel 82801GB HD Audio" rev 0x02: apic 1 int 17 (irq 11 ) azalia0: RIRB time out azalia0: codecs: Analog Devices AD1981HD, 0x/0x, using Analog Devices AD1981HD azalia0: RIRB time out audio0 at azalia0 [...] -- LIVAI Daniel PGP key ID = 0x4AC0A4B1 Key fingerprint = D037 03B9 C12D D338 4412 2D83 1373 917A 4AC0 A4B1
Re: cwm(1): exec globbing
On Wed, 17 Jun 2009 11:50:55 +0200
Thomas Pfaff wrote:
> This diff adds globbing to the exec function so you can type e.g.
> *ctl and get a list of all executable files that ends with ctl.
So, what's the verdict on this one? The fnmatch lookup is case-
sensitive but I think that makes sense; if you use wildcards it
means you want your search to be more specific.
> Index: search.c
> ===
> RCS file: /cvs/OpenBSD/xenocara/app/cwm/search.c,v
> retrieving revision 1.1.1.1
> diff -u -p -r1.1.1.1 search.c
> --- search.c 17 Jun 2009 09:18:34 - 1.1.1.1
> +++ search.c 17 Jun 2009 09:48:17 -
> @@ -17,6 +17,7 @@
> * $Id: search.c,v 1.15 2009/05/18 00:23:35 okan Exp $
> */
>
> +#include
> #include "headers.h"
> #include "calmwm.h"
>
> @@ -181,7 +182,8 @@ search_match_exec(struct menu_q *menuq,
>
> TAILQ_FOREACH(mi, menuq, entry) {
> if (strsubmatch(search, mi->text, 1) == 0)
> - continue;
> + if (fnmatch(search, mi->text, 0) == FNM_NOMATCH)
> + continue;
> for (mj = TAILQ_FIRST(resultq); mj != NULL;
>mj = TAILQ_NEXT(mj, resultentry)) {
> if (strcasecmp(mi->text, mj->text) < 0) {
Re: azalia(4) diff needs testing.
On Tue, 23 Jun 2009 01:42:49 + Jacob Meuser wrote: > On Sun, Jun 21, 2009 at 01:07:37AM +, Jacob Meuser wrote: > > > > Please test the following diff with any azalia(4) adapter, but > > > > especially > > > > with any ATI or NVIDIA chipsets. Make sure sound still works properly > > > > without any unusual sound artifacts. > > haven't gotten much feedback on this one ... > Works for me. OpenBSD 4.6-beta (GENERIC.MP) #11: Tue Jun 23 08:56:12 CEST 2009 tpf...@ws.tp76.info:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 3152609280 (3006MB) avail mem = 3044945920 (2903MB) mainbus0 at root bios0 at mainbus0: SMBIOS rev. 2.4 @ 0xf06b0 (76 entries) bios0: vendor American Megatrends Inc. version "1704" date 11/27/2007 bios0: ASUSTeK Computer INC. P5B-E acpi0 at bios0: rev 2 acpi0: tables DSDT FACP APIC MCFG OEMB HPET acpi0: wakeup devices P0P2(S4) P0P1(S4) UAR1(S4) PS2K(S4) PS2M(S4) EUSB(S4) USBE(S4) P0P4(S4) P0P5(S4) P0P6(S4) P0P7(S4) P0P8(S4) P0P9(S4) USB0(S4) USB1(S4) USB2(S4) USB3(S4) USB4(S4) USB5(S4) acpitimer0 at acpi0: 3579545 Hz, 24 bits acpimadt0 at acpi0 addr 0xfee0: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: Intel(R) Core(TM)2 CPU 6400 @ 2.13GHz, 2562.37 MHz cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,CX16,xTPR,NXE,LONG cpu0: 2MB 64b/line 8-way L2 cache cpu0: apic clock running at 266MHz cpu1 at mainbus0: apid 1 (application processor) cpu1: Intel(R) Core(TM)2 CPU 6400 @ 2.13GHz, 2135.04 MHz cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,SBF,SSE3,MWAIT,DS-CPL,VMX,EST,TM2,CX16,xTPR,NXE,LONG cpu1: 2MB 64b/line 8-way L2 cache ioapic0 at mainbus0 apid 2 pa 0xfec0, version 20, 24 pins acpihpet0 at acpi0: 14318179 Hz acpiprt0 at acpi0: bus 0 (PCI0) acpiprt1 at acpi0: bus 1 (P0P2) acpiprt2 at acpi0: bus 5 (P0P1) acpiprt3 at acpi0: bus 4 (P0P4) acpiprt4 at acpi0: bus -1 (P0P5) acpiprt5 at acpi0: bus -1 (P0P6) acpiprt6 at acpi0: bus 3 (P0P7) acpiprt7 at acpi0: bus 2 (P0P8) acpicpu0 at acpi0: PSS acpicpu1 at acpi0: PSS acpibtn0 at acpi0: PWRB pci0 at mainbus0 bus 0 pchb0 at pci0 dev 0 function 0 "Intel 82G965 Host" rev 0x02 ppb0 at pci0 dev 1 function 0 "Intel 82G965 PCIE" rev 0x02: apic 2 int 16 (irq 11) pci1 at ppb0 bus 1 vga1 at pci1 dev 0 function 0 "NVIDIA GeForce 7600 GT" rev 0xa1 wsdisplay0 at vga1 mux 1: console (80x25, vt100 emulation) wsdisplay0: screen 1-5 added (80x25, vt100 emulation) uhci0 at pci0 dev 26 function 0 "Intel 82801H USB" rev 0x02: apic 2 int 16 (irq 11) uhci1 at pci0 dev 26 function 1 "Intel 82801H USB" rev 0x02: apic 2 int 17 (irq 5) ehci0 at pci0 dev 26 function 7 "Intel 82801H USB" rev 0x02: apic 2 int 18 (irq 15) usb0 at ehci0: USB revision 2.0 uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1 azalia0 at pci0 dev 27 function 0 "Intel 82801H HD Audio" rev 0x02: apic 2 int 22 (irq 3) azalia0: codecs: Analog Devices AD1988A audio0 at azalia0 ppb1 at pci0 dev 28 function 0 "Intel 82801H PCIE" rev 0x02: apic 2 int 16 (irq 11) pci2 at ppb1 bus 4 ppb2 at pci0 dev 28 function 3 "Intel 82801H PCIE" rev 0x02: apic 2 int 19 (irq 10) pci3 at ppb2 bus 3 age0 at pci3 dev 0 function 0 "Attansic Technology L1" rev 0xb0: apic 2 int 19 (irq 10), address 00:18:f3:9d:7d:04 atphy0 at age0 phy 0: F1 10/100/1000 PHY, rev. 5 ppb3 at pci0 dev 28 function 4 "Intel 82801H PCIE" rev 0x02: apic 2 int 16 (irq 11) pci4 at ppb3 bus 2 jmb0 at pci4 dev 0 function 0 "JMicron JMB363 IDE/SATA" rev 0x02 ahci0 at jmb0: apic 2 int 16 (irq 11), AHCI 1.0 scsibus0 at ahci0: 32 targets pciide0 at jmb0: DMA, channel 0 wired to native-PCI, channel 1 wired to native-PCI pciide0: using apic 2 int 16 (irq 11) for native-PCI interrupt atapiscsi0 at pciide0 channel 0 drive 0 scsibus1 at atapiscsi0: 2 targets cd0 at scsibus1 targ 0 lun 0: ATAPI 5/cdrom removable cd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 2 pciide0: channel 1 disabled (no drives) uhci2 at pci0 dev 29 function 0 "Intel 82801H USB" rev 0x02: apic 2 int 23 (irq 7) uhci3 at pci0 dev 29 function 1 "Intel 82801H USB" rev 0x02: apic 2 int 19 (irq 10) uhci4 at pci0 dev 29 function 2 "Intel 82801H USB" rev 0x02: apic 2 int 18 (irq 15) ehci1 at pci0 dev 29 function 7 "Intel 82801H USB" rev 0x02: apic 2 int 23 (irq 7) usb1 at ehci1: USB revision 2.0 uhub1 at usb1 "Intel EHCI root hub" rev 2.00/1.00 addr 1 ppb4 at pci0 dev 30 function 0 "Intel 82801BA Hub-to-PCI" rev 0xf2 pci5 at ppb4 bus 5 puc0 at pci5 dev 1 function 0 "NetMos Nm9835" rev 0x01: ports: 1 com com2 at puc0 port 0 apic 2 int 22 (irq 3): ns16550a, 16 byte fifo re0 at pci5 dev 2 function 0 "D-Link Systems DGE-528T" rev 0x10: RTL8169/8110SB (0x1000), apic 2 int 23 (irq 7), address 00:21:91:12:15:03 rgephy0 at re0 phy 7: RTL8169S/8110S PHY, rev. 3 pcib0 at pci0 dev 31 function 0 "Intel 82801H LPC" rev 0x02 pciide1 at pci0 dev 31 function 2 "Intel 82801H
