passwd files are passwd files

[Ted Unangst]

As discovered by tb, different man pages call /etc/passwd different things.
The legacy of these files is not, however, relevant to their daily operation
and some 20 30? years later, "this file is like that one but different" is
more confusing than helpful.

Are there other references to 6th edition or whatever?

Index: usr.sbin/pwd_mkdb/pwd_mkdb.8
===
RCS file: /cvs/src/usr.sbin/pwd_mkdb/pwd_mkdb.8,v
retrieving revision 1.25
diff -u -p -r1.25 pwd_mkdb.8
--- usr.sbin/pwd_mkdb/pwd_mkdb.89 May 2016 11:13:10 -   1.25
+++ usr.sbin/pwd_mkdb/pwd_mkdb.814 Aug 2016 05:50:39 -
@@ -60,8 +60,6 @@ The
 .Ar file
 must be in the correct format (see
 .Xr passwd 5 ) .
-It is important to note that the format used in this system is
-different from the historic 6th Edition-style format.
 .Pp
 The options are as follows:
 .Bl -tag -width Ds
@@ -125,7 +123,7 @@ exits zero on success, non-zero on failu
 .It Pa /etc/master.passwd
 current password file
 .It Pa /etc/passwd
-a 6th Edition-style password file
+insecure password file
 .It Pa /etc/pwd.db
 insecure password database file
 .It Pa /etc/pwd.db.tmp
Index: usr.sbin/vipw/vipw.8
===
RCS file: /cvs/src/usr.sbin/vipw/vipw.8,v
retrieving revision 1.12
diff -u -p -r1.12 vipw.8
--- usr.sbin/vipw/vipw.813 Mar 2015 19:58:41 -  1.12
+++ usr.sbin/vipw/vipw.814 Aug 2016 05:51:43 -
@@ -91,7 +91,7 @@ will be invoked instead of the default e
 .It Pa /etc/master.passwd
 Current password file.
 .It Pa /etc/passwd
-A Version 7 format password file.
+Insecure password file.
 .It Pa /etc/ptmp
 Password lock file.
 .It Pa /etc/pwd.db

pax: remove many pointless casts

[Philip Guenther]

The quad_t change reminded me that pax is heavily over-cast.  Let's blow 
away some of the paren clouds:
 - remove casts of values to off_t or u_long when they're function
   arguments of that type: lseek(), map_dev(), ul_asc(), ul_oct(), 
   rd_skip(), wr_skip()
 - ditto for values being returned when that's the return type
 - ditto for casting to off_t for an binary operation whose other argument 
   is of type off_t
 - don't need to spell 0 with an L outside of varargs
 - use size_t instead of u_long for a buffer size in file_subs.c
 - when touching a return(), remove the outer parens

Compiled objects are unchanged for all but cpio.o and file_subs.o; those 
compare the same after stripping debugging info with "strip -g".

ok?

Philip Guenther

Index: ar_io.c
===
RCS file: /cvs/src/bin/pax/ar_io.c,v
retrieving revision 1.56
diff -u -p -r1.56 ar_io.c
--- ar_io.c 3 Jun 2016 23:22:20 -   1.56
+++ ar_io.c 14 Aug 2016 05:38:56 -
@@ -175,7 +175,7 @@ ar_open(const char *name)
artyp = ioctl(arfd, MTIOCGET, ) ? ISCHR : ISTAPE;
else if (S_ISBLK(arsb.st_mode))
artyp = ISBLK;
-   else if ((lseek(arfd, (off_t)0L, SEEK_CUR) == -1) && (errno == ESPIPE))
+   else if ((lseek(arfd, 0, SEEK_CUR) == -1) && (errno == ESPIPE))
artyp = ISPIPE;
else
artyp = ISREG;
@@ -462,7 +462,7 @@ ar_set_wr(void)
 * file, we must get rid of all the stuff after the current offset
 * (it was not written by pax).
 */
-   if (((cpos = lseek(arfd, (off_t)0L, SEEK_CUR)) < 0) ||
+   if (((cpos = lseek(arfd, 0, SEEK_CUR)) < 0) ||
(ftruncate(arfd, cpos) < 0)) {
syswarn(1, errno, "Unable to truncate archive file");
return(-1);
@@ -621,9 +621,9 @@ ar_write(char *buf, int bsz)
 * in size by forcing the runt record to next archive
 * volume
 */
-   if ((cpos = lseek(arfd, (off_t)0L, SEEK_CUR)) < 0)
+   if ((cpos = lseek(arfd, 0, SEEK_CUR)) < 0)
break;
-   cpos -= (off_t)res;
+   cpos -= res;
if (ftruncate(arfd, cpos) < 0)
break;
res = lstrval = 0;
@@ -757,9 +757,9 @@ ar_rdsync(void)
io_ok = 0;
if (((fsbz = arsb.st_blksize) <= 0) || (artyp != ISREG))
fsbz = BLKMULT;
-   if ((cpos = lseek(arfd, (off_t)0L, SEEK_CUR)) < 0)
+   if ((cpos = lseek(arfd, 0, SEEK_CUR)) < 0)
break;
-   mpos = fsbz - (cpos % (off_t)fsbz);
+   mpos = fsbz - (cpos % fsbz);
if (lseek(arfd, mpos, SEEK_CUR) < 0)
break;
lstrval = 1;
@@ -818,7 +818,7 @@ ar_fow(off_t sksz, off_t *skipped)
/*
 * figure out where we are in the archive
 */
-   if ((cpos = lseek(arfd, (off_t)0L, SEEK_CUR)) >= 0) {
+   if ((cpos = lseek(arfd, 0, SEEK_CUR)) >= 0) {
/*
 * we can be asked to move farther than there are bytes in this
 * volume, if so, just go to file end and let normal buf_fill()
@@ -886,7 +886,7 @@ ar_rev(off_t sksz)
 * may not even have the ability to lseek() in any direction).
 * First we figure out where we are in the archive.
 */
-   if ((cpos = lseek(arfd, (off_t)0L, SEEK_CUR)) < 0) {
+   if ((cpos = lseek(arfd, 0, SEEK_CUR)) < 0) {
syswarn(1, errno,
   "Unable to obtain current archive byte offset");
lstrval = -1;
@@ -900,7 +900,7 @@ ar_rev(off_t sksz)
 * previous volume and continue our movement backwards from
 * there.
 */
-   if ((cpos -= sksz) < (off_t)0L) {
+   if ((cpos -= sksz) < 0) {
if (arvol > 1) {
/*
 * this should never happen
@@ -909,7 +909,7 @@ ar_rev(off_t sksz)
lstrval = -1;
return(-1);
}
-   cpos = (off_t)0L;
+   cpos = 0;
}
if (lseek(arfd, cpos, SEEK_SET) < 0) {
syswarn(1, errno, "Unable to seek archive backwards");
Index: buf_subs.c
===
RCS file: /cvs/src/bin/pax/buf_subs.c,v
retrieving revision 1.27
diff -u -p -r1.27 buf_subs.c
--- buf_subs.c  19 Mar 2015 05:14:24 -  1.27
+++ buf_subs.c  14 Aug 2016 05:38:56 -
@@ -236,7 +236,7 @@ appnd_start(off_t skcnt)
 

Re: Make Cortex-A7 go fast

[Jonathan Gray]

On Sat, Aug 13, 2016 at 08:26:30PM +0200, Mark Kettenis wrote:
> On Cortex-A7 there is a magic SMP bit in the Auxiliary Control
> Register that "Enables coherent requests to the processor".  The
> Cortex-A7 Technical Reference Manual mentions that:
> 
>   When coherent requests are disabled:
> 
>   * loads to cacheable memory are not cached by the processor.
> 
> So effectively, not setting the bit means that we would be running the
> CPU with its caches disabled.  We do attempt to set this bit, but the
> code actually toggled the bit.  So if the firmware had set the bit,
> like it does on my Banana Pi, we would unset it.  The result was that
> the CPU was running at glacial speed.
> 
> Now the Cortex-A7 TRM also has the following note:
> 
>   You must ensure this bit is set to 1 before the caches and MMU are
>   enabled, or any cache and TLB maintenance operations are
>   performed. The only time this bit is set to 0 is during a processor
>   power-down sequence.
> 
> So we really should be setting the Auxiliary Control Register before
> we enable the MMU and caches by setting the System Control Register.
> The diff below fixes these issues and brings in some symbolic
> constants for the Auxiliary Control Register bits from NetBSD.
> 
> Tested on both Cortex-A9 and Cortex-A7.
> 
> ok?

yes ok, but the defines should really be ACTLR not AUXCTL to match
the arm docs.

Interesting that cortex a53/a57/a72 don't have a smp/coherency bit.

Comparing to the FreeBSD code they also set/mask

cortex a15:
set (1U << 31) "snoop delayed exclusive handling"

cortex a9:
mask (1 << 7) "exclusive L1/L2 cache control"

cortex a8:
set/mask (1 << 1) Enable L2 cache
mask (1 << 0) L1 data cache hardware alias support enabled

cortex a5:
mask (1 << 7) disable exclusive L1/L2 cache control

https://svnweb.freebsd.org/base/head/sys/arm/arm/cpuinfo.c?revision=HEAD=markup

> 
> 
> Index: arch/arm/arm/cpufunc.c
> ===
> RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
> retrieving revision 1.44
> diff -u -p -r1.44 cpufunc.c
> --- arch/arm/arm/cpufunc.c10 Aug 2016 21:22:43 -  1.44
> +++ arch/arm/arm/cpufunc.c13 Aug 2016 18:23:39 -
> @@ -568,6 +568,26 @@ armv7_setup()
>   uint32_t auxctrl, auxctrlmask;
>   uint32_t cpuctrl, cpuctrlmask;
>  
> + auxctrl = auxctrlmask = 0;
> +
> + switch (cputype & CPU_ID_CORTEX_MASK) {
> + case CPU_ID_CORTEX_A5:
> + case CPU_ID_CORTEX_A9:
> + /* Cache and TLB maintenance broadcast */
> +#ifdef notyet
> + auxctrlmask |= CORTEXA9_AUXCTL_FW;
> + auxctrl |= CORTEXA9_AUXCTL_FW;
> +#endif
> + /* FALLTHROUGH */
> + case CPU_ID_CORTEX_A7:
> + case CPU_ID_CORTEX_A15:
> + case CPU_ID_CORTEX_A17:
> + /* Set SMP to allow LDREX/STREX */
> + auxctrlmask |= CORTEXA9_AUXCTL_SMP;
> + auxctrl |= CORTEXA9_AUXCTL_SMP;
> + break;
> + }
> +
>   cpuctrlmask = CPU_CONTROL_MMU_ENABLE
>   | CPU_CONTROL_AFLT_ENABLE
>   | CPU_CONTROL_DC_ENABLE
> @@ -590,29 +610,16 @@ armv7_setup()
>   /* Clear out the cache */
>   cpu_idcache_wbinv_all();
>  
> + /*
> +  * Set the auxilliary control register first, as the SMP bit
> +  * needs to be set to 1 before the caches and the MMU are
> +  * enabled.
> +  */
> + cpu_auxcontrol(auxctrlmask, auxctrl);
> +
>   /* Set the control register */
>   curcpu()->ci_ctrl = cpuctrl;
>   cpu_control(cpuctrlmask, cpuctrl);
> -
> - auxctrl = auxctrlmask = 0;
> -
> - switch (cputype & CPU_ID_CORTEX_MASK) {
> - case CPU_ID_CORTEX_A5:
> - case CPU_ID_CORTEX_A9:
> - /* Cache and TLB maintenance broadcast */
> -#ifdef notyet
> - auxctrl |= (1 << 0);
> -#endif
> - /* FALLTHROUGH */
> - case CPU_ID_CORTEX_A7:
> - case CPU_ID_CORTEX_A15:
> - case CPU_ID_CORTEX_A17:
> - /* Set SMP to allow LDREX/STREX */
> - auxctrl |= (1 << 6);
> - break;
> - }
> -
> - cpu_auxcontrol(auxctrlmask, auxctrl);
>  
>   /* And again. */
>   cpu_idcache_wbinv_all();
> Index: arch/arm/include/armreg.h
> ===
> RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
> retrieving revision 1.33
> diff -u -p -r1.33 armreg.h
> --- arch/arm/include/armreg.h 6 Aug 2016 16:46:25 -   1.33
> +++ arch/arm/include/armreg.h 13 Aug 2016 18:23:39 -
> @@ -269,6 +269,16 @@
>  #define XSCALE_AUXCTL_MD_WT  0x0020 /* mini-D$ wt, read-allocate */
>  #define XSCALE_AUXCTL_MD_MASK0x0030
>  
> +/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
> +#define CORTEXA9_AUXCTL_FW   (1 << 0) /* Cache and TLB updates broadcast */
> +#define CORTEXA9_AUXCTL_L2PE (1 << 1) /* Prefetch hint enable */
> +#define CORTEXA9_AUXCTL_L1PE (1 << 2) /* Data prefetch hint enable */
> 

stop using u_quad_t in pax

[Philip Guenther]

u_quad_t is a remanent of the distant pre-long long past, so let's stop 
using it in pax.  For consistency, replace "uqd" with "ull" in the names 
of the involved functions.

There are a couple amusing spots in gen_subs.c:
if ((val = (val >> 4)) == (u_quad_t)0)
break;
...
if ((val = (val >> 3)) == (u_quad_t)0)
break;

The cast was pointless, but that's kinda confusing as is, so I'm pulling 
the assignment out and making the first of these:
val >>= 4;
if (val == 0)
break;

Tested by archiving, listing, and restoring a file with a date in 2100.

ok?

Philip Guenther


Index: cpio.c
===
RCS file: /data/src/openbsd/src/bin/pax/cpio.c,v
retrieving revision 1.27
diff -u -p -r1.27 cpio.c
--- cpio.c  19 Mar 2015 05:14:24 -  1.27
+++ cpio.c  14 Aug 2016 00:36:41 -
@@ -270,7 +270,7 @@ int
 cpio_rd(ARCHD *arcn, char *buf)
 {
int nsz;
-   u_quad_t val;
+   unsigned long long val;
HD_CPIO *hd;
 
/*
@@ -293,14 +293,14 @@ cpio_rd(ARCHD *arcn, char *buf)
arcn->sb.st_nlink = (nlink_t)asc_ul(hd->c_nlink, sizeof(hd->c_nlink),
OCT);
arcn->sb.st_rdev = (dev_t)asc_ul(hd->c_rdev, sizeof(hd->c_rdev), OCT);
-   val = asc_uqd(hd->c_mtime, sizeof(hd->c_mtime), OCT);
+   val = asc_ull(hd->c_mtime, sizeof(hd->c_mtime), OCT);
if ((time_t)val < 0 || (time_t)val != val)
arcn->sb.st_mtime = INT_MAX;/* XXX 2038 */
else
arcn->sb.st_mtime = val;
arcn->sb.st_mtim.tv_nsec = 0;
arcn->sb.st_ctim = arcn->sb.st_atim = arcn->sb.st_mtim;
-   arcn->sb.st_size = (off_t)asc_uqd(hd->c_filesize,sizeof(hd->c_filesize),
+   arcn->sb.st_size = (off_t)asc_ull(hd->c_filesize,sizeof(hd->c_filesize),
OCT);
 
/*
@@ -396,7 +396,7 @@ cpio_wr(ARCHD *arcn)
/*
 * set data size for file data
 */
-   if (uqd_asc((u_quad_t)arcn->sb.st_size, hd->c_filesize,
+   if (ull_asc(arcn->sb.st_size, hd->c_filesize,
sizeof(hd->c_filesize), OCT)) {
paxwarn(1,"File is too large for cpio format %s",
arcn->org_name);
@@ -439,7 +439,7 @@ cpio_wr(ARCHD *arcn)
 OCT) ||
ul_asc((u_long)arcn->sb.st_rdev, hd->c_rdev, sizeof(hd->c_rdev),
OCT) ||
-   uqd_asc(arcn->sb.st_mtime < 0 ? 0 : arcn->sb.st_mtime, hd->c_mtime,
+   ull_asc(arcn->sb.st_mtime < 0 ? 0 : arcn->sb.st_mtime, hd->c_mtime,
sizeof(hd->c_mtime), OCT) ||
ul_asc((u_long)nsz, hd->c_namesize, sizeof(hd->c_namesize), OCT))
goto out;
@@ -575,7 +575,7 @@ vcpio_rd(ARCHD *arcn, char *buf)
arcn->sb.st_mtime = (time_t)asc_ul(hd->c_mtime,sizeof(hd->c_mtime),HEX);
arcn->sb.st_mtim.tv_nsec = 0;
arcn->sb.st_ctim = arcn->sb.st_atim = arcn->sb.st_mtim;
-   arcn->sb.st_size = (off_t)asc_uqd(hd->c_filesize,
+   arcn->sb.st_size = (off_t)asc_ull(hd->c_filesize,
sizeof(hd->c_filesize), HEX);
arcn->sb.st_nlink = (nlink_t)asc_ul(hd->c_nlink, sizeof(hd->c_nlink),
HEX);
@@ -711,7 +711,7 @@ vcpio_wr(ARCHD *arcn)
 * much to pad.
 */
arcn->pad = VCPIO_PAD(arcn->sb.st_size);
-   if (uqd_asc((u_quad_t)arcn->sb.st_size, hd->c_filesize,
+   if (ull_asc(arcn->sb.st_size, hd->c_filesize,
sizeof(hd->c_filesize), HEX)) {
paxwarn(1,"File is too large for sv4cpio format %s",
arcn->org_name);
Index: extern.h
===
RCS file: /data/src/openbsd/src/bin/pax/extern.h,v
retrieving revision 1.54
diff -u -p -r1.54 extern.h
--- extern.h1 Jan 2016 15:56:03 -   1.54
+++ extern.h14 Aug 2016 00:36:00 -
@@ -174,8 +174,8 @@ void ls_tty(ARCHD *);
 void safe_print(const char *, FILE *);
 u_long asc_ul(char *, int, int);
 int ul_asc(u_long, char *, int, int);
-u_quad_t asc_uqd(char *, int, int);
-int uqd_asc(u_quad_t, char *, int, int);
+unsigned long long asc_ull(char *, int, int);
+int ull_asc(unsigned long long, char *, int, int);
 size_t fieldcpy(char *, size_t, const char *, size_t);
 
 /*
Index: gen_subs.c
===
RCS file: /data/src/openbsd/src/bin/pax/gen_subs.c,v
retrieving revision 1.28
diff -u -p -r1.28 gen_subs.c
--- gen_subs.c  17 Mar 2015 03:23:17 -  1.28
+++ gen_subs.c  14 Aug 2016 00:36:10 -
@@ -251,13 +251,15 @@ ul_asc(u_long val, char *str, int len, i
*pt-- = '0' + (char)digit;
 

realtek 8179 wireless pci

[Prabhu Gurumurthy]

Hello,

I installed OpenBSD 5.9 on relatively new system running AMD A4 processor
(dmesg included) and the system has realtek 8179 wireless pci which does
not get recognized by the stock kernel.

The stock GENERIC kernel throws the following message during bootup for the
PCI device

vendor "Realtek", unknown product 0x8179 (class network subclass
miscellaneous, rev 0x01) at pci8 dev 0 function 0 not configured

After starting to dig further I made changed pcidevs in
/usr/src/sys/dev/pci, and recompiled the GENERIC.MP kernel, but that did
not work. Still got the same message as above

pcidump from the stock kernel
 8:0:0: Realtek unknown
0x: Vendor ID: 10ec Product ID: 8179
0x0004: Command: 0007 Status: 0010
0x0008: Class: 02 Subclass: 80 Interface: 00 Revision: 01
0x000c: BIST: 00 Header Type: 00 Latency Timer: 00 Cache Line Size:
10
0x0010: BAR io addr: 0xc000/0x0100
0x0014: BAR empty ()
0x0018: BAR mem 64bit addr: 0xfe70/0x4000
0x0020: BAR empty ()
0x0024: BAR empty ()
0x0028: Cardbus CIS: 
0x002c: Subsystem Vendor ID: 10ec Product ID: 8179
0x0030: Expansion ROM Base Address: 
0x0038: 
0x003c: Interrupt Pin: 01 Line: 05 Min Gnt: 00 Max Lat: 00
0x0040: Capability 0x01: Power Management
State: D0
0x0050: Capability 0x05: Message Signaled Interrupts (MSI)
0x0070: Capability 0x10: PCI Express
Link Speed: 2.5 / 2.5 GT/s Link Width: x1 / x1
0x: 817910ec 0017 0281 0010
0x0010: c001  fe74 
0x0020:    817910ec
0x0030:  0040  0105


So I changed the following, (why I choose rtwn? because everything else is
either USB or Ethernet interface AFAICT under realtek, this adapter is
capable of running 802.11ac, previous system was Windows 10, so know from
that)

Index: if_rtwn.c
===
RCS file: /cvs/src/sys/dev/pci/if_rtwn.c,v
retrieving revision 1.12
diff -u -p -u -r1.12 if_rtwn.c
--- if_rtwn.c   5 Jan 2016 18:41:15 -   1.12
+++ if_rtwn.c   13 Aug 2016 23:42:25 -
@@ -78,7 +78,8 @@ int rtwn_debug = 0;
R92C_IMR_RXFOVW)

 static const struct pci_matchid rtwn_pci_devices[] = {
-   { PCI_VENDOR_REALTEK,   PCI_PRODUCT_REALTEK_RT8188 }
+   { PCI_VENDOR_REALTEK,   PCI_PRODUCT_REALTEK_RT8188 },
+   { PCI_VENDOR_REALTEK,   PCI_PRODUCT_REALTEK_RT8179 },
 };

 intrtwn_match(struct device *, void *, void *);
Index: pcidevs
===
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1788
diff -u -p -u -r1.1788 pcidevs
--- pcidevs 20 Feb 2016 14:34:27 -  1.1788
+++ pcidevs 13 Aug 2016 23:42:26 -
@@ -6355,6 +6355,7 @@ product REALTEK RTL8192SE 0x8172  8192SE
 product REALTEK RT8180 0x8180  8180
 product REALTEK RT8185 0x8185  8185
 product REALTEK RT8188 0x8176  8188CE
+product REALTEK RT8188 0x8179  8188CE
 product REALTEK RTL8192CE  0x8178  RTL8192CE
 product REALTEK RTL8192EE  0x818b  RTL8192EE
 product REALTEK RTL8190P   0x8190  RTL8190P
Index: pcidevs.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.1781
diff -u -p -u -r1.1781 pcidevs.h
--- pcidevs.h   20 Feb 2016 14:34:32 -  1.1781
+++ pcidevs.h   13 Aug 2016 23:42:27 -
@@ -6361,6 +6361,7 @@
 #definePCI_PRODUCT_REALTEK_RT8185  0x8185  /* 8185 */
 #definePCI_PRODUCT_REALTEK_RT8188  0x8176  /* 8188CE */
 #definePCI_PRODUCT_REALTEK_RTL8192CE   0x8178  /*
RTL8192CE */
+#define  PCI_PRODUCT_REALTEK_RT8179 0x8179
 #definePCI_PRODUCT_REALTEK_RTL8192EE   0x818b  /*
RTL8192EE */
 #definePCI_PRODUCT_REALTEK_RTL8190P0x8190  /* RTL8190P
*/
 #definePCI_PRODUCT_REALTEK_RTL8192E0x8192  /* RTL8192E
*/
Index: pcidevs_data.h
===
RCS file: /cvs/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.1776
diff -u -p -u -r1.1776 pcidevs_data.h
--- pcidevs_data.h  20 Feb 2016 14:34:32 -  1.1776
+++ pcidevs_data.h  13 Aug 2016 23:42:27 -
@@ -22156,6 +22156,10 @@ static const struct pci_known_product pc
"8192SE",
},
{
+PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8179,
+"8179",
+   },
+   {
PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180,
"8180",
},

which resulted in the kernel knowing more about the device.

rtwn0 at pci8 dev 0 function 0 "Realtek 8179" rev 0x01: msi
rtwn0: MAC/BB RTL8188CE, RF 6052 1T1R, address 

Re: bus_dmamap_sync() of size zero

[Ted Unangst]

Mark Kettenis wrote:
> OpenBSD/arm seems to be the only port that doesn't like it when you
> pass its bus_dmamap_sync() a size of zero.  While it is indeed a bit
> silly to do so, adding checks for this in the drivers might be
> overkill.  In fact if you read the bus_dma_sync(9) man page, you could
> could interpret from
> 
>  On platforms which implement reordered stores, bus_dmamap_sync() will
>  always cause the store buffer to be flushed.
> 
> that passing a size of zero is useful to flush the store buffers.
> 
> So my idea is that we simply remove the check.

In many other contexts, zero lengths are acceptable. (even so when other
arguments are not). makes a lot of sense to me.

Re: sixuart fifo fix

[Mark Kettenis]

> Date: Sat, 13 Aug 2016 23:06:45 +0200
> From: Marcus Glocker 
> 
> When I currently boot the allwinner,sun5i-r8 board with an UART cable
> connected for console but no terminal attached, the boot hangs as soon
> the driver switches from the console output routines to interrupts.
> 
> I figured out that this is caused because at one place we set the
> FIFO RX interupt trigger to RXT2 (trigger on 1/2 full) instead of RXT0
> (trigger on 1 char).  I guess it's a typo since everywhere else in the
> driver it gets set to RXT0.
> 
> When setting it to RXT0 (which is the reset value) the boot doesn't
> hang anymore also when an UART cable is connected without a terminal
> attached.
> 
> ok?

Not sure if it is a typo, but if it fixes your issues, go ahead.
> 
> Index: sxiuart.c
> ===
> RCS file: /cvs/src/sys/arch/armv7/sunxi/sxiuart.c,v
> retrieving revision 1.12
> diff -u -p -r1.12 sxiuart.c
> --- sxiuart.c 12 Aug 2016 16:09:37 -  1.12
> +++ sxiuart.c 13 Aug 2016 20:34:48 -
> @@ -660,7 +660,7 @@ sxiuartopen(dev_t dev, int flag, int mod
>   iot = sc->sc_iot;
>   ioh = sc->sc_ioh;
>  
> - bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT2);
> + bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT0);
>   delay(100);
>   while (ISSET(bus_space_read_1(iot, ioh, SXIUART_LSR),
>   LSR_RXRDY))
> 
> 

Re: libtls: Add server side support for SNI

[Reyk Floeter]

On Sun, Aug 14, 2016 at 04:04:34AM +1000, Joel Sing wrote:
> For those who are interested, the following diff adds server side support
> for SNI to libtls. There are three additional functions:
> 
> tls_config_add_keypair_file()
> tls_config_add_keypair_mem()
> tls_conninfo_servername()
> 
> The first two allow you to add additional certificates/private keys that will
> be used if the client sends a TLS servername extension that matches one
> of the SANs. The third function returns the TLS servername extension that
> the client specified.
> 

It's a big diff and I saw that you're splitting it up, but you can
find a few comments below.  Otherwise it looks OK to me, it is
surprisingly straight forward.

Reyk

> Index: tls.c
> ===
> RCS file: /cvs/src/lib/libtls/tls.c,v
> retrieving revision 1.45
> diff -u -p -r1.45 tls.c
> --- tls.c 13 Aug 2016 13:05:51 -  1.45
> +++ tls.c 13 Aug 2016 17:58:02 -
> @@ -177,6 +177,24 @@ tls_set_errorx(struct tls *ctx, const ch
>   return (rv);
>  }
>  
> +struct tls_sni_ctx *
> +tls_sni_ctx_new(void)
> +{
> + return (calloc(1, sizeof(struct tls_sni_ctx)));
> +}
> +
> +void
> +tls_sni_ctx_free(struct tls_sni_ctx *sni_ctx)
> +{
> + if (sni_ctx == NULL)
> + return;
> +
> + SSL_CTX_free(sni_ctx->ssl_ctx);
> + X509_free(sni_ctx->ssl_cert);
> +
> + free(sni_ctx);
> +}
> +
>  struct tls *
>  tls_new(void)
>  {
> @@ -207,7 +225,7 @@ tls_configure(struct tls *ctx, struct tl
>  }
>  
>  int
> -tls_configure_keypair(struct tls *ctx, SSL_CTX *ssl_ctx,
> +tls_configure_ssl_keypair(struct tls *ctx, SSL_CTX *ssl_ctx,
>  struct tls_keypair *keypair, int required)
>  {
>   EVP_PKEY *pkey = NULL;
> @@ -274,27 +292,27 @@ tls_configure_keypair(struct tls *ctx, S
>  }
>  
>  int
> -tls_configure_ssl(struct tls *ctx)
> +tls_configure_ssl(struct tls *ctx, SSL_CTX *ssl_ctx)
>  {
> - SSL_CTX_set_mode(ctx->ssl_ctx, SSL_MODE_ENABLE_PARTIAL_WRITE);
> - SSL_CTX_set_mode(ctx->ssl_ctx, SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER);
> + SSL_CTX_set_mode(ssl_ctx, SSL_MODE_ENABLE_PARTIAL_WRITE);
> + SSL_CTX_set_mode(ssl_ctx, SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER);
>  
> - SSL_CTX_set_options(ctx->ssl_ctx, SSL_OP_NO_SSLv2);
> - SSL_CTX_set_options(ctx->ssl_ctx, SSL_OP_NO_SSLv3);
> + SSL_CTX_set_options(ssl_ctx, SSL_OP_NO_SSLv2);
> + SSL_CTX_set_options(ssl_ctx, SSL_OP_NO_SSLv3);
>  
> - SSL_CTX_clear_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1);
> - SSL_CTX_clear_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1_1);
> - SSL_CTX_clear_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1_2);
> + SSL_CTX_clear_options(ssl_ctx, SSL_OP_NO_TLSv1);
> + SSL_CTX_clear_options(ssl_ctx, SSL_OP_NO_TLSv1_1);
> + SSL_CTX_clear_options(ssl_ctx, SSL_OP_NO_TLSv1_2);
>  
>   if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_0) == 0)
> - SSL_CTX_set_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1);
> + SSL_CTX_set_options(ssl_ctx, SSL_OP_NO_TLSv1);
>   if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_1) == 0)
> - SSL_CTX_set_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1_1);
> + SSL_CTX_set_options(ssl_ctx, SSL_OP_NO_TLSv1_1);
>   if ((ctx->config->protocols & TLS_PROTOCOL_TLSv1_2) == 0)
> - SSL_CTX_set_options(ctx->ssl_ctx, SSL_OP_NO_TLSv1_2);
> + SSL_CTX_set_options(ssl_ctx, SSL_OP_NO_TLSv1_2);
>  
>   if (ctx->config->alpn != NULL) {
> - if (SSL_CTX_set_alpn_protos(ctx->ssl_ctx, ctx->config->alpn,
> + if (SSL_CTX_set_alpn_protos(ssl_ctx, ctx->config->alpn,
>   ctx->config->alpn_len) != 0) {
>   tls_set_errorx(ctx, "failed to set alpn");
>   goto err;
> @@ -302,7 +320,7 @@ tls_configure_ssl(struct tls *ctx)
>   }
>  
>   if (ctx->config->ciphers != NULL) {
> - if (SSL_CTX_set_cipher_list(ctx->ssl_ctx,
> + if (SSL_CTX_set_cipher_list(ssl_ctx,
>   ctx->config->ciphers) != 1) {
>   tls_set_errorx(ctx, "failed to set ciphers");
>   goto err;
> @@ -310,7 +328,7 @@ tls_configure_ssl(struct tls *ctx)
>   }
>  
>   if (ctx->config->verify_time == 0) {
> - X509_VERIFY_PARAM_set_flags(ctx->ssl_ctx->param,
> + X509_VERIFY_PARAM_set_flags(ssl_ctx->param,
>   X509_V_FLAG_NO_CHECK_TIME);
>   }
>  
> @@ -321,13 +339,13 @@ tls_configure_ssl(struct tls *ctx)
>  }
>  
>  int
> -tls_configure_ssl_verify(struct tls *ctx, int verify)
> +tls_configure_ssl_verify(struct tls *ctx, SSL_CTX *ssl_ctx, int verify)
>  {
>   size_t ca_len = ctx->config->ca_len;
>   char *ca_mem = ctx->config->ca_mem;
>   char *ca_free = NULL;
>  
> - SSL_CTX_set_verify(ctx->ssl_ctx, verify, NULL);
> + SSL_CTX_set_verify(ssl_ctx, verify, NULL);
>  
>   /* If no CA has been specified, attempt to load the default. */
>   if 

Re: httpd: Add SNI support

[Reyk Floeter]

On Sun, Aug 14, 2016 at 04:06:26AM +1000, Joel Sing wrote:
> The following enables SNI support within httpd.
> 
> It requires libtls to have server side support for SNI (diff previously
> posted).
> 

The code is amazingly simple but it works fine and the diff is good:

OK reyk@

Two small notes:

- A few of the TLS log messages could probably be turned into DPRINTFs
later and we should find a consistent way to print TLS lowercase or
uppercase :)

- We could probably also use tls_conn_servername() in
server_handshake_tls() to switch srv_conf early, but this not really
needed and would only provide a small benefit for settings that cannot
be set in the "vhosts" (eg. timeouts, connection/request options).

Reyk

> Index: server.c
> ===
> RCS file: /cvs/src/usr.sbin/httpd/server.c,v
> retrieving revision 1.85
> diff -u -p -r1.85 server.c
> --- server.c  28 Apr 2016 17:18:06 -  1.85
> +++ server.c  13 Aug 2016 17:18:51 -
> @@ -159,6 +159,8 @@ server_tls_load_keypair(struct server *s
>  int
>  server_tls_init(struct server *srv)
>  {
> + struct server_config *srv_conf;
> +
>   if ((srv->srv_conf.flags & SRVFLAG_TLS) == 0)
>   return (0);
>  
> @@ -207,6 +209,19 @@ server_tls_init(struct server *srv)
>   return (-1);
>   }
>  
> + TAILQ_FOREACH(srv_conf, >srv_hosts, entry) {
> + if (srv_conf->tls_cert == NULL || srv_conf->tls_key == NULL)
> + continue;
> + log_debug("%s: adding keypair for server %s", __func__,
> + srv->srv_conf.name);
> + if (tls_config_add_keypair_mem(srv->srv_tls_config,
> + srv_conf->tls_cert, srv_conf->tls_cert_len,
> + srv_conf->tls_key, srv_conf->tls_key_len) != 0) {
> + log_warnx("%s: failed to add tls keypair", __func__);
> + return (-1);
> + }
> + }
> +
>   if (tls_configure(srv->srv_tls_ctx, srv->srv_tls_config) != 0) {
>   log_warnx("%s: failed to configure TLS - %s", __func__,
>   tls_error(srv->srv_tls_ctx));
> @@ -261,6 +276,9 @@ server_launch(void)
>   struct server   *srv;
>  
>   TAILQ_FOREACH(srv, env->sc_servers, srv_entry) {
> + log_debug("%s: configuring server %s", __func__,
> + srv->srv_conf.name);
> +
>   server_tls_init(srv);
>   server_http_init(srv);
>  
> 

-- 

sixuart fifo fix

[Marcus Glocker]

When I currently boot the allwinner,sun5i-r8 board with an UART cable
connected for console but no terminal attached, the boot hangs as soon
the driver switches from the console output routines to interrupts.

I figured out that this is caused because at one place we set the
FIFO RX interupt trigger to RXT2 (trigger on 1/2 full) instead of RXT0
(trigger on 1 char).  I guess it's a typo since everywhere else in the
driver it gets set to RXT0.

When setting it to RXT0 (which is the reset value) the boot doesn't
hang anymore also when an UART cable is connected without a terminal
attached.

ok?


Index: sxiuart.c
===
RCS file: /cvs/src/sys/arch/armv7/sunxi/sxiuart.c,v
retrieving revision 1.12
diff -u -p -r1.12 sxiuart.c
--- sxiuart.c   12 Aug 2016 16:09:37 -  1.12
+++ sxiuart.c   13 Aug 2016 20:34:48 -
@@ -660,7 +660,7 @@ sxiuartopen(dev_t dev, int flag, int mod
iot = sc->sc_iot;
ioh = sc->sc_ioh;
 
-   bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT2);
+   bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT0);
delay(100);
while (ISSET(bus_space_read_1(iot, ioh, SXIUART_LSR),
LSR_RXRDY))

bus_dmamap_sync() of size zero

[Mark Kettenis]

OpenBSD/arm seems to be the only port that doesn't like it when you
pass its bus_dmamap_sync() a size of zero.  While it is indeed a bit
silly to do so, adding checks for this in the drivers might be
overkill.  In fact if you read the bus_dma_sync(9) man page, you could
could interpret from

 On platforms which implement reordered stores, bus_dmamap_sync() will
 always cause the store buffer to be flushed.

that passing a size of zero is useful to flush the store buffers.

So my idea is that we simply remove the check.

ok?


Index: arch/arm/arm/bus_dma.c
===
RCS file: /cvs/src/sys/arch/arm/arm/bus_dma.c,v
retrieving revision 1.30
diff -u -p -r1.30 bus_dma.c
--- arch/arm/arm/bus_dma.c  16 May 2016 15:13:50 -  1.30
+++ arch/arm/arm/bus_dma.c  13 Aug 2016 19:45:52 -
@@ -589,7 +589,7 @@ _bus_dmamap_sync(bus_dma_tag_t t, bus_dm
if (offset >= map->dm_mapsize)
panic("_bus_dmamap_sync: bad offset %lu (map size is %lu)",
offset, map->dm_mapsize);
-   if (len == 0 || (offset + len) > map->dm_mapsize)
+   if ((offset + len) > map->dm_mapsize)
panic("_bus_dmamap_sync: bad length");
 #endif
 

Re: acpiec: handle burst mode failure

[Mark Kettenis]

> Date: Fri, 12 Aug 2016 08:58:19 -0500
> From: joshua stein 
> 
> On Fri, 08 Jul 2016 at 18:51:17 -0500, joshua stein wrote:
> > If the EC fails to go into burst mode for whatever reason, the Burst
> > Acknowledge byte will not be there to read, which means the status
> > won't have EC_STAT_OBF, which means acpiec_wait will spin forever,
> > hanging the machine.
> > 
> > This at least gets us moving again, ignoring the failure to enter
> > burst mode.
> 
> That patch was put into the latest snapshot (but not yet in CVS) and
> some people are seeing fallout from it like strange thermal and
> battery status readings.
> 
> This is a different patch which just doesn't bother with burst mode
> unless the transfer is big.  This should match how Linux and FreeBSD
> behave.  I have at least one confirmation that this fixes things on
> the ThinkPad X260.
> 
> Anyone else that is seeing strangeness on the latest snapshot, I ask
> that you try this patch against -current and see if your issues go
> away.

FWIW, tis diff makes sense to me.  There is no real point in enabling
burst mode if you're only going to do a single read or write.  And I
wouldn't be surprised if some ECs protested against this.

No apparent issues with this diff on an x220 and an x1 gen3.

ok kettenis@

> Index: sys/dev/acpi/acpiec.c
> ===
> RCS file: /cvs/src/sys/dev/acpi/acpiec.c,v
> retrieving revision 1.53
> diff -u -p -u -r1.53 acpiec.c
> --- sys/dev/acpi/acpiec.c 7 May 2016 18:03:36 -   1.53
> +++ sys/dev/acpi/acpiec.c 11 Aug 2016 20:06:54 -
> @@ -218,10 +218,12 @@ acpiec_read(struct acpiec_softc *sc, u_i
>*/
>   dnprintf(20, "%s: read %d, %d\n", DEVNAME(sc), (int)addr, len);
>   sc->sc_ecbusy = 1;
> - acpiec_burst_enable(sc);
> + if (len > 1)
> + acpiec_burst_enable(sc);
>   for (reg = 0; reg < len; reg++)
>   buffer[reg] = acpiec_read_1(sc, addr + reg);
> - acpiec_burst_disable(sc);
> + if (len > 1)
> + acpiec_burst_disable(sc);
>   sc->sc_ecbusy = 0;
>  }
>  
> @@ -237,10 +239,12 @@ acpiec_write(struct acpiec_softc *sc, u_
>*/
>   dnprintf(20, "%s: write %d, %d\n", DEVNAME(sc), (int)addr, len);
>   sc->sc_ecbusy = 1;
> - acpiec_burst_enable(sc);
> + if (len > 1)
> + acpiec_burst_enable(sc);
>   for (reg = 0; reg < len; reg++)
>   acpiec_write_1(sc, addr + reg, buffer[reg]);
> - acpiec_burst_disable(sc);
> + if (len > 1)
> + acpiec_burst_disable(sc);
>   sc->sc_ecbusy = 0;
>  }
>  
> 
> 

Make Cortex-A7 go fast

[Mark Kettenis]

On Cortex-A7 there is a magic SMP bit in the Auxiliary Control
Register that "Enables coherent requests to the processor".  The
Cortex-A7 Technical Reference Manual mentions that:

  When coherent requests are disabled:

  * loads to cacheable memory are not cached by the processor.

So effectively, not setting the bit means that we would be running the
CPU with its caches disabled.  We do attempt to set this bit, but the
code actually toggled the bit.  So if the firmware had set the bit,
like it does on my Banana Pi, we would unset it.  The result was that
the CPU was running at glacial speed.

Now the Cortex-A7 TRM also has the following note:

  You must ensure this bit is set to 1 before the caches and MMU are
  enabled, or any cache and TLB maintenance operations are
  performed. The only time this bit is set to 0 is during a processor
  power-down sequence.

So we really should be setting the Auxiliary Control Register before
we enable the MMU and caches by setting the System Control Register.
The diff below fixes these issues and brings in some symbolic
constants for the Auxiliary Control Register bits from NetBSD.

Tested on both Cortex-A9 and Cortex-A7.

ok?


Index: arch/arm/arm/cpufunc.c
===
RCS file: /cvs/src/sys/arch/arm/arm/cpufunc.c,v
retrieving revision 1.44
diff -u -p -r1.44 cpufunc.c
--- arch/arm/arm/cpufunc.c  10 Aug 2016 21:22:43 -  1.44
+++ arch/arm/arm/cpufunc.c  13 Aug 2016 18:23:39 -
@@ -568,6 +568,26 @@ armv7_setup()
uint32_t auxctrl, auxctrlmask;
uint32_t cpuctrl, cpuctrlmask;
 
+   auxctrl = auxctrlmask = 0;
+
+   switch (cputype & CPU_ID_CORTEX_MASK) {
+   case CPU_ID_CORTEX_A5:
+   case CPU_ID_CORTEX_A9:
+   /* Cache and TLB maintenance broadcast */
+#ifdef notyet
+   auxctrlmask |= CORTEXA9_AUXCTL_FW;
+   auxctrl |= CORTEXA9_AUXCTL_FW;
+#endif
+   /* FALLTHROUGH */
+   case CPU_ID_CORTEX_A7:
+   case CPU_ID_CORTEX_A15:
+   case CPU_ID_CORTEX_A17:
+   /* Set SMP to allow LDREX/STREX */
+   auxctrlmask |= CORTEXA9_AUXCTL_SMP;
+   auxctrl |= CORTEXA9_AUXCTL_SMP;
+   break;
+   }
+
cpuctrlmask = CPU_CONTROL_MMU_ENABLE
| CPU_CONTROL_AFLT_ENABLE
| CPU_CONTROL_DC_ENABLE
@@ -590,29 +610,16 @@ armv7_setup()
/* Clear out the cache */
cpu_idcache_wbinv_all();
 
+   /*
+* Set the auxilliary control register first, as the SMP bit
+* needs to be set to 1 before the caches and the MMU are
+* enabled.
+*/
+   cpu_auxcontrol(auxctrlmask, auxctrl);
+
/* Set the control register */
curcpu()->ci_ctrl = cpuctrl;
cpu_control(cpuctrlmask, cpuctrl);
-
-   auxctrl = auxctrlmask = 0;
-
-   switch (cputype & CPU_ID_CORTEX_MASK) {
-   case CPU_ID_CORTEX_A5:
-   case CPU_ID_CORTEX_A9:
-   /* Cache and TLB maintenance broadcast */
-#ifdef notyet
-   auxctrl |= (1 << 0);
-#endif
-   /* FALLTHROUGH */
-   case CPU_ID_CORTEX_A7:
-   case CPU_ID_CORTEX_A15:
-   case CPU_ID_CORTEX_A17:
-   /* Set SMP to allow LDREX/STREX */
-   auxctrl |= (1 << 6);
-   break;
-   }
-
-   cpu_auxcontrol(auxctrlmask, auxctrl);
 
/* And again. */
cpu_idcache_wbinv_all();
Index: arch/arm/include/armreg.h
===
RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
retrieving revision 1.33
diff -u -p -r1.33 armreg.h
--- arch/arm/include/armreg.h   6 Aug 2016 16:46:25 -   1.33
+++ arch/arm/include/armreg.h   13 Aug 2016 18:23:39 -
@@ -269,6 +269,16 @@
 #define XSCALE_AUXCTL_MD_WT0x0020 /* mini-D$ wt, read-allocate */
 #define XSCALE_AUXCTL_MD_MASK  0x0030
 
+/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
+#define CORTEXA9_AUXCTL_FW (1 << 0) /* Cache and TLB updates broadcast */
+#define CORTEXA9_AUXCTL_L2PE   (1 << 1) /* Prefetch hint enable */
+#define CORTEXA9_AUXCTL_L1PE   (1 << 2) /* Data prefetch hint enable */
+#define CORTEXA9_AUXCTL_WR_ZERO(1 << 3) /* Ena. write full line of 0s 
mode */
+#define CORTEXA9_AUXCTL_SMP(1 << 6) /* Coherency is active */
+#define CORTEXA9_AUXCTL_EXCL   (1 << 7) /* Exclusive cache bit */
+#define CORTEXA9_AUXCTL_ONEWAY (1 << 8) /* Allocate in on cache way only */
+#define CORTEXA9_AUXCTL_PARITY (1 << 9) /* Support parity checking */
+
 /* Cache type register definitions */
 #define CPU_CT_ISIZE(x)((x) & 0xfff)   /* I$ info */
 #define CPU_CT_DSIZE(x)(((x) >> 12) & 0xfff)   /* D$ info */

httpd: Add SNI support

[Joel Sing]

The following enables SNI support within httpd.

It requires libtls to have server side support for SNI (diff previously
posted).

Index: server.c
===
RCS file: /cvs/src/usr.sbin/httpd/server.c,v
retrieving revision 1.85
diff -u -p -r1.85 server.c
--- server.c28 Apr 2016 17:18:06 -  1.85
+++ server.c13 Aug 2016 17:18:51 -
@@ -159,6 +159,8 @@ server_tls_load_keypair(struct server *s
 int
 server_tls_init(struct server *srv)
 {
+   struct server_config *srv_conf;
+
if ((srv->srv_conf.flags & SRVFLAG_TLS) == 0)
return (0);
 
@@ -207,6 +209,19 @@ server_tls_init(struct server *srv)
return (-1);
}
 
+   TAILQ_FOREACH(srv_conf, >srv_hosts, entry) {
+   if (srv_conf->tls_cert == NULL || srv_conf->tls_key == NULL)
+   continue;
+   log_debug("%s: adding keypair for server %s", __func__,
+   srv->srv_conf.name);
+   if (tls_config_add_keypair_mem(srv->srv_tls_config,
+   srv_conf->tls_cert, srv_conf->tls_cert_len,
+   srv_conf->tls_key, srv_conf->tls_key_len) != 0) {
+   log_warnx("%s: failed to add tls keypair", __func__);
+   return (-1);
+   }
+   }
+
if (tls_configure(srv->srv_tls_ctx, srv->srv_tls_config) != 0) {
log_warnx("%s: failed to configure TLS - %s", __func__,
tls_error(srv->srv_tls_ctx));
@@ -261,6 +276,9 @@ server_launch(void)
struct server   *srv;
 
TAILQ_FOREACH(srv, env->sc_servers, srv_entry) {
+   log_debug("%s: configuring server %s", __func__,
+   srv->srv_conf.name);
+
server_tls_init(srv);
server_http_init(srv);
 

jot: streamline and refactor the code a bit more:

[Theo Buehler]

There are two sentinels for infinite output: infinity == true and
reps == 0.

Ensure that infinity is set to true whenever reps is set to zero, then
always use 'if (infinity)'.

We can then merge the loop for deterministic output into the first
if (!randomize) statement, which is a lot tidier.

Inserting an occasional blank line doesn't hurt either.

Index: jot.c
===
RCS file: /var/cvs/src/usr.bin/jot/jot.c,v
retrieving revision 1.34
diff -u -p -r1.34 jot.c
--- jot.c   12 Aug 2016 23:29:59 -  1.34
+++ jot.c   13 Aug 2016 04:35:11 -
@@ -165,6 +165,8 @@ main(int argc, char *argv[])
if (!sscanf(argv[0], "%ld", ))
errx(1, "Bad reps value:  %s", argv[0]);
mask |= REPS;
+   if (reps == 0)
+   infinity = true;
if (prec == -1)
prec = 0;
}
@@ -176,8 +178,9 @@ main(int argc, char *argv[])
errx(1, "Too many arguments.  What do you mean by %s?",
argv[4]);
}
+
getformat();
-   /* If random output is requested, use defaults for omitted values. */
+
if (!randomize) {
/*
 * Consolidate the values of reps, begin, ender, step:
@@ -190,11 +193,10 @@ main(int argc, char *argv[])
 *begin and ender were specified.
 * 3. Assign defaults to omitted values for reps, begin, ender,
 *from left to right.
-* 4. reps == 0 means infinite output
 */
switch (mask) { /* Four cases involve both begin and ender. */
case REPS | BEGIN | ENDER | STEP:
-   if (reps == 0)
+   if (infinity)
errx(1,
"Can't specify end of infinite sequence");
if (step != 0.0) {
@@ -206,7 +208,7 @@ main(int argc, char *argv[])
}
break;
case REPS | BEGIN | ENDER:
-   if (reps == 0)
+   if (infinity)
errx(1,
"Can't specify end of infinite sequence");
if (reps == 1)
@@ -220,6 +222,7 @@ main(int argc, char *argv[])
case BEGIN | ENDER | STEP:
if (step == 0.0) {
reps = 0;
+   infinity = true;
break;
}
reps = (ender - begin + step) / step;
@@ -230,7 +233,7 @@ main(int argc, char *argv[])
case ENDER | STEP:
case REPS | ENDER:
case REPS | ENDER | STEP:
-   if (reps == 0)
+   if (infinity)
errx(1,
"Must specify start of infinite sequence");
begin = ender - reps * step + step;
@@ -244,10 +247,11 @@ main(int argc, char *argv[])
 */
break;
}
-   }
-   if (reps == 0)
-   infinity = true;
-   if (randomize) {
+
+   for (i = 1, x = begin; i <= reps || infinity; i++, x += step)
+   if (putdata(x, reps == i && !infinity))
+   errx(1, "range error in conversion: %f", x);
+   } else { /* Random output: use defaults for omitted values. */
booluse_unif;
uint32_tpow10 = 1;
uint32_tuintx = 0; /* Initialized to make gcc happy. */
@@ -293,11 +297,8 @@ main(int argc, char *argv[])
if (putdata(v, reps == i && !infinity))
errx(1, "range error in conversion: %f", v);
}
-   } else {
-   for (i = 1, x = begin; i <= reps || infinity; i++, x += step)
-   if (putdata(x, reps == i && !infinity))
-   errx(1, "range error in conversion: %f", x);
}
+
if (finalnl)
putchar('\n');
return (0);

Re: kill FUSE_ROOT_ID

[Mark Kettenis]

> Date: Sat, 13 Aug 2016 13:02:19 +0200
> From: Martin Natano 
> 
> Kill FUSE_ROOT_ID and use FUSE_ROOTINO instead for the only place where
> it was used. Also, remove one (ino_t) cast from FUSE_ROOTINO, as it is
> already included in the #define. Ok?
> 
> natano

ok kettenis@

> Index: miscfs/fuse/fuse_vfsops.c
> ===
> RCS file: /cvs/src/sys/miscfs/fuse/fuse_vfsops.c,v
> retrieving revision 1.24
> diff -u -p -r1.24 fuse_vfsops.c
> --- miscfs/fuse/fuse_vfsops.c 12 Aug 2016 20:18:44 -  1.24
> +++ miscfs/fuse/fuse_vfsops.c 13 Aug 2016 10:53:23 -
> @@ -172,7 +172,7 @@ fusefs_root(struct mount *mp, struct vno
>   struct vnode *nvp;
>   int error;
>  
> - if ((error = VFS_VGET(mp, (ino_t)FUSE_ROOTINO, )) != 0)
> + if ((error = VFS_VGET(mp, FUSE_ROOTINO, )) != 0)
>   return (error);
>  
>   nvp->v_type = VDIR;
> @@ -200,7 +200,7 @@ fusefs_statfs(struct mount *mp, struct s
>   copy_statfs_info(sbp, mp);
>  
>   if (fmp->sess_init) {
> - fbuf = fb_setup(0, FUSE_ROOT_ID, FBT_STATFS, p);
> + fbuf = fb_setup(0, FUSE_ROOTINO, FBT_STATFS, p);
>  
>   error = fb_queue(fmp->dev, fbuf);
>  
> Index: sys/fusebuf.h
> ===
> RCS file: /cvs/src/sys/sys/fusebuf.h,v
> retrieving revision 1.9
> diff -u -p -r1.9 fusebuf.h
> --- sys/fusebuf.h 16 Jan 2014 09:31:44 -  1.9
> +++ sys/fusebuf.h 13 Aug 2016 10:53:23 -
> @@ -133,9 +133,6 @@ struct fusebuf {
>  
>  #ifdef _KERNEL
>  
> -/* The node ID of the root inode */
> -#define FUSE_ROOT_ID 1
> -
>  /* fusebuf prototypes */
>  struct   fusebuf *fb_setup(size_t, ino_t, int, struct proc *);
>  int  fb_queue(dev_t, struct fusebuf *);
> 
> 

kill FUSE_ROOT_ID

[Martin Natano]

Kill FUSE_ROOT_ID and use FUSE_ROOTINO instead for the only place where
it was used. Also, remove one (ino_t) cast from FUSE_ROOTINO, as it is
already included in the #define. Ok?

natano


Index: miscfs/fuse/fuse_vfsops.c
===
RCS file: /cvs/src/sys/miscfs/fuse/fuse_vfsops.c,v
retrieving revision 1.24
diff -u -p -r1.24 fuse_vfsops.c
--- miscfs/fuse/fuse_vfsops.c   12 Aug 2016 20:18:44 -  1.24
+++ miscfs/fuse/fuse_vfsops.c   13 Aug 2016 10:53:23 -
@@ -172,7 +172,7 @@ fusefs_root(struct mount *mp, struct vno
struct vnode *nvp;
int error;
 
-   if ((error = VFS_VGET(mp, (ino_t)FUSE_ROOTINO, )) != 0)
+   if ((error = VFS_VGET(mp, FUSE_ROOTINO, )) != 0)
return (error);
 
nvp->v_type = VDIR;
@@ -200,7 +200,7 @@ fusefs_statfs(struct mount *mp, struct s
copy_statfs_info(sbp, mp);
 
if (fmp->sess_init) {
-   fbuf = fb_setup(0, FUSE_ROOT_ID, FBT_STATFS, p);
+   fbuf = fb_setup(0, FUSE_ROOTINO, FBT_STATFS, p);
 
error = fb_queue(fmp->dev, fbuf);
 
Index: sys/fusebuf.h
===
RCS file: /cvs/src/sys/sys/fusebuf.h,v
retrieving revision 1.9
diff -u -p -r1.9 fusebuf.h
--- sys/fusebuf.h   16 Jan 2014 09:31:44 -  1.9
+++ sys/fusebuf.h   13 Aug 2016 10:53:23 -
@@ -133,9 +133,6 @@ struct fusebuf {
 
 #ifdef _KERNEL
 
-/* The node ID of the root inode */
-#define FUSE_ROOT_ID   1
-
 /* fusebuf prototypes */
 struct fusebuf *fb_setup(size_t, ino_t, int, struct proc *);
 intfb_queue(dev_t, struct fusebuf *);

bigger mbuf clusters for sosend()

[Claudio Jeker]

This diff refactors the uio to mbuf code to make use of bigger buffers (up
to 64k) and also switches the MCLGET to use M_WAIT like the MGET calls in
the same function. I see no point in not waiting for a cluster and instead
chain lots of mbufs together as a consequence.

This makes in my opinion the code easier to read and allows for further
optimizations (like using non-DMA reachable mbufs for AF_UNIX sockets).

This increased the preformance of loopback connections significantly when
I tested this at n2k16.
-- 
:wq Claudio


Index: kern//uipc_socket.c
===
RCS file: /cvs/src/sys/kern/uipc_socket.c,v
retrieving revision 1.152
diff -u -p -r1.152 uipc_socket.c
--- kern//uipc_socket.c 13 Jun 2016 21:24:43 -  1.152
+++ kern//uipc_socket.c 12 Aug 2016 14:07:36 -
@@ -373,6 +373,8 @@ bad:
return (error);
 }
 
+int m_getuio(struct mbuf **, int, long, struct uio *);
+
 #defineSBLOCKWAIT(f)   (((f) & MSG_DONTWAIT) ? M_NOWAIT : M_WAITOK)
 /*
  * Send on a socket.
@@ -395,10 +397,7 @@ int
 sosend(struct socket *so, struct mbuf *addr, struct uio *uio, struct mbuf *top,
 struct mbuf *control, int flags)
 {
-   struct mbuf **mp;
-   struct mbuf *m;
long space, clen = 0;
-   u_long len, mlen;
size_t resid;
int error, s;
int atomic = sosendallatonce(so) || top;
@@ -475,7 +474,6 @@ restart:
goto restart;
}
splx(s);
-   mp = 
space -= clen;
do {
if (uio == NULL) {
@@ -485,52 +483,14 @@ restart:
resid = 0;
if (flags & MSG_EOR)
top->m_flags |= M_EOR;
-   } else do {
-   if (top == 0) {
-   MGETHDR(m, M_WAIT, MT_DATA);
-   mlen = MHLEN;
-   m->m_pkthdr.len = 0;
-   m->m_pkthdr.ph_ifidx = 0;
-   } else {
-   MGET(m, M_WAIT, MT_DATA);
-   mlen = MLEN;
-   }
-   if (resid >= MINCLSIZE && space >= MCLBYTES) {
-   MCLGET(m, M_NOWAIT);
-   if ((m->m_flags & M_EXT) == 0)
-   goto nopages;
-   if (atomic && top == 0) {
-   len = ulmin(MCLBYTES - max_hdr,
-   resid);
-   m->m_data += max_hdr;
-   } else
-   len = ulmin(MCLBYTES, resid);
-   space -= len;
-   } else {
-nopages:
-   len = ulmin(ulmin(mlen, resid), space);
-   space -= len;
-   /*
-* For datagram protocols, leave room
-* for protocol headers in first mbuf.
-*/
-   if (atomic && top == 0 && len < mlen)
-   MH_ALIGN(m, len);
-   }
-   error = uiomove(mtod(m, caddr_t), len, uio);
+   } else {
+   error = m_getuio(, atomic,
+   space, uio);
+   space -= top->m_pkthdr.len;
resid = uio->uio_resid;
-   m->m_len = len;
-   *mp = m;
-   top->m_pkthdr.len += len;
-   if (error)
-   goto release;
-   mp = >m_next;
-   if (resid == 0) {
-   if (flags & MSG_EOR)
-   top->m_flags |= M_EOR;
-   break;
-   }
-   } while (space > 0 && atomic);
+   if (flags & MSG_EOR)
+   top->m_flags |= M_EOR;
+   }
s = splsoftnet();   /* XXX */
if (resid == 0)
so->so_state &= ~SS_ISSENDING;
@@ -539,9 +499,8 @@ nopages: