ok? Index: arch/alpha/alpha/db_disasm.c =================================================================== RCS file: /cvs/src/sys/arch/alpha/alpha/db_disasm.c,v retrieving revision 1.23 diff -u -p -r1.23 db_disasm.c --- arch/alpha/alpha/db_disasm.c 27 Apr 2016 11:03:24 -0000 1.23 +++ arch/alpha/alpha/db_disasm.c 6 Nov 2019 07:46:53 -0000 @@ -823,12 +823,10 @@ register_name (ireg) * (optional) alternate format. Return address of start of * next instruction. */ -int alpha_print_instruction(db_addr_t, alpha_instruction, boolean_t); +int alpha_print_instruction(db_addr_t, alpha_instruction, int); db_addr_t -db_disasm(loc, altfmt) - db_addr_t loc; - boolean_t altfmt; +db_disasm(db_addr_t loc, int altfmt) { alpha_instruction inst; @@ -839,20 +837,17 @@ db_disasm(loc, altfmt) } int -alpha_print_instruction(iadr, i, showregs) - db_addr_t iadr; - alpha_instruction i; - boolean_t showregs; +alpha_print_instruction(db_addr_t iadr, alpha_instruction i, int showregs) { const char *opcode; int ireg; long signed_immediate; - boolean_t fstore; + int fstore; pal_instruction p; char tmpfmt[28]; regcount = 0; - fstore = FALSE; + fstore = 0; opcode = op_name[i.mem_format.opcode]; /* @@ -1021,7 +1016,7 @@ foperate: case op_stg: case op_sts: case op_stt: - fstore = TRUE; + fstore = 1; /* FALLTHROUGH */ case op_ldl: case op_ldq: Index: arch/alpha/alpha/db_interface.c =================================================================== RCS file: /cvs/src/sys/arch/alpha/alpha/db_interface.c,v retrieving revision 1.24 diff -u -p -r1.24 db_interface.c --- arch/alpha/alpha/db_interface.c 20 Mar 2018 15:45:32 -0000 1.24 +++ arch/alpha/alpha/db_interface.c 6 Nov 2019 07:46:34 -0000 @@ -167,11 +167,11 @@ ddb_trap(a0, a1, a2, entry, regs) s = splhigh(); db_active++; - cnpollc(TRUE); /* Set polling mode, unblank video */ + cnpollc(1); /* Set polling mode, unblank video */ db_trap(entry, a0); /* Where the work happens */ - cnpollc(FALSE); /* Resume interrupt mode */ + cnpollc(0); /* Resume interrupt mode */ db_active--; splx(s); @@ -286,9 +286,8 @@ db_register_value(regs, regno) * Support functions for software single-step. */ -boolean_t -db_inst_call(ins) - int ins; +int +db_inst_call(int ins) { alpha_instruction insn; @@ -298,9 +297,8 @@ db_inst_call(ins) (insn.jump_format.action & 1))); } -boolean_t -db_inst_return(ins) - int ins; +int +db_inst_return(int ins) { alpha_instruction insn; @@ -309,9 +307,8 @@ db_inst_return(ins) (insn.jump_format.action == op_ret)); } -boolean_t -db_inst_trap_return(ins) - int ins; +int +db_inst_trap_return(int ins) { alpha_instruction insn; @@ -320,9 +317,8 @@ db_inst_trap_return(ins) (insn.pal_format.function == PAL_OSF1_rti)); } -boolean_t -db_inst_branch(ins) - int ins; +int +db_inst_branch(int ins) { alpha_instruction insn; @@ -344,15 +340,14 @@ db_inst_branch(ins) case op_bne: case op_bge: case op_bgt: - return (TRUE); + return 1; } - return (FALSE); + return 0; } -boolean_t -db_inst_unconditional_flow_transfer(ins) - int ins; +int +db_inst_unconditional_flow_transfer(int ins) { alpha_instruction insn; @@ -360,62 +355,48 @@ db_inst_unconditional_flow_transfer(ins) switch (insn.branch_format.opcode) { case op_j: case op_br: - return (TRUE); + return 1; case op_pal: switch (insn.pal_format.function) { case PAL_OSF1_retsys: case PAL_OSF1_rti: case PAL_OSF1_callsys: - return (TRUE); + return 1; } } - return (FALSE); + return 0; } -#if 0 -boolean_t -db_inst_spill(ins, regn) - int ins, regn; +int +db_inst_load(int ins) { alpha_instruction insn; insn.bits = ins; - return ((insn.mem_format.opcode == op_stq) && - (insn.mem_format.rd == regn)); -} -#endif -boolean_t -db_inst_load(ins) - int ins; -{ - alpha_instruction insn; - - insn.bits = ins; - /* Loads. */ if (insn.mem_format.opcode == op_ldbu || insn.mem_format.opcode == op_ldq_u || insn.mem_format.opcode == op_ldwu) - return (TRUE); + return 1; if ((insn.mem_format.opcode >= op_ldf) && (insn.mem_format.opcode <= op_ldt)) - return (TRUE); + return 1; if ((insn.mem_format.opcode >= op_ldl) && (insn.mem_format.opcode <= op_ldq_l)) - return (TRUE); + return 1; /* Prefetches. */ if (insn.mem_format.opcode == op_special) { /* Note: MB is treated as a store. */ if ((insn.mem_format.displacement == (short)op_fetch) || (insn.mem_format.displacement == (short)op_fetch_m)) - return (TRUE); + return 1; } - return (FALSE); + return 0; } db_addr_t Index: arch/alpha/include/db_machdep.h =================================================================== RCS file: /cvs/src/sys/arch/alpha/include/db_machdep.h,v retrieving revision 1.25 diff -u -p -r1.25 db_machdep.h --- arch/alpha/include/db_machdep.h 27 Apr 2016 11:10:48 -0000 1.25 +++ arch/alpha/include/db_machdep.h 6 Nov 2019 07:45:41 -0000 @@ -27,9 +27,6 @@ #ifndef _MACHINE_DB_MACHDEP_H_ #define _MACHINE_DB_MACHDEP_H_ -/* XXX - Need to include vm.h for boolean_t */ -#include <uvm/uvm_extern.h> - struct opcode { enum opc_fmt { OPC_PAL, OPC_RES, OPC_MEM, OPC_OP, OPC_BR } opc_fmt; char *opc_name; @@ -72,12 +69,12 @@ extern db_regs_t ddb_regs; int alpha_debug(unsigned long, unsigned long, unsigned long, unsigned long, struct trapframe *); db_addr_t db_branch_taken(int, db_addr_t, db_regs_t *); -boolean_t db_inst_branch(int); -boolean_t db_inst_call(int); -boolean_t db_inst_load(int); -boolean_t db_inst_return(int); -boolean_t db_inst_trap_return(int); -boolean_t db_inst_unconditional_flow_transfer(int); +int db_inst_branch(int); +int db_inst_call(int); +int db_inst_load(int); +int db_inst_return(int); +int db_inst_trap_return(int); +int db_inst_unconditional_flow_transfer(int); u_long db_register_value(db_regs_t *, int); int db_valid_breakpoint(db_addr_t); int ddb_trap(unsigned long, unsigned long, unsigned long,