Re: arm/sysreg.h use in C

[aa e30]

13.7.2017 17.50 "Mark Kettenis"  kirjoitti:

> Date: Thu, 13 Jul 2017 15:49:03 +0300
> From: Artturi Alm 
>
> On Sat, Jul 01, 2017 at 10:53:14AM +0300, Artturi Alm wrote:
> > Hi,
> >
> > just in case i didn't make it clear what it is for, here's diff "fixing"
> > current uses below, compile-tested.
> >
> > -Artturi
> >
>
> Hi,
>
> ping?
> Noone up for bikeshedding, or seen useless/worse than handcrafting?
> I think this would alleviate from some of the complementary commenting,
> regarding the CP15 reg usage, that is currently somewhat of necessity.

I'm not sure myself if doing something like this is actually an
improvement.


Ok, i'll try to get some fbsd dev to
comment why they never went for
this, just for my own curiousity,
so not pushing the diff any further.

-Artturi


> > diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
> > index c91108e7066..fcb56627af7 100644
> > --- a/sys/arch/arm/arm/cpufunc.c
> > +++ b/sys/arch/arm/arm/cpufunc.c
> > @@ -55,6 +55,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  #if defined(PERFCTRS)
> >  struct arm_pmc_funcs *arm_pmc;
> > @@ -176,8 +177,7 @@ arm_get_cachetype_cp15v7(void)
> > uint32_t sel, level;
> >
> > /* CTR - Cache Type Register */
> > -   __asm volatile("mrc p15, 0, %0, c0, c0, 1"
> > -   : "=r" (ctype));
> > +   __asm volatile("mrc " SR_STR(CP15_CTR(%0)) "\n" : "=r"(ctype));
> >
> > arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
> > arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
> > @@ -185,8 +185,8 @@ arm_get_cachetype_cp15v7(void)
> > min(arm_icache_min_line_size, arm_dcache_min_line_size);
> >
> > /* CLIDR - Cache Level ID Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 1"
> > -   : "=r" (cache_level_id) :);
> > +   __asm volatile("mrc " SR_STR(CP15_CLIDR(%0))
> > +   : "=r"(cache_level_id));
> > cpu_drain_writebuf();
> >
> > /* L1 Cache available. */
> > @@ -201,17 +201,18 @@ arm_get_cachetype_cp15v7(void)
> > cache_level_id & (0x2 << level)) {
> > sel = level << 1 | 0 << 0; /* L1 | unified/data
cache */
> > /* CSSELR - Cache Size Selection Register */
> > -   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> > -   :: "r" (sel));
> > +   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0))
"\n"
> > +   :: "r"(sel));
> > cpu_drain_writebuf();
> > /* CCSIDR - Cache Size Identification Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> > -   : "=r" (cachereg) :);
> > +   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0))
"\n"
> > +   : "=r"(cachereg));
> > cpu_drain_writebuf();
> > sets = ((cachereg >> 13) & 0x7fff) + 1;
> > arm_pdcache_line_size = 1 << ((cachereg & 0x7) + 4);
> > arm_pdcache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> > -   arm_pdcache_size = arm_pdcache_line_size *
arm_pdcache_ways * sets;
> > +   arm_pdcache_size =
> > +   arm_pdcache_line_size * arm_pdcache_ways * sets;
> > switch (cachereg & 0xc000) {
> > case 0x:
> > arm_pcache_type = 0;
> > @@ -230,24 +231,26 @@ arm_get_cachetype_cp15v7(void)
> > if (cache_level_id & (0x1 << level)) {
> > sel = level << 1 | 1 << 0; /* L1 | instruction
cache */
> > /* CSSELR - Cache Size Selection Register */
> > -   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> > -   :: "r" (sel));
> > +   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0))
"\n"
> > +   :: "r"(sel));
> > cpu_drain_writebuf();
> > /* CCSIDR - Cache Size Identification Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> > -   : "=r" (cachereg) :);
> > +   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0))
"\n"
> > +   : "=r"(cachereg));
> > cpu_drain_writebuf();
> > sets = ((cachereg >> 13) & 0x7fff) + 1;
> > arm_picache_line_size = 1 << ((cachereg & 0x7) + 4);
> > arm_picache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> > -   arm_picache_size = arm_picache_line_size *
arm_picache_ways * sets;
> > +   arm_picache_size =
> > +   arm_picache_line_size * arm_picache_ways * sets;
> > }
> > }
> >
> > arm_dcache_align = arm_pdcache_line_size;
> > arm_dcache_align_mask = arm_dcache_align - 1;
> >
> > - 

Re: arm/sysreg.h use in C

[Mark Kettenis]

> Date: Thu, 13 Jul 2017 15:49:03 +0300
> From: Artturi Alm 
> 
> On Sat, Jul 01, 2017 at 10:53:14AM +0300, Artturi Alm wrote:
> > Hi,
> > 
> > just in case i didn't make it clear what it is for, here's diff "fixing"
> > current uses below, compile-tested.
> > 
> > -Artturi
> > 
> 
> Hi,
> 
> ping?
> Noone up for bikeshedding, or seen useless/worse than handcrafting?
> I think this would alleviate from some of the complementary commenting,
> regarding the CP15 reg usage, that is currently somewhat of necessity.

I'm not sure myself if doing something like this is actually an
improvement.

> > diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
> > index c91108e7066..fcb56627af7 100644
> > --- a/sys/arch/arm/arm/cpufunc.c
> > +++ b/sys/arch/arm/arm/cpufunc.c
> > @@ -55,6 +55,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  
> >  #if defined(PERFCTRS)
> >  struct arm_pmc_funcs *arm_pmc;
> > @@ -176,8 +177,7 @@ arm_get_cachetype_cp15v7(void)
> > uint32_t sel, level;
> >  
> > /* CTR - Cache Type Register */
> > -   __asm volatile("mrc p15, 0, %0, c0, c0, 1"
> > -   : "=r" (ctype));
> > +   __asm volatile("mrc " SR_STR(CP15_CTR(%0)) "\n" : "=r"(ctype));
> >  
> > arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
> > arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
> > @@ -185,8 +185,8 @@ arm_get_cachetype_cp15v7(void)
> > min(arm_icache_min_line_size, arm_dcache_min_line_size);
> >  
> > /* CLIDR - Cache Level ID Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 1"
> > -   : "=r" (cache_level_id) :);
> > +   __asm volatile("mrc " SR_STR(CP15_CLIDR(%0))
> > +   : "=r"(cache_level_id));
> > cpu_drain_writebuf();
> >  
> > /* L1 Cache available. */
> > @@ -201,17 +201,18 @@ arm_get_cachetype_cp15v7(void)
> > cache_level_id & (0x2 << level)) {
> > sel = level << 1 | 0 << 0; /* L1 | unified/data cache */
> > /* CSSELR - Cache Size Selection Register */
> > -   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> > -   :: "r" (sel));
> > +   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
> > +   :: "r"(sel));
> > cpu_drain_writebuf();
> > /* CCSIDR - Cache Size Identification Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> > -   : "=r" (cachereg) :);
> > +   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
> > +   : "=r"(cachereg));
> > cpu_drain_writebuf();
> > sets = ((cachereg >> 13) & 0x7fff) + 1;
> > arm_pdcache_line_size = 1 << ((cachereg & 0x7) + 4);
> > arm_pdcache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> > -   arm_pdcache_size = arm_pdcache_line_size * 
> > arm_pdcache_ways * sets;
> > +   arm_pdcache_size =
> > +   arm_pdcache_line_size * arm_pdcache_ways * sets;
> > switch (cachereg & 0xc000) {
> > case 0x:
> > arm_pcache_type = 0;
> > @@ -230,24 +231,26 @@ arm_get_cachetype_cp15v7(void)
> > if (cache_level_id & (0x1 << level)) {
> > sel = level << 1 | 1 << 0; /* L1 | instruction cache */
> > /* CSSELR - Cache Size Selection Register */
> > -   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> > -   :: "r" (sel));
> > +   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
> > +   :: "r"(sel));
> > cpu_drain_writebuf();
> > /* CCSIDR - Cache Size Identification Register */
> > -   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> > -   : "=r" (cachereg) :);
> > +   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
> > +   : "=r"(cachereg));
> > cpu_drain_writebuf();
> > sets = ((cachereg >> 13) & 0x7fff) + 1;
> > arm_picache_line_size = 1 << ((cachereg & 0x7) + 4);
> > arm_picache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> > -   arm_picache_size = arm_picache_line_size * 
> > arm_picache_ways * sets;
> > +   arm_picache_size =
> > +   arm_picache_line_size * arm_picache_ways * sets;
> > }
> > }
> >  
> > arm_dcache_align = arm_pdcache_line_size;
> > arm_dcache_align_mask = arm_dcache_align - 1;
> >  
> > -   arm_dcache_l2_nsets = 
> > arm_pdcache_size/arm_pdcache_ways/arm_pdcache_line_size;
> > +   arm_dcache_l2_nsets =
> > +   arm_pdcache_size / arm_pdcache_ways / arm_pdcache_line_size;
> > 

Re: arm/sysreg.h use in C

[Artturi Alm]

On Sat, Jul 01, 2017 at 10:53:14AM +0300, Artturi Alm wrote:
> Hi,
> 
> just in case i didn't make it clear what it is for, here's diff "fixing"
> current uses below, compile-tested.
> 
> -Artturi
> 

Hi,

ping?
Noone up for bikeshedding, or seen useless/worse than handcrafting?
I think this would alleviate from some of the complementary commenting,
regarding the CP15 reg usage, that is currently somewhat of necessity.

-Artturi

> 
> diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
> index c91108e7066..fcb56627af7 100644
> --- a/sys/arch/arm/arm/cpufunc.c
> +++ b/sys/arch/arm/arm/cpufunc.c
> @@ -55,6 +55,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #if defined(PERFCTRS)
>  struct arm_pmc_funcs *arm_pmc;
> @@ -176,8 +177,7 @@ arm_get_cachetype_cp15v7(void)
>   uint32_t sel, level;
>  
>   /* CTR - Cache Type Register */
> - __asm volatile("mrc p15, 0, %0, c0, c0, 1"
> - : "=r" (ctype));
> + __asm volatile("mrc " SR_STR(CP15_CTR(%0)) "\n" : "=r"(ctype));
>  
>   arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
>   arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
> @@ -185,8 +185,8 @@ arm_get_cachetype_cp15v7(void)
>   min(arm_icache_min_line_size, arm_dcache_min_line_size);
>  
>   /* CLIDR - Cache Level ID Register */
> - __asm volatile("mrc p15, 1, %0, c0, c0, 1"
> - : "=r" (cache_level_id) :);
> + __asm volatile("mrc " SR_STR(CP15_CLIDR(%0))
> + : "=r"(cache_level_id));
>   cpu_drain_writebuf();
>  
>   /* L1 Cache available. */
> @@ -201,17 +201,18 @@ arm_get_cachetype_cp15v7(void)
>   cache_level_id & (0x2 << level)) {
>   sel = level << 1 | 0 << 0; /* L1 | unified/data cache */
>   /* CSSELR - Cache Size Selection Register */
> - __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> - :: "r" (sel));
> + __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
> + :: "r"(sel));
>   cpu_drain_writebuf();
>   /* CCSIDR - Cache Size Identification Register */
> - __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> - : "=r" (cachereg) :);
> + __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
> + : "=r"(cachereg));
>   cpu_drain_writebuf();
>   sets = ((cachereg >> 13) & 0x7fff) + 1;
>   arm_pdcache_line_size = 1 << ((cachereg & 0x7) + 4);
>   arm_pdcache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> - arm_pdcache_size = arm_pdcache_line_size * 
> arm_pdcache_ways * sets;
> + arm_pdcache_size =
> + arm_pdcache_line_size * arm_pdcache_ways * sets;
>   switch (cachereg & 0xc000) {
>   case 0x:
>   arm_pcache_type = 0;
> @@ -230,24 +231,26 @@ arm_get_cachetype_cp15v7(void)
>   if (cache_level_id & (0x1 << level)) {
>   sel = level << 1 | 1 << 0; /* L1 | instruction cache */
>   /* CSSELR - Cache Size Selection Register */
> - __asm volatile("mcr p15, 2, %0, c0, c0, 0"
> - :: "r" (sel));
> + __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
> + :: "r"(sel));
>   cpu_drain_writebuf();
>   /* CCSIDR - Cache Size Identification Register */
> - __asm volatile("mrc p15, 1, %0, c0, c0, 0"
> - : "=r" (cachereg) :);
> + __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
> + : "=r"(cachereg));
>   cpu_drain_writebuf();
>   sets = ((cachereg >> 13) & 0x7fff) + 1;
>   arm_picache_line_size = 1 << ((cachereg & 0x7) + 4);
>   arm_picache_ways = ((cachereg >> 3) & 0x3ff) + 1;
> - arm_picache_size = arm_picache_line_size * 
> arm_picache_ways * sets;
> + arm_picache_size =
> + arm_picache_line_size * arm_picache_ways * sets;
>   }
>   }
>  
>   arm_dcache_align = arm_pdcache_line_size;
>   arm_dcache_align_mask = arm_dcache_align - 1;
>  
> - arm_dcache_l2_nsets = 
> arm_pdcache_size/arm_pdcache_ways/arm_pdcache_line_size;
> + arm_dcache_l2_nsets =
> + arm_pdcache_size / arm_pdcache_ways / arm_pdcache_line_size;
>   arm_dcache_l2_assoc = log2(arm_pdcache_ways);
>   arm_dcache_l2_linesize = log2(arm_pdcache_line_size);
>  }
> @@ -255,17 +258,16 @@ arm_get_cachetype_cp15v7(void)
>  /* 
>   */
>  void
> -armv7_idcache_wbinv_all()
> 

Re: arm/sysreg.h use in C

[Artturi Alm]

Hi,

just in case i didn't make it clear what it is for, here's diff "fixing"
current uses below, compile-tested.

-Artturi


diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index c91108e7066..fcb56627af7 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -55,6 +55,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(PERFCTRS)
 struct arm_pmc_funcs *arm_pmc;
@@ -176,8 +177,7 @@ arm_get_cachetype_cp15v7(void)
uint32_t sel, level;
 
/* CTR - Cache Type Register */
-   __asm volatile("mrc p15, 0, %0, c0, c0, 1"
-   : "=r" (ctype));
+   __asm volatile("mrc " SR_STR(CP15_CTR(%0)) "\n" : "=r"(ctype));
 
arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
@@ -185,8 +185,8 @@ arm_get_cachetype_cp15v7(void)
min(arm_icache_min_line_size, arm_dcache_min_line_size);
 
/* CLIDR - Cache Level ID Register */
-   __asm volatile("mrc p15, 1, %0, c0, c0, 1"
-   : "=r" (cache_level_id) :);
+   __asm volatile("mrc " SR_STR(CP15_CLIDR(%0))
+   : "=r"(cache_level_id));
cpu_drain_writebuf();
 
/* L1 Cache available. */
@@ -201,17 +201,18 @@ arm_get_cachetype_cp15v7(void)
cache_level_id & (0x2 << level)) {
sel = level << 1 | 0 << 0; /* L1 | unified/data cache */
/* CSSELR - Cache Size Selection Register */
-   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
-   :: "r" (sel));
+   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
+   :: "r"(sel));
cpu_drain_writebuf();
/* CCSIDR - Cache Size Identification Register */
-   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
-   : "=r" (cachereg) :);
+   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
+   : "=r"(cachereg));
cpu_drain_writebuf();
sets = ((cachereg >> 13) & 0x7fff) + 1;
arm_pdcache_line_size = 1 << ((cachereg & 0x7) + 4);
arm_pdcache_ways = ((cachereg >> 3) & 0x3ff) + 1;
-   arm_pdcache_size = arm_pdcache_line_size * 
arm_pdcache_ways * sets;
+   arm_pdcache_size =
+   arm_pdcache_line_size * arm_pdcache_ways * sets;
switch (cachereg & 0xc000) {
case 0x:
arm_pcache_type = 0;
@@ -230,24 +231,26 @@ arm_get_cachetype_cp15v7(void)
if (cache_level_id & (0x1 << level)) {
sel = level << 1 | 1 << 0; /* L1 | instruction cache */
/* CSSELR - Cache Size Selection Register */
-   __asm volatile("mcr p15, 2, %0, c0, c0, 0"
-   :: "r" (sel));
+   __asm volatile("mcr " SR_STR(CP15_CSSELR(%0)) "\n"
+   :: "r"(sel));
cpu_drain_writebuf();
/* CCSIDR - Cache Size Identification Register */
-   __asm volatile("mrc p15, 1, %0, c0, c0, 0"
-   : "=r" (cachereg) :);
+   __asm volatile("mcr " SR_STR(CP15_CCSIDR(%0)) "\n"
+   : "=r"(cachereg));
cpu_drain_writebuf();
sets = ((cachereg >> 13) & 0x7fff) + 1;
arm_picache_line_size = 1 << ((cachereg & 0x7) + 4);
arm_picache_ways = ((cachereg >> 3) & 0x3ff) + 1;
-   arm_picache_size = arm_picache_line_size * 
arm_picache_ways * sets;
+   arm_picache_size =
+   arm_picache_line_size * arm_picache_ways * sets;
}
}
 
arm_dcache_align = arm_pdcache_line_size;
arm_dcache_align_mask = arm_dcache_align - 1;
 
-   arm_dcache_l2_nsets = 
arm_pdcache_size/arm_pdcache_ways/arm_pdcache_line_size;
+   arm_dcache_l2_nsets =
+   arm_pdcache_size / arm_pdcache_ways / arm_pdcache_line_size;
arm_dcache_l2_assoc = log2(arm_pdcache_ways);
arm_dcache_l2_linesize = log2(arm_pdcache_line_size);
 }
@@ -255,17 +258,16 @@ arm_get_cachetype_cp15v7(void)
 /* 
  */
 void
-armv7_idcache_wbinv_all()
+armv7_idcache_wbinv_all(void)
 {
-   uint32_t arg;
-   arg = 0;
-   __asm volatile("mcr p15, 0, r0, c7, c5, 0" :: "r" (arg));
+   /* Instruction cache invalidate all PoU */
+   __asm volatile("mcr " SR_STR(CP15_ICIALLU) "\n" ::: "memory");
armv7_dcache_wbinv_all();
 }
 
 /* brute force cache flushing */
 void
-armv7_dcache_wbinv_all()

arm/sysreg.h use in C

[Artturi Alm]

Hi,


saw something like this missing:

diff --git a/sys/arch/arm/include/sysreg.h b/sys/arch/arm/include/sysreg.h
index c2aab7d6667..f41a3b362ec 100644
--- a/sys/arch/arm/include/sysreg.h
+++ b/sys/arch/arm/include/sysreg.h
@@ -269,4 +269,20 @@
  */
 #define CP15_CBAR(rr)  p15, 4, rr, c15, c0, 0 /* Configuration Base 
Address Register */
 
+/*
+ * SysRegSTRing-Macro to be used within asm(), to allow using macros above.
+ * like:
+ *
+ * u_int
+ * cpu_mpidr(void)
+ * {
+ * u_int mpidr;
+ * asm volatile("mrc   " SR_STR(CP15_MPIDR(%0)) "\n" : "=r"(mpidr));
+ * return mpidr;
+ * }
+ *
+ */
+#define__SRSTR(...)#__VA_ARGS__
+#defineSR_STR(x)   __SRSTR(x)
+
 #endif /* !MACHINE_SYSREG_H */


now, i'm not certainly suggesting above as is, but just to show it,
and to give something to those who like bikeshedding, i don't care
about the name, nor suggest it would need the comment above.

another _bad_ example of what it would allow:

diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index 65da821b49a..c3e4274ceb3 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -160,7 +160,22 @@ extern u_int cputype;
 #define cpu_id()   cpufuncs.cf_id()
 #definecpu_cpwait()cpufuncs.cf_cpwait()
 
-#define cpu_control(c, s)  cpufuncs.cf_control(c, s)
+#include 
+/*efine cpu_control(c, s)  cpufuncs.cf_control(c, s)*/
+static inline u_int
+cpu_control(u_int clrb, u_int xorb)
+{
+   u_int ov, nv;
+   asm volatile(
+   "mrc" SR_STR(CP15_SCTLR(%0)) "\n"   /* %0 = sctlr; */
+   "bic%1, %0, %2\n"   /* %1 = %0 & ~clrb; */
+   "eor%1, %1, %3\n"   /* %1 ^= xorb; */
+   "teq%0, %1\n"   /* if (%0 != %1) */
+   "mcrne  " SR_STR(CP15_SCTLR(%1)) "\n"   /* sctlr = %1; */
+   : "=r"(ov), "=r"(nv) : "r"(clrb), "r"(xorb) : "memory");
+   return ov;
+}
+
 #define cpu_auxcontrol(c, s)   cpufuncs.cf_auxcontrol(c, s)
 #define cpu_domains(d) cpufuncs.cf_domains(d)
 #define cpu_setttb(t)  cpufuncs.cf_setttb(t)


the above is bad, esp. in placement, because whoever goes out to rewrite
cpufuncs out of armv7, or anything like that, should imo. do it into
arch/armv7/ fwiw. to not carry the various licenses involved any further
as remains of unnecessary abstraction.

anyway, the first diff would be usable in current as is making the various
CP15 uses more readable etc. when applied where possible.

-Artturi